2 * $Id: asic.c,v 1.9 2005-12-26 10:48:55 nkeynes Exp $
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE asic_module
26 #include "dreamcast.h"
27 #include "maple/maple.h"
28 #include "gdrom/ide.h"
34 * 1) Does changing the mask after event occurance result in the
35 * interrupt being delivered immediately?
36 * TODO: Logic diagram of ASIC event/interrupt logic.
38 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
39 * practically nothing is publicly known...
42 struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
45 void asic_check_cleared_events( void );
47 void asic_init( void )
49 register_io_region( &mmio_region_ASIC );
50 register_io_region( &mmio_region_EXTDMA );
51 mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
52 asic_event( EVENT_GDROM_CMD );
55 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
61 /* Clear any interrupts */
62 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
63 asic_check_cleared_events();
66 MMIO_WRITE( ASIC, reg, val );
68 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
69 WARN( "Maple request initiated at %08X, halting", maple_addr );
70 maple_handle_buffer( maple_addr );
71 MMIO_WRITE( ASIC, reg, 0 );
76 MMIO_WRITE( ASIC, reg, val );
77 WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
78 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
82 int32_t mmio_region_ASIC_read( uint32_t reg )
94 val = MMIO_READ(ASIC, reg);
95 // WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
96 // reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
99 return 0; /* find out later if there's any cases we actually need to care about */
101 val = MMIO_READ(ASIC, reg);
102 WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
103 reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
109 void asic_event( int event )
111 int offset = ((event&0x60)>>3);
112 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
114 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
115 intc_raise_interrupt( INT_IRQ13 );
116 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
117 intc_raise_interrupt( INT_IRQ11 );
118 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
119 intc_raise_interrupt( INT_IRQ9 );
122 void asic_check_cleared_events( )
124 int i, setA = 0, setB = 0, setC = 0;
126 for( i=0; i<3; i++ ) {
127 bits = MMIO_READ( ASIC, PIRQ0 + i );
128 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
129 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
130 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
133 intc_clear_interrupt( INT_IRQ13 );
135 intc_clear_interrupt( INT_IRQ11 );
137 intc_clear_interrupt( INT_IRQ9 );
141 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
144 case IDEALTSTATUS: /* Device control */
145 ide_write_control( val );
148 ide_write_data_pio( val );
151 if( ide_can_write_regs() )
152 idereg.feature = (uint8_t)val;
155 if( ide_can_write_regs() )
156 idereg.count = (uint8_t)val;
159 if( ide_can_write_regs() )
160 idereg.lba0 = (uint8_t)val;
163 if( ide_can_write_regs() )
164 idereg.lba1 = (uint8_t)val;
167 if( ide_can_write_regs() )
168 idereg.lba2 = (uint8_t)val;
171 if( ide_can_write_regs() )
172 idereg.device = (uint8_t)val;
175 if( ide_can_write_regs() ) {
176 ide_clear_interrupt();
177 ide_write_command( (uint8_t)val );
182 MMIO_WRITE( EXTDMA, reg, val );
186 MMIO_REGION_READ_FN( EXTDMA, reg )
189 case IDEALTSTATUS: return idereg.status;
190 case IDEDATA: return ide_read_data_pio( );
191 case IDEFEAT: return idereg.error;
192 case IDECOUNT:return idereg.count;
193 case IDELBA0: return idereg.disc;
194 case IDELBA1: return idereg.lba1;
195 case IDELBA2: return idereg.lba2;
196 case IDEDEV: return idereg.device;
198 ide_clear_interrupt();
199 return idereg.status;
201 return MMIO_READ( EXTDMA, reg );
.