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lxdream.org :: lxdream/src/sh4/sh4x86.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4x86.c
changeset 601:d8d1af0d133c
prev596:dfc0c93d882e
next604:1024c3a9cb88
author nkeynes
date Tue Jan 22 10:11:45 2008 +0000 (14 years ago)
permissions -rw-r--r--
last change Invoke emulator single-step for untranslatable delay slots (and fix a few
related bugs)
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 => x86 translation. This version does no real optimization, it just
     5  * outputs straight-line x86 code - it mainly exists to provide a baseline
     6  * to test the optimizing versions against.
     7  *
     8  * Copyright (c) 2007 Nathan Keynes.
     9  *
    10  * This program is free software; you can redistribute it and/or modify
    11  * it under the terms of the GNU General Public License as published by
    12  * the Free Software Foundation; either version 2 of the License, or
    13  * (at your option) any later version.
    14  *
    15  * This program is distributed in the hope that it will be useful,
    16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18  * GNU General Public License for more details.
    19  */
    21 #include <assert.h>
    22 #include <math.h>
    24 #ifndef NDEBUG
    25 #define DEBUG_JUMPS 1
    26 #endif
    28 #include "sh4/xltcache.h"
    29 #include "sh4/sh4core.h"
    30 #include "sh4/sh4trans.h"
    31 #include "sh4/sh4mmio.h"
    32 #include "sh4/x86op.h"
    33 #include "clock.h"
    35 #define DEFAULT_BACKPATCH_SIZE 4096
    37 struct backpatch_record {
    38     uint32_t *fixup_addr;
    39     uint32_t fixup_icount;
    40     int32_t exc_code;
    41 };
    43 #define MAX_RECOVERY_SIZE 2048
    45 #define DELAY_NONE 0
    46 #define DELAY_PC 1
    47 #define DELAY_PC_PR 2
    49 /** 
    50  * Struct to manage internal translation state. This state is not saved -
    51  * it is only valid between calls to sh4_translate_begin_block() and
    52  * sh4_translate_end_block()
    53  */
    54 struct sh4_x86_state {
    55     int in_delay_slot;
    56     gboolean priv_checked; /* true if we've already checked the cpu mode. */
    57     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
    58     gboolean branch_taken; /* true if we branched unconditionally */
    59     uint32_t block_start_pc;
    60     uint32_t stack_posn;   /* Trace stack height for alignment purposes */
    61     int tstate;
    63     /* mode flags */
    64     gboolean tlb_on; /* True if tlb translation is active */
    66     /* Allocated memory for the (block-wide) back-patch list */
    67     struct backpatch_record *backpatch_list;
    68     uint32_t backpatch_posn;
    69     uint32_t backpatch_size;
    70 };
    72 #define TSTATE_NONE -1
    73 #define TSTATE_O    0
    74 #define TSTATE_C    2
    75 #define TSTATE_E    4
    76 #define TSTATE_NE   5
    77 #define TSTATE_G    0xF
    78 #define TSTATE_GE   0xD
    79 #define TSTATE_A    7
    80 #define TSTATE_AE   3
    82 /** Branch if T is set (either in the current cflags, or in sh4r.t) */
    83 #define JT_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
    84 	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
    85     OP(0x70+sh4_x86.tstate); OP(rel8); \
    86     MARK_JMP(rel8,label)
    87 /** Branch if T is clear (either in the current cflags or in sh4r.t) */
    88 #define JF_rel8(rel8,label) if( sh4_x86.tstate == TSTATE_NONE ) { \
    89 	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
    90     OP(0x70+ (sh4_x86.tstate^1)); OP(rel8); \
    91     MARK_JMP(rel8, label)
    93 static struct sh4_x86_state sh4_x86;
    95 static uint32_t max_int = 0x7FFFFFFF;
    96 static uint32_t min_int = 0x80000000;
    97 static uint32_t save_fcw; /* save value for fpu control word */
    98 static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
   100 void sh4_x86_init()
   101 {
   102     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
   103     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
   104 }
   107 static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
   108 {
   109     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
   110 	sh4_x86.backpatch_size <<= 1;
   111 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
   112 					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
   113 	assert( sh4_x86.backpatch_list != NULL );
   114     }
   115     if( sh4_x86.in_delay_slot ) {
   116 	fixup_pc -= 2;
   117     }
   118     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_addr = (uint32_t *)fixup_addr;
   119     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
   120     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
   121     sh4_x86.backpatch_posn++;
   122 }
   124 /**
   125  * Emit an instruction to load an SH4 reg into a real register
   126  */
   127 static inline void load_reg( int x86reg, int sh4reg ) 
   128 {
   129     /* mov [bp+n], reg */
   130     OP(0x8B);
   131     OP(0x45 + (x86reg<<3));
   132     OP(REG_OFFSET(r[sh4reg]));
   133 }
   135 static inline void load_reg16s( int x86reg, int sh4reg )
   136 {
   137     OP(0x0F);
   138     OP(0xBF);
   139     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   140 }
   142 static inline void load_reg16u( int x86reg, int sh4reg )
   143 {
   144     OP(0x0F);
   145     OP(0xB7);
   146     MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
   148 }
   150 #define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
   151 #define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
   152 /**
   153  * Emit an instruction to load an immediate value into a register
   154  */
   155 static inline void load_imm32( int x86reg, uint32_t value ) {
   156     /* mov #value, reg */
   157     OP(0xB8 + x86reg);
   158     OP32(value);
   159 }
   161 /**
   162  * Load an immediate 64-bit quantity (note: x86-64 only)
   163  */
   164 static inline void load_imm64( int x86reg, uint32_t value ) {
   165     /* mov #value, reg */
   166     REXW();
   167     OP(0xB8 + x86reg);
   168     OP64(value);
   169 }
   172 /**
   173  * Emit an instruction to store an SH4 reg (RN)
   174  */
   175 void static inline store_reg( int x86reg, int sh4reg ) {
   176     /* mov reg, [bp+n] */
   177     OP(0x89);
   178     OP(0x45 + (x86reg<<3));
   179     OP(REG_OFFSET(r[sh4reg]));
   180 }
   182 #define load_fr_bank(bankreg) load_spreg( bankreg, REG_OFFSET(fr_bank))
   184 /**
   185  * Load an FR register (single-precision floating point) into an integer x86
   186  * register (eg for register-to-register moves)
   187  */
   188 void static inline load_fr( int bankreg, int x86reg, int frm )
   189 {
   190     OP(0x8B); OP(0x40+bankreg+(x86reg<<3)); OP((frm^1)<<2);
   191 }
   193 /**
   194  * Store an FR register (single-precision floating point) into an integer x86
   195  * register (eg for register-to-register moves)
   196  */
   197 void static inline store_fr( int bankreg, int x86reg, int frn )
   198 {
   199     OP(0x89);  OP(0x40+bankreg+(x86reg<<3)); OP((frn^1)<<2);
   200 }
   203 /**
   204  * Load a pointer to the back fp back into the specified x86 register. The
   205  * bankreg must have been previously loaded with FPSCR.
   206  * NB: 12 bytes
   207  */
   208 static inline void load_xf_bank( int bankreg )
   209 {
   210     NOT_r32( bankreg );
   211     SHR_imm8_r32( (21 - 6), bankreg ); // Extract bit 21 then *64 for bank size
   212     AND_imm8s_r32( 0x40, bankreg );    // Complete extraction
   213     OP(0x8D); OP(0x44+(bankreg<<3)); OP(0x28+bankreg); OP(REG_OFFSET(fr)); // LEA [ebp+bankreg+disp], bankreg
   214 }
   216 /**
   217  * Update the fr_bank pointer based on the current fpscr value.
   218  */
   219 static inline void update_fr_bank( int fpscrreg )
   220 {
   221     SHR_imm8_r32( (21 - 6), fpscrreg ); // Extract bit 21 then *64 for bank size
   222     AND_imm8s_r32( 0x40, fpscrreg );    // Complete extraction
   223     OP(0x8D); OP(0x44+(fpscrreg<<3)); OP(0x28+fpscrreg); OP(REG_OFFSET(fr)); // LEA [ebp+fpscrreg+disp], fpscrreg
   224     store_spreg( fpscrreg, REG_OFFSET(fr_bank) );
   225 }
   226 /**
   227  * Push FPUL (as a 32-bit float) onto the FPU stack
   228  */
   229 static inline void push_fpul( )
   230 {
   231     OP(0xD9); OP(0x45); OP(R_FPUL);
   232 }
   234 /**
   235  * Pop FPUL (as a 32-bit float) from the FPU stack
   236  */
   237 static inline void pop_fpul( )
   238 {
   239     OP(0xD9); OP(0x5D); OP(R_FPUL);
   240 }
   242 /**
   243  * Push a 32-bit float onto the FPU stack, with bankreg previously loaded
   244  * with the location of the current fp bank.
   245  */
   246 static inline void push_fr( int bankreg, int frm ) 
   247 {
   248     OP(0xD9); OP(0x40 + bankreg); OP((frm^1)<<2);  // FLD.S [bankreg + frm^1*4]
   249 }
   251 /**
   252  * Pop a 32-bit float from the FPU stack and store it back into the fp bank, 
   253  * with bankreg previously loaded with the location of the current fp bank.
   254  */
   255 static inline void pop_fr( int bankreg, int frm )
   256 {
   257     OP(0xD9); OP(0x58 + bankreg); OP((frm^1)<<2); // FST.S [bankreg + frm^1*4]
   258 }
   260 /**
   261  * Push a 64-bit double onto the FPU stack, with bankreg previously loaded
   262  * with the location of the current fp bank.
   263  */
   264 static inline void push_dr( int bankreg, int frm )
   265 {
   266     OP(0xDD); OP(0x40 + bankreg); OP(frm<<2); // FLD.D [bankreg + frm*4]
   267 }
   269 static inline void pop_dr( int bankreg, int frm )
   270 {
   271     OP(0xDD); OP(0x58 + bankreg); OP(frm<<2); // FST.D [bankreg + frm*4]
   272 }
   274 /* Exception checks - Note that all exception checks will clobber EAX */
   276 #define check_priv( ) \
   277     if( !sh4_x86.priv_checked ) { \
   278 	sh4_x86.priv_checked = TRUE;\
   279 	load_spreg( R_EAX, R_SR );\
   280 	AND_imm32_r32( SR_MD, R_EAX );\
   281 	if( sh4_x86.in_delay_slot ) {\
   282 	    JE_exc( EXC_SLOT_ILLEGAL );\
   283 	} else {\
   284 	    JE_exc( EXC_ILLEGAL );\
   285 	}\
   286     }\
   288 #define check_fpuen( ) \
   289     if( !sh4_x86.fpuen_checked ) {\
   290 	sh4_x86.fpuen_checked = TRUE;\
   291 	load_spreg( R_EAX, R_SR );\
   292 	AND_imm32_r32( SR_FD, R_EAX );\
   293 	if( sh4_x86.in_delay_slot ) {\
   294 	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
   295 	} else {\
   296 	    JNE_exc(EXC_FPU_DISABLED);\
   297 	}\
   298     }
   300 #define check_ralign16( x86reg ) \
   301     TEST_imm32_r32( 0x00000001, x86reg ); \
   302     JNE_exc(EXC_DATA_ADDR_READ)
   304 #define check_walign16( x86reg ) \
   305     TEST_imm32_r32( 0x00000001, x86reg ); \
   306     JNE_exc(EXC_DATA_ADDR_WRITE);
   308 #define check_ralign32( x86reg ) \
   309     TEST_imm32_r32( 0x00000003, x86reg ); \
   310     JNE_exc(EXC_DATA_ADDR_READ)
   312 #define check_walign32( x86reg ) \
   313     TEST_imm32_r32( 0x00000003, x86reg ); \
   314     JNE_exc(EXC_DATA_ADDR_WRITE);
   316 #define UNDEF()
   317 #define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
   318 #define MEM_READ_BYTE( addr_reg, value_reg ) call_func1(sh4_read_byte, addr_reg ); MEM_RESULT(value_reg)
   319 #define MEM_READ_WORD( addr_reg, value_reg ) call_func1(sh4_read_word, addr_reg ); MEM_RESULT(value_reg)
   320 #define MEM_READ_LONG( addr_reg, value_reg ) call_func1(sh4_read_long, addr_reg ); MEM_RESULT(value_reg)
   321 #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_func2(sh4_write_byte, addr_reg, value_reg)
   322 #define MEM_WRITE_WORD( addr_reg, value_reg ) call_func2(sh4_write_word, addr_reg, value_reg)
   323 #define MEM_WRITE_LONG( addr_reg, value_reg ) call_func2(sh4_write_long, addr_reg, value_reg)
   325 /**
   326  * Perform MMU translation on the address in addr_reg for a read operation, iff the TLB is turned 
   327  * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
   328  */
   329 #define MMU_TRANSLATE_READ( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
   331 #define MMU_TRANSLATE_READ_EXC( addr_reg, exc_code ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_read, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(exc_code); MEM_RESULT(addr_reg) }
   332 /**
   333  * Perform MMU translation on the address in addr_reg for a write operation, iff the TLB is turned 
   334  * on, otherwise do nothing. Clobbers EAX, ECX and EDX. May raise a TLB exception or address error.
   335  */
   336 #define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
   338 #define MEM_READ_SIZE (CALL_FUNC1_SIZE)
   339 #define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
   340 #define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
   342 #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
   344 /****** Import appropriate calling conventions ******/
   345 #if SH4_TRANSLATOR == TARGET_X86_64
   346 #include "sh4/ia64abi.h"
   347 #else /* SH4_TRANSLATOR == TARGET_X86 */
   348 #ifdef APPLE_BUILD
   349 #include "sh4/ia32mac.h"
   350 #else
   351 #include "sh4/ia32abi.h"
   352 #endif
   353 #endif
   355 uint32_t sh4_translate_end_block_size()
   356 {
   357     if( sh4_x86.backpatch_posn <= 3 ) {
   358 	return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*12);
   359     } else {
   360 	return EPILOGUE_SIZE + 48 + (sh4_x86.backpatch_posn-3)*15;
   361     }
   362 }
   365 /**
   366  * Embed a breakpoint into the generated code
   367  */
   368 void sh4_translate_emit_breakpoint( sh4vma_t pc )
   369 {
   370     load_imm32( R_EAX, pc );
   371     call_func1( sh4_translate_breakpoint_hit, R_EAX );
   372 }
   375 #define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
   377 /**
   378  * Embed a call to sh4_execute_instruction for situations that we
   379  * can't translate (just page-crossing delay slots at the moment).
   380  * Caller is responsible for setting new_pc before calling this function.
   381  *
   382  * Performs:
   383  *   Set PC = endpc
   384  *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
   385  *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
   386  *   Call sh4_execute_instruction
   387  *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
   388  */
   389 void exit_block_emu( sh4vma_t endpc )
   390 {
   391     load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
   392     ADD_r32_sh4r( R_ECX, R_PC );
   394     load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
   395     ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   396     load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
   397     store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
   399     call_func0( sh4_execute_instruction );    
   400     load_spreg( R_EAX, R_PC );
   401     if( sh4_x86.tlb_on ) {
   402 	call_func1(xlat_get_code_by_vma,R_EAX);
   403     } else {
   404 	call_func1(xlat_get_code,R_EAX);
   405     }
   406     AND_imm8s_rptr( 0xFC, R_EAX );
   407     POP_r32(R_EBP);
   408     RET();
   409 } 
   411 /**
   412  * Translate a single instruction. Delayed branches are handled specially
   413  * by translating both branch and delayed instruction as a single unit (as
   414  * 
   415  * The instruction MUST be in the icache (assert check)
   416  *
   417  * @return true if the instruction marks the end of a basic block
   418  * (eg a branch or 
   419  */
   420 uint32_t sh4_translate_instruction( sh4vma_t pc )
   421 {
   422     uint32_t ir;
   423     /* Read instruction from icache */
   424     assert( IS_IN_ICACHE(pc) );
   425     ir = *(uint16_t *)GET_ICACHE_PTR(pc);
   427 	/* PC is not in the current icache - this usually means we're running
   428 	 * with MMU on, and we've gone past the end of the page. And since 
   429 	 * sh4_translate_block is pretty careful about this, it means we're
   430 	 * almost certainly in a delay slot.
   431 	 *
   432 	 * Since we can't assume the page is present (and we can't fault it in
   433 	 * at this point, inline a call to sh4_execute_instruction (with a few
   434 	 * small repairs to cope with the different environment).
   435 	 */
   437     if( !sh4_x86.in_delay_slot ) {
   438 	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
   439     }
   440         switch( (ir&0xF000) >> 12 ) {
   441             case 0x0:
   442                 switch( ir&0xF ) {
   443                     case 0x2:
   444                         switch( (ir&0x80) >> 7 ) {
   445                             case 0x0:
   446                                 switch( (ir&0x70) >> 4 ) {
   447                                     case 0x0:
   448                                         { /* STC SR, Rn */
   449                                         uint32_t Rn = ((ir>>8)&0xF); 
   450                                         check_priv();
   451                                         call_func0(sh4_read_sr);
   452                                         store_reg( R_EAX, Rn );
   453                                         sh4_x86.tstate = TSTATE_NONE;
   454                                         }
   455                                         break;
   456                                     case 0x1:
   457                                         { /* STC GBR, Rn */
   458                                         uint32_t Rn = ((ir>>8)&0xF); 
   459                                         load_spreg( R_EAX, R_GBR );
   460                                         store_reg( R_EAX, Rn );
   461                                         }
   462                                         break;
   463                                     case 0x2:
   464                                         { /* STC VBR, Rn */
   465                                         uint32_t Rn = ((ir>>8)&0xF); 
   466                                         check_priv();
   467                                         load_spreg( R_EAX, R_VBR );
   468                                         store_reg( R_EAX, Rn );
   469                                         sh4_x86.tstate = TSTATE_NONE;
   470                                         }
   471                                         break;
   472                                     case 0x3:
   473                                         { /* STC SSR, Rn */
   474                                         uint32_t Rn = ((ir>>8)&0xF); 
   475                                         check_priv();
   476                                         load_spreg( R_EAX, R_SSR );
   477                                         store_reg( R_EAX, Rn );
   478                                         sh4_x86.tstate = TSTATE_NONE;
   479                                         }
   480                                         break;
   481                                     case 0x4:
   482                                         { /* STC SPC, Rn */
   483                                         uint32_t Rn = ((ir>>8)&0xF); 
   484                                         check_priv();
   485                                         load_spreg( R_EAX, R_SPC );
   486                                         store_reg( R_EAX, Rn );
   487                                         sh4_x86.tstate = TSTATE_NONE;
   488                                         }
   489                                         break;
   490                                     default:
   491                                         UNDEF();
   492                                         break;
   493                                 }
   494                                 break;
   495                             case 0x1:
   496                                 { /* STC Rm_BANK, Rn */
   497                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   498                                 check_priv();
   499                                 load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
   500                                 store_reg( R_EAX, Rn );
   501                                 sh4_x86.tstate = TSTATE_NONE;
   502                                 }
   503                                 break;
   504                         }
   505                         break;
   506                     case 0x3:
   507                         switch( (ir&0xF0) >> 4 ) {
   508                             case 0x0:
   509                                 { /* BSRF Rn */
   510                                 uint32_t Rn = ((ir>>8)&0xF); 
   511                                 if( sh4_x86.in_delay_slot ) {
   512                             	SLOTILLEGAL();
   513                                 } else {
   514                             	load_spreg( R_EAX, R_PC );
   515                             	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
   516                             	store_spreg( R_EAX, R_PR );
   517                             	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
   518                             	store_spreg( R_EAX, R_NEW_PC );
   520                             	sh4_x86.in_delay_slot = DELAY_PC;
   521                             	sh4_x86.tstate = TSTATE_NONE;
   522                             	sh4_x86.branch_taken = TRUE;
   523                             	if( UNTRANSLATABLE(pc+2) ) {
   524                             	    exit_block_emu(pc+2);
   525                             	    return 2;
   526                             	} else {
   527                             	    sh4_translate_instruction( pc + 2 );
   528                             	    exit_block_newpcset(pc+2);
   529                             	    return 4;
   530                             	}
   531                                 }
   532                                 }
   533                                 break;
   534                             case 0x2:
   535                                 { /* BRAF Rn */
   536                                 uint32_t Rn = ((ir>>8)&0xF); 
   537                                 if( sh4_x86.in_delay_slot ) {
   538                             	SLOTILLEGAL();
   539                                 } else {
   540                             	load_spreg( R_EAX, R_PC );
   541                             	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
   542                             	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
   543                             	store_spreg( R_EAX, R_NEW_PC );
   544                             	sh4_x86.in_delay_slot = DELAY_PC;
   545                             	sh4_x86.tstate = TSTATE_NONE;
   546                             	sh4_x86.branch_taken = TRUE;
   547                             	if( UNTRANSLATABLE(pc+2) ) {
   548                             	    exit_block_emu(pc+2);
   549                             	    return 2;
   550                             	} else {
   551                             	    sh4_translate_instruction( pc + 2 );
   552                             	    exit_block_newpcset(pc+2);
   553                             	    return 4;
   554                             	}
   555                                 }
   556                                 }
   557                                 break;
   558                             case 0x8:
   559                                 { /* PREF @Rn */
   560                                 uint32_t Rn = ((ir>>8)&0xF); 
   561                                 load_reg( R_EAX, Rn );
   562                                 MOV_r32_r32( R_EAX, R_ECX );
   563                                 AND_imm32_r32( 0xFC000000, R_EAX );
   564                                 CMP_imm32_r32( 0xE0000000, R_EAX );
   565                                 JNE_rel8(8+CALL_FUNC1_SIZE, end);
   566                                 call_func1( sh4_flush_store_queue, R_ECX );
   567                                 TEST_r32_r32( R_EAX, R_EAX );
   568                                 JE_exc(-1);
   569                                 JMP_TARGET(end);
   570                                 sh4_x86.tstate = TSTATE_NONE;
   571                                 }
   572                                 break;
   573                             case 0x9:
   574                                 { /* OCBI @Rn */
   575                                 uint32_t Rn = ((ir>>8)&0xF); 
   576                                 }
   577                                 break;
   578                             case 0xA:
   579                                 { /* OCBP @Rn */
   580                                 uint32_t Rn = ((ir>>8)&0xF); 
   581                                 }
   582                                 break;
   583                             case 0xB:
   584                                 { /* OCBWB @Rn */
   585                                 uint32_t Rn = ((ir>>8)&0xF); 
   586                                 }
   587                                 break;
   588                             case 0xC:
   589                                 { /* MOVCA.L R0, @Rn */
   590                                 uint32_t Rn = ((ir>>8)&0xF); 
   591                                 load_reg( R_EAX, Rn );
   592                                 check_walign32( R_EAX );
   593                                 MMU_TRANSLATE_WRITE( R_EAX );
   594                                 load_reg( R_EDX, 0 );
   595                                 MEM_WRITE_LONG( R_EAX, R_EDX );
   596                                 sh4_x86.tstate = TSTATE_NONE;
   597                                 }
   598                                 break;
   599                             default:
   600                                 UNDEF();
   601                                 break;
   602                         }
   603                         break;
   604                     case 0x4:
   605                         { /* MOV.B Rm, @(R0, Rn) */
   606                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   607                         load_reg( R_EAX, 0 );
   608                         load_reg( R_ECX, Rn );
   609                         ADD_r32_r32( R_ECX, R_EAX );
   610                         MMU_TRANSLATE_WRITE( R_EAX );
   611                         load_reg( R_EDX, Rm );
   612                         MEM_WRITE_BYTE( R_EAX, R_EDX );
   613                         sh4_x86.tstate = TSTATE_NONE;
   614                         }
   615                         break;
   616                     case 0x5:
   617                         { /* MOV.W Rm, @(R0, Rn) */
   618                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   619                         load_reg( R_EAX, 0 );
   620                         load_reg( R_ECX, Rn );
   621                         ADD_r32_r32( R_ECX, R_EAX );
   622                         check_walign16( R_EAX );
   623                         MMU_TRANSLATE_WRITE( R_EAX );
   624                         load_reg( R_EDX, Rm );
   625                         MEM_WRITE_WORD( R_EAX, R_EDX );
   626                         sh4_x86.tstate = TSTATE_NONE;
   627                         }
   628                         break;
   629                     case 0x6:
   630                         { /* MOV.L Rm, @(R0, Rn) */
   631                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   632                         load_reg( R_EAX, 0 );
   633                         load_reg( R_ECX, Rn );
   634                         ADD_r32_r32( R_ECX, R_EAX );
   635                         check_walign32( R_EAX );
   636                         MMU_TRANSLATE_WRITE( R_EAX );
   637                         load_reg( R_EDX, Rm );
   638                         MEM_WRITE_LONG( R_EAX, R_EDX );
   639                         sh4_x86.tstate = TSTATE_NONE;
   640                         }
   641                         break;
   642                     case 0x7:
   643                         { /* MUL.L Rm, Rn */
   644                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   645                         load_reg( R_EAX, Rm );
   646                         load_reg( R_ECX, Rn );
   647                         MUL_r32( R_ECX );
   648                         store_spreg( R_EAX, R_MACL );
   649                         sh4_x86.tstate = TSTATE_NONE;
   650                         }
   651                         break;
   652                     case 0x8:
   653                         switch( (ir&0xFF0) >> 4 ) {
   654                             case 0x0:
   655                                 { /* CLRT */
   656                                 CLC();
   657                                 SETC_t();
   658                                 sh4_x86.tstate = TSTATE_C;
   659                                 }
   660                                 break;
   661                             case 0x1:
   662                                 { /* SETT */
   663                                 STC();
   664                                 SETC_t();
   665                                 sh4_x86.tstate = TSTATE_C;
   666                                 }
   667                                 break;
   668                             case 0x2:
   669                                 { /* CLRMAC */
   670                                 XOR_r32_r32(R_EAX, R_EAX);
   671                                 store_spreg( R_EAX, R_MACL );
   672                                 store_spreg( R_EAX, R_MACH );
   673                                 sh4_x86.tstate = TSTATE_NONE;
   674                                 }
   675                                 break;
   676                             case 0x3:
   677                                 { /* LDTLB */
   678                                 call_func0( MMU_ldtlb );
   679                                 }
   680                                 break;
   681                             case 0x4:
   682                                 { /* CLRS */
   683                                 CLC();
   684                                 SETC_sh4r(R_S);
   685                                 sh4_x86.tstate = TSTATE_C;
   686                                 }
   687                                 break;
   688                             case 0x5:
   689                                 { /* SETS */
   690                                 STC();
   691                                 SETC_sh4r(R_S);
   692                                 sh4_x86.tstate = TSTATE_C;
   693                                 }
   694                                 break;
   695                             default:
   696                                 UNDEF();
   697                                 break;
   698                         }
   699                         break;
   700                     case 0x9:
   701                         switch( (ir&0xF0) >> 4 ) {
   702                             case 0x0:
   703                                 { /* NOP */
   704                                 /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */
   705                                 }
   706                                 break;
   707                             case 0x1:
   708                                 { /* DIV0U */
   709                                 XOR_r32_r32( R_EAX, R_EAX );
   710                                 store_spreg( R_EAX, R_Q );
   711                                 store_spreg( R_EAX, R_M );
   712                                 store_spreg( R_EAX, R_T );
   713                                 sh4_x86.tstate = TSTATE_C; // works for DIV1
   714                                 }
   715                                 break;
   716                             case 0x2:
   717                                 { /* MOVT Rn */
   718                                 uint32_t Rn = ((ir>>8)&0xF); 
   719                                 load_spreg( R_EAX, R_T );
   720                                 store_reg( R_EAX, Rn );
   721                                 }
   722                                 break;
   723                             default:
   724                                 UNDEF();
   725                                 break;
   726                         }
   727                         break;
   728                     case 0xA:
   729                         switch( (ir&0xF0) >> 4 ) {
   730                             case 0x0:
   731                                 { /* STS MACH, Rn */
   732                                 uint32_t Rn = ((ir>>8)&0xF); 
   733                                 load_spreg( R_EAX, R_MACH );
   734                                 store_reg( R_EAX, Rn );
   735                                 }
   736                                 break;
   737                             case 0x1:
   738                                 { /* STS MACL, Rn */
   739                                 uint32_t Rn = ((ir>>8)&0xF); 
   740                                 load_spreg( R_EAX, R_MACL );
   741                                 store_reg( R_EAX, Rn );
   742                                 }
   743                                 break;
   744                             case 0x2:
   745                                 { /* STS PR, Rn */
   746                                 uint32_t Rn = ((ir>>8)&0xF); 
   747                                 load_spreg( R_EAX, R_PR );
   748                                 store_reg( R_EAX, Rn );
   749                                 }
   750                                 break;
   751                             case 0x3:
   752                                 { /* STC SGR, Rn */
   753                                 uint32_t Rn = ((ir>>8)&0xF); 
   754                                 check_priv();
   755                                 load_spreg( R_EAX, R_SGR );
   756                                 store_reg( R_EAX, Rn );
   757                                 sh4_x86.tstate = TSTATE_NONE;
   758                                 }
   759                                 break;
   760                             case 0x5:
   761                                 { /* STS FPUL, Rn */
   762                                 uint32_t Rn = ((ir>>8)&0xF); 
   763                                 load_spreg( R_EAX, R_FPUL );
   764                                 store_reg( R_EAX, Rn );
   765                                 }
   766                                 break;
   767                             case 0x6:
   768                                 { /* STS FPSCR, Rn */
   769                                 uint32_t Rn = ((ir>>8)&0xF); 
   770                                 load_spreg( R_EAX, R_FPSCR );
   771                                 store_reg( R_EAX, Rn );
   772                                 }
   773                                 break;
   774                             case 0xF:
   775                                 { /* STC DBR, Rn */
   776                                 uint32_t Rn = ((ir>>8)&0xF); 
   777                                 check_priv();
   778                                 load_spreg( R_EAX, R_DBR );
   779                                 store_reg( R_EAX, Rn );
   780                                 sh4_x86.tstate = TSTATE_NONE;
   781                                 }
   782                                 break;
   783                             default:
   784                                 UNDEF();
   785                                 break;
   786                         }
   787                         break;
   788                     case 0xB:
   789                         switch( (ir&0xFF0) >> 4 ) {
   790                             case 0x0:
   791                                 { /* RTS */
   792                                 if( sh4_x86.in_delay_slot ) {
   793                             	SLOTILLEGAL();
   794                                 } else {
   795                             	load_spreg( R_ECX, R_PR );
   796                             	store_spreg( R_ECX, R_NEW_PC );
   797                             	sh4_x86.in_delay_slot = DELAY_PC;
   798                             	sh4_x86.branch_taken = TRUE;
   799                             	if( UNTRANSLATABLE(pc+2) ) {
   800                             	    exit_block_emu(pc+2);
   801                             	    return 2;
   802                             	} else {
   803                             	    sh4_translate_instruction(pc+2);
   804                             	    exit_block_newpcset(pc+2);
   805                             	    return 4;
   806                             	}
   807                                 }
   808                                 }
   809                                 break;
   810                             case 0x1:
   811                                 { /* SLEEP */
   812                                 check_priv();
   813                                 call_func0( sh4_sleep );
   814                                 sh4_x86.tstate = TSTATE_NONE;
   815                                 sh4_x86.in_delay_slot = DELAY_NONE;
   816                                 return 2;
   817                                 }
   818                                 break;
   819                             case 0x2:
   820                                 { /* RTE */
   821                                 if( sh4_x86.in_delay_slot ) {
   822                             	SLOTILLEGAL();
   823                                 } else {
   824                             	check_priv();
   825                             	load_spreg( R_ECX, R_SPC );
   826                             	store_spreg( R_ECX, R_NEW_PC );
   827                             	load_spreg( R_EAX, R_SSR );
   828                             	call_func1( sh4_write_sr, R_EAX );
   829                             	sh4_x86.in_delay_slot = DELAY_PC;
   830                             	sh4_x86.priv_checked = FALSE;
   831                             	sh4_x86.fpuen_checked = FALSE;
   832                             	sh4_x86.tstate = TSTATE_NONE;
   833                             	sh4_x86.branch_taken = TRUE;
   834                             	if( UNTRANSLATABLE(pc+2) ) {
   835                             	    exit_block_emu(pc+2);
   836                             	    return 2;
   837                             	} else {
   838                             	    sh4_translate_instruction(pc+2);
   839                             	    exit_block_newpcset(pc+2);
   840                             	    return 4;
   841                             	}
   842                                 }
   843                                 }
   844                                 break;
   845                             default:
   846                                 UNDEF();
   847                                 break;
   848                         }
   849                         break;
   850                     case 0xC:
   851                         { /* MOV.B @(R0, Rm), Rn */
   852                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   853                         load_reg( R_EAX, 0 );
   854                         load_reg( R_ECX, Rm );
   855                         ADD_r32_r32( R_ECX, R_EAX );
   856                         MMU_TRANSLATE_READ( R_EAX )
   857                         MEM_READ_BYTE( R_EAX, R_EAX );
   858                         store_reg( R_EAX, Rn );
   859                         sh4_x86.tstate = TSTATE_NONE;
   860                         }
   861                         break;
   862                     case 0xD:
   863                         { /* MOV.W @(R0, Rm), Rn */
   864                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   865                         load_reg( R_EAX, 0 );
   866                         load_reg( R_ECX, Rm );
   867                         ADD_r32_r32( R_ECX, R_EAX );
   868                         check_ralign16( R_EAX );
   869                         MMU_TRANSLATE_READ( R_EAX );
   870                         MEM_READ_WORD( R_EAX, R_EAX );
   871                         store_reg( R_EAX, Rn );
   872                         sh4_x86.tstate = TSTATE_NONE;
   873                         }
   874                         break;
   875                     case 0xE:
   876                         { /* MOV.L @(R0, Rm), Rn */
   877                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   878                         load_reg( R_EAX, 0 );
   879                         load_reg( R_ECX, Rm );
   880                         ADD_r32_r32( R_ECX, R_EAX );
   881                         check_ralign32( R_EAX );
   882                         MMU_TRANSLATE_READ( R_EAX );
   883                         MEM_READ_LONG( R_EAX, R_EAX );
   884                         store_reg( R_EAX, Rn );
   885                         sh4_x86.tstate = TSTATE_NONE;
   886                         }
   887                         break;
   888                     case 0xF:
   889                         { /* MAC.L @Rm+, @Rn+ */
   890                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   891                         if( Rm == Rn ) {
   892                     	load_reg( R_EAX, Rm );
   893                     	check_ralign32( R_EAX );
   894                     	MMU_TRANSLATE_READ( R_EAX );
   895                     	PUSH_realigned_r32( R_EAX );
   896                     	load_reg( R_EAX, Rn );
   897                     	ADD_imm8s_r32( 4, R_EAX );
   898                     	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
   899                     	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
   900                     	// Note translate twice in case of page boundaries. Maybe worth
   901                     	// adding a page-boundary check to skip the second translation
   902                         } else {
   903                     	load_reg( R_EAX, Rm );
   904                     	check_ralign32( R_EAX );
   905                     	MMU_TRANSLATE_READ( R_EAX );
   906                     	load_reg( R_ECX, Rn );
   907                     	check_ralign32( R_ECX );
   908                     	PUSH_realigned_r32( R_EAX );
   909                     	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
   910                     	MOV_r32_r32( R_ECX, R_EAX );
   911                     	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
   912                     	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
   913                         }
   914                         MEM_READ_LONG( R_EAX, R_EAX );
   915                         POP_r32( R_ECX );
   916                         PUSH_r32( R_EAX );
   917                         MEM_READ_LONG( R_ECX, R_EAX );
   918                         POP_realigned_r32( R_ECX );
   920                         IMUL_r32( R_ECX );
   921                         ADD_r32_sh4r( R_EAX, R_MACL );
   922                         ADC_r32_sh4r( R_EDX, R_MACH );
   924                         load_spreg( R_ECX, R_S );
   925                         TEST_r32_r32(R_ECX, R_ECX);
   926                         JE_rel8( CALL_FUNC0_SIZE, nosat );
   927                         call_func0( signsat48 );
   928                         JMP_TARGET( nosat );
   929                         sh4_x86.tstate = TSTATE_NONE;
   930                         }
   931                         break;
   932                     default:
   933                         UNDEF();
   934                         break;
   935                 }
   936                 break;
   937             case 0x1:
   938                 { /* MOV.L Rm, @(disp, Rn) */
   939                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   940                 load_reg( R_EAX, Rn );
   941                 ADD_imm32_r32( disp, R_EAX );
   942                 check_walign32( R_EAX );
   943                 MMU_TRANSLATE_WRITE( R_EAX );
   944                 load_reg( R_EDX, Rm );
   945                 MEM_WRITE_LONG( R_EAX, R_EDX );
   946                 sh4_x86.tstate = TSTATE_NONE;
   947                 }
   948                 break;
   949             case 0x2:
   950                 switch( ir&0xF ) {
   951                     case 0x0:
   952                         { /* MOV.B Rm, @Rn */
   953                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   954                         load_reg( R_EAX, Rn );
   955                         MMU_TRANSLATE_WRITE( R_EAX );
   956                         load_reg( R_EDX, Rm );
   957                         MEM_WRITE_BYTE( R_EAX, R_EDX );
   958                         sh4_x86.tstate = TSTATE_NONE;
   959                         }
   960                         break;
   961                     case 0x1:
   962                         { /* MOV.W Rm, @Rn */
   963                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   964                         load_reg( R_EAX, Rn );
   965                         check_walign16( R_EAX );
   966                         MMU_TRANSLATE_WRITE( R_EAX )
   967                         load_reg( R_EDX, Rm );
   968                         MEM_WRITE_WORD( R_EAX, R_EDX );
   969                         sh4_x86.tstate = TSTATE_NONE;
   970                         }
   971                         break;
   972                     case 0x2:
   973                         { /* MOV.L Rm, @Rn */
   974                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   975                         load_reg( R_EAX, Rn );
   976                         check_walign32(R_EAX);
   977                         MMU_TRANSLATE_WRITE( R_EAX );
   978                         load_reg( R_EDX, Rm );
   979                         MEM_WRITE_LONG( R_EAX, R_EDX );
   980                         sh4_x86.tstate = TSTATE_NONE;
   981                         }
   982                         break;
   983                     case 0x4:
   984                         { /* MOV.B Rm, @-Rn */
   985                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   986                         load_reg( R_EAX, Rn );
   987                         ADD_imm8s_r32( -1, R_EAX );
   988                         MMU_TRANSLATE_WRITE( R_EAX );
   989                         load_reg( R_EDX, Rm );
   990                         ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
   991                         MEM_WRITE_BYTE( R_EAX, R_EDX );
   992                         sh4_x86.tstate = TSTATE_NONE;
   993                         }
   994                         break;
   995                     case 0x5:
   996                         { /* MOV.W Rm, @-Rn */
   997                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   998                         load_reg( R_EAX, Rn );
   999                         ADD_imm8s_r32( -2, R_EAX );
  1000                         check_walign16( R_EAX );
  1001                         MMU_TRANSLATE_WRITE( R_EAX );
  1002                         load_reg( R_EDX, Rm );
  1003                         ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
  1004                         MEM_WRITE_WORD( R_EAX, R_EDX );
  1005                         sh4_x86.tstate = TSTATE_NONE;
  1007                         break;
  1008                     case 0x6:
  1009                         { /* MOV.L Rm, @-Rn */
  1010                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1011                         load_reg( R_EAX, Rn );
  1012                         ADD_imm8s_r32( -4, R_EAX );
  1013                         check_walign32( R_EAX );
  1014                         MMU_TRANSLATE_WRITE( R_EAX );
  1015                         load_reg( R_EDX, Rm );
  1016                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1017                         MEM_WRITE_LONG( R_EAX, R_EDX );
  1018                         sh4_x86.tstate = TSTATE_NONE;
  1020                         break;
  1021                     case 0x7:
  1022                         { /* DIV0S Rm, Rn */
  1023                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1024                         load_reg( R_EAX, Rm );
  1025                         load_reg( R_ECX, Rn );
  1026                         SHR_imm8_r32( 31, R_EAX );
  1027                         SHR_imm8_r32( 31, R_ECX );
  1028                         store_spreg( R_EAX, R_M );
  1029                         store_spreg( R_ECX, R_Q );
  1030                         CMP_r32_r32( R_EAX, R_ECX );
  1031                         SETNE_t();
  1032                         sh4_x86.tstate = TSTATE_NE;
  1034                         break;
  1035                     case 0x8:
  1036                         { /* TST Rm, Rn */
  1037                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1038                         load_reg( R_EAX, Rm );
  1039                         load_reg( R_ECX, Rn );
  1040                         TEST_r32_r32( R_EAX, R_ECX );
  1041                         SETE_t();
  1042                         sh4_x86.tstate = TSTATE_E;
  1044                         break;
  1045                     case 0x9:
  1046                         { /* AND Rm, Rn */
  1047                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1048                         load_reg( R_EAX, Rm );
  1049                         load_reg( R_ECX, Rn );
  1050                         AND_r32_r32( R_EAX, R_ECX );
  1051                         store_reg( R_ECX, Rn );
  1052                         sh4_x86.tstate = TSTATE_NONE;
  1054                         break;
  1055                     case 0xA:
  1056                         { /* XOR Rm, Rn */
  1057                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1058                         load_reg( R_EAX, Rm );
  1059                         load_reg( R_ECX, Rn );
  1060                         XOR_r32_r32( R_EAX, R_ECX );
  1061                         store_reg( R_ECX, Rn );
  1062                         sh4_x86.tstate = TSTATE_NONE;
  1064                         break;
  1065                     case 0xB:
  1066                         { /* OR Rm, Rn */
  1067                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1068                         load_reg( R_EAX, Rm );
  1069                         load_reg( R_ECX, Rn );
  1070                         OR_r32_r32( R_EAX, R_ECX );
  1071                         store_reg( R_ECX, Rn );
  1072                         sh4_x86.tstate = TSTATE_NONE;
  1074                         break;
  1075                     case 0xC:
  1076                         { /* CMP/STR Rm, Rn */
  1077                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1078                         load_reg( R_EAX, Rm );
  1079                         load_reg( R_ECX, Rn );
  1080                         XOR_r32_r32( R_ECX, R_EAX );
  1081                         TEST_r8_r8( R_AL, R_AL );
  1082                         JE_rel8(13, target1);
  1083                         TEST_r8_r8( R_AH, R_AH ); // 2
  1084                         JE_rel8(9, target2);
  1085                         SHR_imm8_r32( 16, R_EAX ); // 3
  1086                         TEST_r8_r8( R_AL, R_AL ); // 2
  1087                         JE_rel8(2, target3);
  1088                         TEST_r8_r8( R_AH, R_AH ); // 2
  1089                         JMP_TARGET(target1);
  1090                         JMP_TARGET(target2);
  1091                         JMP_TARGET(target3);
  1092                         SETE_t();
  1093                         sh4_x86.tstate = TSTATE_E;
  1095                         break;
  1096                     case 0xD:
  1097                         { /* XTRCT Rm, Rn */
  1098                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1099                         load_reg( R_EAX, Rm );
  1100                         load_reg( R_ECX, Rn );
  1101                         SHL_imm8_r32( 16, R_EAX );
  1102                         SHR_imm8_r32( 16, R_ECX );
  1103                         OR_r32_r32( R_EAX, R_ECX );
  1104                         store_reg( R_ECX, Rn );
  1105                         sh4_x86.tstate = TSTATE_NONE;
  1107                         break;
  1108                     case 0xE:
  1109                         { /* MULU.W Rm, Rn */
  1110                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1111                         load_reg16u( R_EAX, Rm );
  1112                         load_reg16u( R_ECX, Rn );
  1113                         MUL_r32( R_ECX );
  1114                         store_spreg( R_EAX, R_MACL );
  1115                         sh4_x86.tstate = TSTATE_NONE;
  1117                         break;
  1118                     case 0xF:
  1119                         { /* MULS.W Rm, Rn */
  1120                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1121                         load_reg16s( R_EAX, Rm );
  1122                         load_reg16s( R_ECX, Rn );
  1123                         MUL_r32( R_ECX );
  1124                         store_spreg( R_EAX, R_MACL );
  1125                         sh4_x86.tstate = TSTATE_NONE;
  1127                         break;
  1128                     default:
  1129                         UNDEF();
  1130                         break;
  1132                 break;
  1133             case 0x3:
  1134                 switch( ir&0xF ) {
  1135                     case 0x0:
  1136                         { /* CMP/EQ Rm, Rn */
  1137                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1138                         load_reg( R_EAX, Rm );
  1139                         load_reg( R_ECX, Rn );
  1140                         CMP_r32_r32( R_EAX, R_ECX );
  1141                         SETE_t();
  1142                         sh4_x86.tstate = TSTATE_E;
  1144                         break;
  1145                     case 0x2:
  1146                         { /* CMP/HS Rm, Rn */
  1147                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1148                         load_reg( R_EAX, Rm );
  1149                         load_reg( R_ECX, Rn );
  1150                         CMP_r32_r32( R_EAX, R_ECX );
  1151                         SETAE_t();
  1152                         sh4_x86.tstate = TSTATE_AE;
  1154                         break;
  1155                     case 0x3:
  1156                         { /* CMP/GE Rm, Rn */
  1157                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1158                         load_reg( R_EAX, Rm );
  1159                         load_reg( R_ECX, Rn );
  1160                         CMP_r32_r32( R_EAX, R_ECX );
  1161                         SETGE_t();
  1162                         sh4_x86.tstate = TSTATE_GE;
  1164                         break;
  1165                     case 0x4:
  1166                         { /* DIV1 Rm, Rn */
  1167                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1168                         load_spreg( R_ECX, R_M );
  1169                         load_reg( R_EAX, Rn );
  1170                         if( sh4_x86.tstate != TSTATE_C ) {
  1171                     	LDC_t();
  1173                         RCL1_r32( R_EAX );
  1174                         SETC_r8( R_DL ); // Q'
  1175                         CMP_sh4r_r32( R_Q, R_ECX );
  1176                         JE_rel8(5, mqequal);
  1177                         ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1178                         JMP_rel8(3, end);
  1179                         JMP_TARGET(mqequal);
  1180                         SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  1181                         JMP_TARGET(end);
  1182                         store_reg( R_EAX, Rn ); // Done with Rn now
  1183                         SETC_r8(R_AL); // tmp1
  1184                         XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
  1185                         XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
  1186                         store_spreg( R_ECX, R_Q );
  1187                         XOR_imm8s_r32( 1, R_AL );   // T = !Q'
  1188                         MOVZX_r8_r32( R_AL, R_EAX );
  1189                         store_spreg( R_EAX, R_T );
  1190                         sh4_x86.tstate = TSTATE_NONE;
  1192                         break;
  1193                     case 0x5:
  1194                         { /* DMULU.L Rm, Rn */
  1195                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1196                         load_reg( R_EAX, Rm );
  1197                         load_reg( R_ECX, Rn );
  1198                         MUL_r32(R_ECX);
  1199                         store_spreg( R_EDX, R_MACH );
  1200                         store_spreg( R_EAX, R_MACL );    
  1201                         sh4_x86.tstate = TSTATE_NONE;
  1203                         break;
  1204                     case 0x6:
  1205                         { /* CMP/HI Rm, Rn */
  1206                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1207                         load_reg( R_EAX, Rm );
  1208                         load_reg( R_ECX, Rn );
  1209                         CMP_r32_r32( R_EAX, R_ECX );
  1210                         SETA_t();
  1211                         sh4_x86.tstate = TSTATE_A;
  1213                         break;
  1214                     case 0x7:
  1215                         { /* CMP/GT Rm, Rn */
  1216                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1217                         load_reg( R_EAX, Rm );
  1218                         load_reg( R_ECX, Rn );
  1219                         CMP_r32_r32( R_EAX, R_ECX );
  1220                         SETG_t();
  1221                         sh4_x86.tstate = TSTATE_G;
  1223                         break;
  1224                     case 0x8:
  1225                         { /* SUB Rm, Rn */
  1226                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1227                         load_reg( R_EAX, Rm );
  1228                         load_reg( R_ECX, Rn );
  1229                         SUB_r32_r32( R_EAX, R_ECX );
  1230                         store_reg( R_ECX, Rn );
  1231                         sh4_x86.tstate = TSTATE_NONE;
  1233                         break;
  1234                     case 0xA:
  1235                         { /* SUBC Rm, Rn */
  1236                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1237                         load_reg( R_EAX, Rm );
  1238                         load_reg( R_ECX, Rn );
  1239                         if( sh4_x86.tstate != TSTATE_C ) {
  1240                     	LDC_t();
  1242                         SBB_r32_r32( R_EAX, R_ECX );
  1243                         store_reg( R_ECX, Rn );
  1244                         SETC_t();
  1245                         sh4_x86.tstate = TSTATE_C;
  1247                         break;
  1248                     case 0xB:
  1249                         { /* SUBV Rm, Rn */
  1250                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1251                         load_reg( R_EAX, Rm );
  1252                         load_reg( R_ECX, Rn );
  1253                         SUB_r32_r32( R_EAX, R_ECX );
  1254                         store_reg( R_ECX, Rn );
  1255                         SETO_t();
  1256                         sh4_x86.tstate = TSTATE_O;
  1258                         break;
  1259                     case 0xC:
  1260                         { /* ADD Rm, Rn */
  1261                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1262                         load_reg( R_EAX, Rm );
  1263                         load_reg( R_ECX, Rn );
  1264                         ADD_r32_r32( R_EAX, R_ECX );
  1265                         store_reg( R_ECX, Rn );
  1266                         sh4_x86.tstate = TSTATE_NONE;
  1268                         break;
  1269                     case 0xD:
  1270                         { /* DMULS.L Rm, Rn */
  1271                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1272                         load_reg( R_EAX, Rm );
  1273                         load_reg( R_ECX, Rn );
  1274                         IMUL_r32(R_ECX);
  1275                         store_spreg( R_EDX, R_MACH );
  1276                         store_spreg( R_EAX, R_MACL );
  1277                         sh4_x86.tstate = TSTATE_NONE;
  1279                         break;
  1280                     case 0xE:
  1281                         { /* ADDC Rm, Rn */
  1282                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1283                         if( sh4_x86.tstate != TSTATE_C ) {
  1284                     	LDC_t();
  1286                         load_reg( R_EAX, Rm );
  1287                         load_reg( R_ECX, Rn );
  1288                         ADC_r32_r32( R_EAX, R_ECX );
  1289                         store_reg( R_ECX, Rn );
  1290                         SETC_t();
  1291                         sh4_x86.tstate = TSTATE_C;
  1293                         break;
  1294                     case 0xF:
  1295                         { /* ADDV Rm, Rn */
  1296                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1297                         load_reg( R_EAX, Rm );
  1298                         load_reg( R_ECX, Rn );
  1299                         ADD_r32_r32( R_EAX, R_ECX );
  1300                         store_reg( R_ECX, Rn );
  1301                         SETO_t();
  1302                         sh4_x86.tstate = TSTATE_O;
  1304                         break;
  1305                     default:
  1306                         UNDEF();
  1307                         break;
  1309                 break;
  1310             case 0x4:
  1311                 switch( ir&0xF ) {
  1312                     case 0x0:
  1313                         switch( (ir&0xF0) >> 4 ) {
  1314                             case 0x0:
  1315                                 { /* SHLL Rn */
  1316                                 uint32_t Rn = ((ir>>8)&0xF); 
  1317                                 load_reg( R_EAX, Rn );
  1318                                 SHL1_r32( R_EAX );
  1319                                 SETC_t();
  1320                                 store_reg( R_EAX, Rn );
  1321                                 sh4_x86.tstate = TSTATE_C;
  1323                                 break;
  1324                             case 0x1:
  1325                                 { /* DT Rn */
  1326                                 uint32_t Rn = ((ir>>8)&0xF); 
  1327                                 load_reg( R_EAX, Rn );
  1328                                 ADD_imm8s_r32( -1, R_EAX );
  1329                                 store_reg( R_EAX, Rn );
  1330                                 SETE_t();
  1331                                 sh4_x86.tstate = TSTATE_E;
  1333                                 break;
  1334                             case 0x2:
  1335                                 { /* SHAL Rn */
  1336                                 uint32_t Rn = ((ir>>8)&0xF); 
  1337                                 load_reg( R_EAX, Rn );
  1338                                 SHL1_r32( R_EAX );
  1339                                 SETC_t();
  1340                                 store_reg( R_EAX, Rn );
  1341                                 sh4_x86.tstate = TSTATE_C;
  1343                                 break;
  1344                             default:
  1345                                 UNDEF();
  1346                                 break;
  1348                         break;
  1349                     case 0x1:
  1350                         switch( (ir&0xF0) >> 4 ) {
  1351                             case 0x0:
  1352                                 { /* SHLR Rn */
  1353                                 uint32_t Rn = ((ir>>8)&0xF); 
  1354                                 load_reg( R_EAX, Rn );
  1355                                 SHR1_r32( R_EAX );
  1356                                 SETC_t();
  1357                                 store_reg( R_EAX, Rn );
  1358                                 sh4_x86.tstate = TSTATE_C;
  1360                                 break;
  1361                             case 0x1:
  1362                                 { /* CMP/PZ Rn */
  1363                                 uint32_t Rn = ((ir>>8)&0xF); 
  1364                                 load_reg( R_EAX, Rn );
  1365                                 CMP_imm8s_r32( 0, R_EAX );
  1366                                 SETGE_t();
  1367                                 sh4_x86.tstate = TSTATE_GE;
  1369                                 break;
  1370                             case 0x2:
  1371                                 { /* SHAR Rn */
  1372                                 uint32_t Rn = ((ir>>8)&0xF); 
  1373                                 load_reg( R_EAX, Rn );
  1374                                 SAR1_r32( R_EAX );
  1375                                 SETC_t();
  1376                                 store_reg( R_EAX, Rn );
  1377                                 sh4_x86.tstate = TSTATE_C;
  1379                                 break;
  1380                             default:
  1381                                 UNDEF();
  1382                                 break;
  1384                         break;
  1385                     case 0x2:
  1386                         switch( (ir&0xF0) >> 4 ) {
  1387                             case 0x0:
  1388                                 { /* STS.L MACH, @-Rn */
  1389                                 uint32_t Rn = ((ir>>8)&0xF); 
  1390                                 load_reg( R_EAX, Rn );
  1391                                 check_walign32( R_EAX );
  1392                                 ADD_imm8s_r32( -4, R_EAX );
  1393                                 MMU_TRANSLATE_WRITE( R_EAX );
  1394                                 load_spreg( R_EDX, R_MACH );
  1395                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1396                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1397                                 sh4_x86.tstate = TSTATE_NONE;
  1399                                 break;
  1400                             case 0x1:
  1401                                 { /* STS.L MACL, @-Rn */
  1402                                 uint32_t Rn = ((ir>>8)&0xF); 
  1403                                 load_reg( R_EAX, Rn );
  1404                                 check_walign32( R_EAX );
  1405                                 ADD_imm8s_r32( -4, R_EAX );
  1406                                 MMU_TRANSLATE_WRITE( R_EAX );
  1407                                 load_spreg( R_EDX, R_MACL );
  1408                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1409                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1410                                 sh4_x86.tstate = TSTATE_NONE;
  1412                                 break;
  1413                             case 0x2:
  1414                                 { /* STS.L PR, @-Rn */
  1415                                 uint32_t Rn = ((ir>>8)&0xF); 
  1416                                 load_reg( R_EAX, Rn );
  1417                                 check_walign32( R_EAX );
  1418                                 ADD_imm8s_r32( -4, R_EAX );
  1419                                 MMU_TRANSLATE_WRITE( R_EAX );
  1420                                 load_spreg( R_EDX, R_PR );
  1421                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1422                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1423                                 sh4_x86.tstate = TSTATE_NONE;
  1425                                 break;
  1426                             case 0x3:
  1427                                 { /* STC.L SGR, @-Rn */
  1428                                 uint32_t Rn = ((ir>>8)&0xF); 
  1429                                 check_priv();
  1430                                 load_reg( R_EAX, Rn );
  1431                                 check_walign32( R_EAX );
  1432                                 ADD_imm8s_r32( -4, R_EAX );
  1433                                 MMU_TRANSLATE_WRITE( R_EAX );
  1434                                 load_spreg( R_EDX, R_SGR );
  1435                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1436                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1437                                 sh4_x86.tstate = TSTATE_NONE;
  1439                                 break;
  1440                             case 0x5:
  1441                                 { /* STS.L FPUL, @-Rn */
  1442                                 uint32_t Rn = ((ir>>8)&0xF); 
  1443                                 load_reg( R_EAX, Rn );
  1444                                 check_walign32( R_EAX );
  1445                                 ADD_imm8s_r32( -4, R_EAX );
  1446                                 MMU_TRANSLATE_WRITE( R_EAX );
  1447                                 load_spreg( R_EDX, R_FPUL );
  1448                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1449                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1450                                 sh4_x86.tstate = TSTATE_NONE;
  1452                                 break;
  1453                             case 0x6:
  1454                                 { /* STS.L FPSCR, @-Rn */
  1455                                 uint32_t Rn = ((ir>>8)&0xF); 
  1456                                 load_reg( R_EAX, Rn );
  1457                                 check_walign32( R_EAX );
  1458                                 ADD_imm8s_r32( -4, R_EAX );
  1459                                 MMU_TRANSLATE_WRITE( R_EAX );
  1460                                 load_spreg( R_EDX, R_FPSCR );
  1461                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1462                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1463                                 sh4_x86.tstate = TSTATE_NONE;
  1465                                 break;
  1466                             case 0xF:
  1467                                 { /* STC.L DBR, @-Rn */
  1468                                 uint32_t Rn = ((ir>>8)&0xF); 
  1469                                 check_priv();
  1470                                 load_reg( R_EAX, Rn );
  1471                                 check_walign32( R_EAX );
  1472                                 ADD_imm8s_r32( -4, R_EAX );
  1473                                 MMU_TRANSLATE_WRITE( R_EAX );
  1474                                 load_spreg( R_EDX, R_DBR );
  1475                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1476                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1477                                 sh4_x86.tstate = TSTATE_NONE;
  1479                                 break;
  1480                             default:
  1481                                 UNDEF();
  1482                                 break;
  1484                         break;
  1485                     case 0x3:
  1486                         switch( (ir&0x80) >> 7 ) {
  1487                             case 0x0:
  1488                                 switch( (ir&0x70) >> 4 ) {
  1489                                     case 0x0:
  1490                                         { /* STC.L SR, @-Rn */
  1491                                         uint32_t Rn = ((ir>>8)&0xF); 
  1492                                         check_priv();
  1493                                         load_reg( R_EAX, Rn );
  1494                                         check_walign32( R_EAX );
  1495                                         ADD_imm8s_r32( -4, R_EAX );
  1496                                         MMU_TRANSLATE_WRITE( R_EAX );
  1497                                         PUSH_realigned_r32( R_EAX );
  1498                                         call_func0( sh4_read_sr );
  1499                                         POP_realigned_r32( R_ECX );
  1500                                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1501                                         MEM_WRITE_LONG( R_ECX, R_EAX );
  1502                                         sh4_x86.tstate = TSTATE_NONE;
  1504                                         break;
  1505                                     case 0x1:
  1506                                         { /* STC.L GBR, @-Rn */
  1507                                         uint32_t Rn = ((ir>>8)&0xF); 
  1508                                         load_reg( R_EAX, Rn );
  1509                                         check_walign32( R_EAX );
  1510                                         ADD_imm8s_r32( -4, R_EAX );
  1511                                         MMU_TRANSLATE_WRITE( R_EAX );
  1512                                         load_spreg( R_EDX, R_GBR );
  1513                                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1514                                         MEM_WRITE_LONG( R_EAX, R_EDX );
  1515                                         sh4_x86.tstate = TSTATE_NONE;
  1517                                         break;
  1518                                     case 0x2:
  1519                                         { /* STC.L VBR, @-Rn */
  1520                                         uint32_t Rn = ((ir>>8)&0xF); 
  1521                                         check_priv();
  1522                                         load_reg( R_EAX, Rn );
  1523                                         check_walign32( R_EAX );
  1524                                         ADD_imm8s_r32( -4, R_EAX );
  1525                                         MMU_TRANSLATE_WRITE( R_EAX );
  1526                                         load_spreg( R_EDX, R_VBR );
  1527                                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1528                                         MEM_WRITE_LONG( R_EAX, R_EDX );
  1529                                         sh4_x86.tstate = TSTATE_NONE;
  1531                                         break;
  1532                                     case 0x3:
  1533                                         { /* STC.L SSR, @-Rn */
  1534                                         uint32_t Rn = ((ir>>8)&0xF); 
  1535                                         check_priv();
  1536                                         load_reg( R_EAX, Rn );
  1537                                         check_walign32( R_EAX );
  1538                                         ADD_imm8s_r32( -4, R_EAX );
  1539                                         MMU_TRANSLATE_WRITE( R_EAX );
  1540                                         load_spreg( R_EDX, R_SSR );
  1541                                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1542                                         MEM_WRITE_LONG( R_EAX, R_EDX );
  1543                                         sh4_x86.tstate = TSTATE_NONE;
  1545                                         break;
  1546                                     case 0x4:
  1547                                         { /* STC.L SPC, @-Rn */
  1548                                         uint32_t Rn = ((ir>>8)&0xF); 
  1549                                         check_priv();
  1550                                         load_reg( R_EAX, Rn );
  1551                                         check_walign32( R_EAX );
  1552                                         ADD_imm8s_r32( -4, R_EAX );
  1553                                         MMU_TRANSLATE_WRITE( R_EAX );
  1554                                         load_spreg( R_EDX, R_SPC );
  1555                                         ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1556                                         MEM_WRITE_LONG( R_EAX, R_EDX );
  1557                                         sh4_x86.tstate = TSTATE_NONE;
  1559                                         break;
  1560                                     default:
  1561                                         UNDEF();
  1562                                         break;
  1564                                 break;
  1565                             case 0x1:
  1566                                 { /* STC.L Rm_BANK, @-Rn */
  1567                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1568                                 check_priv();
  1569                                 load_reg( R_EAX, Rn );
  1570                                 check_walign32( R_EAX );
  1571                                 ADD_imm8s_r32( -4, R_EAX );
  1572                                 MMU_TRANSLATE_WRITE( R_EAX );
  1573                                 load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
  1574                                 ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
  1575                                 MEM_WRITE_LONG( R_EAX, R_EDX );
  1576                                 sh4_x86.tstate = TSTATE_NONE;
  1578                                 break;
  1580                         break;
  1581                     case 0x4:
  1582                         switch( (ir&0xF0) >> 4 ) {
  1583                             case 0x0:
  1584                                 { /* ROTL Rn */
  1585                                 uint32_t Rn = ((ir>>8)&0xF); 
  1586                                 load_reg( R_EAX, Rn );
  1587                                 ROL1_r32( R_EAX );
  1588                                 store_reg( R_EAX, Rn );
  1589                                 SETC_t();
  1590                                 sh4_x86.tstate = TSTATE_C;
  1592                                 break;
  1593                             case 0x2:
  1594                                 { /* ROTCL Rn */
  1595                                 uint32_t Rn = ((ir>>8)&0xF); 
  1596                                 load_reg( R_EAX, Rn );
  1597                                 if( sh4_x86.tstate != TSTATE_C ) {
  1598                             	LDC_t();
  1600                                 RCL1_r32( R_EAX );
  1601                                 store_reg( R_EAX, Rn );
  1602                                 SETC_t();
  1603                                 sh4_x86.tstate = TSTATE_C;
  1605                                 break;
  1606                             default:
  1607                                 UNDEF();
  1608                                 break;
  1610                         break;
  1611                     case 0x5:
  1612                         switch( (ir&0xF0) >> 4 ) {
  1613                             case 0x0:
  1614                                 { /* ROTR Rn */
  1615                                 uint32_t Rn = ((ir>>8)&0xF); 
  1616                                 load_reg( R_EAX, Rn );
  1617                                 ROR1_r32( R_EAX );
  1618                                 store_reg( R_EAX, Rn );
  1619                                 SETC_t();
  1620                                 sh4_x86.tstate = TSTATE_C;
  1622                                 break;
  1623                             case 0x1:
  1624                                 { /* CMP/PL Rn */
  1625                                 uint32_t Rn = ((ir>>8)&0xF); 
  1626                                 load_reg( R_EAX, Rn );
  1627                                 CMP_imm8s_r32( 0, R_EAX );
  1628                                 SETG_t();
  1629                                 sh4_x86.tstate = TSTATE_G;
  1631                                 break;
  1632                             case 0x2:
  1633                                 { /* ROTCR Rn */
  1634                                 uint32_t Rn = ((ir>>8)&0xF); 
  1635                                 load_reg( R_EAX, Rn );
  1636                                 if( sh4_x86.tstate != TSTATE_C ) {
  1637                             	LDC_t();
  1639                                 RCR1_r32( R_EAX );
  1640                                 store_reg( R_EAX, Rn );
  1641                                 SETC_t();
  1642                                 sh4_x86.tstate = TSTATE_C;
  1644                                 break;
  1645                             default:
  1646                                 UNDEF();
  1647                                 break;
  1649                         break;
  1650                     case 0x6:
  1651                         switch( (ir&0xF0) >> 4 ) {
  1652                             case 0x0:
  1653                                 { /* LDS.L @Rm+, MACH */
  1654                                 uint32_t Rm = ((ir>>8)&0xF); 
  1655                                 load_reg( R_EAX, Rm );
  1656                                 check_ralign32( R_EAX );
  1657                                 MMU_TRANSLATE_READ( R_EAX );
  1658                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1659                                 MEM_READ_LONG( R_EAX, R_EAX );
  1660                                 store_spreg( R_EAX, R_MACH );
  1661                                 sh4_x86.tstate = TSTATE_NONE;
  1663                                 break;
  1664                             case 0x1:
  1665                                 { /* LDS.L @Rm+, MACL */
  1666                                 uint32_t Rm = ((ir>>8)&0xF); 
  1667                                 load_reg( R_EAX, Rm );
  1668                                 check_ralign32( R_EAX );
  1669                                 MMU_TRANSLATE_READ( R_EAX );
  1670                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1671                                 MEM_READ_LONG( R_EAX, R_EAX );
  1672                                 store_spreg( R_EAX, R_MACL );
  1673                                 sh4_x86.tstate = TSTATE_NONE;
  1675                                 break;
  1676                             case 0x2:
  1677                                 { /* LDS.L @Rm+, PR */
  1678                                 uint32_t Rm = ((ir>>8)&0xF); 
  1679                                 load_reg( R_EAX, Rm );
  1680                                 check_ralign32( R_EAX );
  1681                                 MMU_TRANSLATE_READ( R_EAX );
  1682                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1683                                 MEM_READ_LONG( R_EAX, R_EAX );
  1684                                 store_spreg( R_EAX, R_PR );
  1685                                 sh4_x86.tstate = TSTATE_NONE;
  1687                                 break;
  1688                             case 0x3:
  1689                                 { /* LDC.L @Rm+, SGR */
  1690                                 uint32_t Rm = ((ir>>8)&0xF); 
  1691                                 check_priv();
  1692                                 load_reg( R_EAX, Rm );
  1693                                 check_ralign32( R_EAX );
  1694                                 MMU_TRANSLATE_READ( R_EAX );
  1695                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1696                                 MEM_READ_LONG( R_EAX, R_EAX );
  1697                                 store_spreg( R_EAX, R_SGR );
  1698                                 sh4_x86.tstate = TSTATE_NONE;
  1700                                 break;
  1701                             case 0x5:
  1702                                 { /* LDS.L @Rm+, FPUL */
  1703                                 uint32_t Rm = ((ir>>8)&0xF); 
  1704                                 load_reg( R_EAX, Rm );
  1705                                 check_ralign32( R_EAX );
  1706                                 MMU_TRANSLATE_READ( R_EAX );
  1707                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1708                                 MEM_READ_LONG( R_EAX, R_EAX );
  1709                                 store_spreg( R_EAX, R_FPUL );
  1710                                 sh4_x86.tstate = TSTATE_NONE;
  1712                                 break;
  1713                             case 0x6:
  1714                                 { /* LDS.L @Rm+, FPSCR */
  1715                                 uint32_t Rm = ((ir>>8)&0xF); 
  1716                                 load_reg( R_EAX, Rm );
  1717                                 check_ralign32( R_EAX );
  1718                                 MMU_TRANSLATE_READ( R_EAX );
  1719                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1720                                 MEM_READ_LONG( R_EAX, R_EAX );
  1721                                 store_spreg( R_EAX, R_FPSCR );
  1722                                 update_fr_bank( R_EAX );
  1723                                 sh4_x86.tstate = TSTATE_NONE;
  1725                                 break;
  1726                             case 0xF:
  1727                                 { /* LDC.L @Rm+, DBR */
  1728                                 uint32_t Rm = ((ir>>8)&0xF); 
  1729                                 check_priv();
  1730                                 load_reg( R_EAX, Rm );
  1731                                 check_ralign32( R_EAX );
  1732                                 MMU_TRANSLATE_READ( R_EAX );
  1733                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1734                                 MEM_READ_LONG( R_EAX, R_EAX );
  1735                                 store_spreg( R_EAX, R_DBR );
  1736                                 sh4_x86.tstate = TSTATE_NONE;
  1738                                 break;
  1739                             default:
  1740                                 UNDEF();
  1741                                 break;
  1743                         break;
  1744                     case 0x7:
  1745                         switch( (ir&0x80) >> 7 ) {
  1746                             case 0x0:
  1747                                 switch( (ir&0x70) >> 4 ) {
  1748                                     case 0x0:
  1749                                         { /* LDC.L @Rm+, SR */
  1750                                         uint32_t Rm = ((ir>>8)&0xF); 
  1751                                         if( sh4_x86.in_delay_slot ) {
  1752                                     	SLOTILLEGAL();
  1753                                         } else {
  1754                                     	check_priv();
  1755                                     	load_reg( R_EAX, Rm );
  1756                                     	check_ralign32( R_EAX );
  1757                                     	MMU_TRANSLATE_READ( R_EAX );
  1758                                     	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1759                                     	MEM_READ_LONG( R_EAX, R_EAX );
  1760                                     	call_func1( sh4_write_sr, R_EAX );
  1761                                     	sh4_x86.priv_checked = FALSE;
  1762                                     	sh4_x86.fpuen_checked = FALSE;
  1763                                     	sh4_x86.tstate = TSTATE_NONE;
  1766                                         break;
  1767                                     case 0x1:
  1768                                         { /* LDC.L @Rm+, GBR */
  1769                                         uint32_t Rm = ((ir>>8)&0xF); 
  1770                                         load_reg( R_EAX, Rm );
  1771                                         check_ralign32( R_EAX );
  1772                                         MMU_TRANSLATE_READ( R_EAX );
  1773                                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1774                                         MEM_READ_LONG( R_EAX, R_EAX );
  1775                                         store_spreg( R_EAX, R_GBR );
  1776                                         sh4_x86.tstate = TSTATE_NONE;
  1778                                         break;
  1779                                     case 0x2:
  1780                                         { /* LDC.L @Rm+, VBR */
  1781                                         uint32_t Rm = ((ir>>8)&0xF); 
  1782                                         check_priv();
  1783                                         load_reg( R_EAX, Rm );
  1784                                         check_ralign32( R_EAX );
  1785                                         MMU_TRANSLATE_READ( R_EAX );
  1786                                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1787                                         MEM_READ_LONG( R_EAX, R_EAX );
  1788                                         store_spreg( R_EAX, R_VBR );
  1789                                         sh4_x86.tstate = TSTATE_NONE;
  1791                                         break;
  1792                                     case 0x3:
  1793                                         { /* LDC.L @Rm+, SSR */
  1794                                         uint32_t Rm = ((ir>>8)&0xF); 
  1795                                         check_priv();
  1796                                         load_reg( R_EAX, Rm );
  1797                                         check_ralign32( R_EAX );
  1798                                         MMU_TRANSLATE_READ( R_EAX );
  1799                                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1800                                         MEM_READ_LONG( R_EAX, R_EAX );
  1801                                         store_spreg( R_EAX, R_SSR );
  1802                                         sh4_x86.tstate = TSTATE_NONE;
  1804                                         break;
  1805                                     case 0x4:
  1806                                         { /* LDC.L @Rm+, SPC */
  1807                                         uint32_t Rm = ((ir>>8)&0xF); 
  1808                                         check_priv();
  1809                                         load_reg( R_EAX, Rm );
  1810                                         check_ralign32( R_EAX );
  1811                                         MMU_TRANSLATE_READ( R_EAX );
  1812                                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1813                                         MEM_READ_LONG( R_EAX, R_EAX );
  1814                                         store_spreg( R_EAX, R_SPC );
  1815                                         sh4_x86.tstate = TSTATE_NONE;
  1817                                         break;
  1818                                     default:
  1819                                         UNDEF();
  1820                                         break;
  1822                                 break;
  1823                             case 0x1:
  1824                                 { /* LDC.L @Rm+, Rn_BANK */
  1825                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1826                                 check_priv();
  1827                                 load_reg( R_EAX, Rm );
  1828                                 check_ralign32( R_EAX );
  1829                                 MMU_TRANSLATE_READ( R_EAX );
  1830                                 ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  1831                                 MEM_READ_LONG( R_EAX, R_EAX );
  1832                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  1833                                 sh4_x86.tstate = TSTATE_NONE;
  1835                                 break;
  1837                         break;
  1838                     case 0x8:
  1839                         switch( (ir&0xF0) >> 4 ) {
  1840                             case 0x0:
  1841                                 { /* SHLL2 Rn */
  1842                                 uint32_t Rn = ((ir>>8)&0xF); 
  1843                                 load_reg( R_EAX, Rn );
  1844                                 SHL_imm8_r32( 2, R_EAX );
  1845                                 store_reg( R_EAX, Rn );
  1846                                 sh4_x86.tstate = TSTATE_NONE;
  1848                                 break;
  1849                             case 0x1:
  1850                                 { /* SHLL8 Rn */
  1851                                 uint32_t Rn = ((ir>>8)&0xF); 
  1852                                 load_reg( R_EAX, Rn );
  1853                                 SHL_imm8_r32( 8, R_EAX );
  1854                                 store_reg( R_EAX, Rn );
  1855                                 sh4_x86.tstate = TSTATE_NONE;
  1857                                 break;
  1858                             case 0x2:
  1859                                 { /* SHLL16 Rn */
  1860                                 uint32_t Rn = ((ir>>8)&0xF); 
  1861                                 load_reg( R_EAX, Rn );
  1862                                 SHL_imm8_r32( 16, R_EAX );
  1863                                 store_reg( R_EAX, Rn );
  1864                                 sh4_x86.tstate = TSTATE_NONE;
  1866                                 break;
  1867                             default:
  1868                                 UNDEF();
  1869                                 break;
  1871                         break;
  1872                     case 0x9:
  1873                         switch( (ir&0xF0) >> 4 ) {
  1874                             case 0x0:
  1875                                 { /* SHLR2 Rn */
  1876                                 uint32_t Rn = ((ir>>8)&0xF); 
  1877                                 load_reg( R_EAX, Rn );
  1878                                 SHR_imm8_r32( 2, R_EAX );
  1879                                 store_reg( R_EAX, Rn );
  1880                                 sh4_x86.tstate = TSTATE_NONE;
  1882                                 break;
  1883                             case 0x1:
  1884                                 { /* SHLR8 Rn */
  1885                                 uint32_t Rn = ((ir>>8)&0xF); 
  1886                                 load_reg( R_EAX, Rn );
  1887                                 SHR_imm8_r32( 8, R_EAX );
  1888                                 store_reg( R_EAX, Rn );
  1889                                 sh4_x86.tstate = TSTATE_NONE;
  1891                                 break;
  1892                             case 0x2:
  1893                                 { /* SHLR16 Rn */
  1894                                 uint32_t Rn = ((ir>>8)&0xF); 
  1895                                 load_reg( R_EAX, Rn );
  1896                                 SHR_imm8_r32( 16, R_EAX );
  1897                                 store_reg( R_EAX, Rn );
  1898                                 sh4_x86.tstate = TSTATE_NONE;
  1900                                 break;
  1901                             default:
  1902                                 UNDEF();
  1903                                 break;
  1905                         break;
  1906                     case 0xA:
  1907                         switch( (ir&0xF0) >> 4 ) {
  1908                             case 0x0:
  1909                                 { /* LDS Rm, MACH */
  1910                                 uint32_t Rm = ((ir>>8)&0xF); 
  1911                                 load_reg( R_EAX, Rm );
  1912                                 store_spreg( R_EAX, R_MACH );
  1914                                 break;
  1915                             case 0x1:
  1916                                 { /* LDS Rm, MACL */
  1917                                 uint32_t Rm = ((ir>>8)&0xF); 
  1918                                 load_reg( R_EAX, Rm );
  1919                                 store_spreg( R_EAX, R_MACL );
  1921                                 break;
  1922                             case 0x2:
  1923                                 { /* LDS Rm, PR */
  1924                                 uint32_t Rm = ((ir>>8)&0xF); 
  1925                                 load_reg( R_EAX, Rm );
  1926                                 store_spreg( R_EAX, R_PR );
  1928                                 break;
  1929                             case 0x3:
  1930                                 { /* LDC Rm, SGR */
  1931                                 uint32_t Rm = ((ir>>8)&0xF); 
  1932                                 check_priv();
  1933                                 load_reg( R_EAX, Rm );
  1934                                 store_spreg( R_EAX, R_SGR );
  1935                                 sh4_x86.tstate = TSTATE_NONE;
  1937                                 break;
  1938                             case 0x5:
  1939                                 { /* LDS Rm, FPUL */
  1940                                 uint32_t Rm = ((ir>>8)&0xF); 
  1941                                 load_reg( R_EAX, Rm );
  1942                                 store_spreg( R_EAX, R_FPUL );
  1944                                 break;
  1945                             case 0x6:
  1946                                 { /* LDS Rm, FPSCR */
  1947                                 uint32_t Rm = ((ir>>8)&0xF); 
  1948                                 load_reg( R_EAX, Rm );
  1949                                 store_spreg( R_EAX, R_FPSCR );
  1950                                 update_fr_bank( R_EAX );
  1951                                 sh4_x86.tstate = TSTATE_NONE;
  1953                                 break;
  1954                             case 0xF:
  1955                                 { /* LDC Rm, DBR */
  1956                                 uint32_t Rm = ((ir>>8)&0xF); 
  1957                                 check_priv();
  1958                                 load_reg( R_EAX, Rm );
  1959                                 store_spreg( R_EAX, R_DBR );
  1960                                 sh4_x86.tstate = TSTATE_NONE;
  1962                                 break;
  1963                             default:
  1964                                 UNDEF();
  1965                                 break;
  1967                         break;
  1968                     case 0xB:
  1969                         switch( (ir&0xF0) >> 4 ) {
  1970                             case 0x0:
  1971                                 { /* JSR @Rn */
  1972                                 uint32_t Rn = ((ir>>8)&0xF); 
  1973                                 if( sh4_x86.in_delay_slot ) {
  1974                             	SLOTILLEGAL();
  1975                                 } else {
  1976                             	load_spreg( R_EAX, R_PC );
  1977                             	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
  1978                             	store_spreg( R_EAX, R_PR );
  1979                             	load_reg( R_ECX, Rn );
  1980                             	store_spreg( R_ECX, R_NEW_PC );
  1981                             	sh4_x86.in_delay_slot = DELAY_PC;
  1982                             	sh4_x86.branch_taken = TRUE;
  1983                             	sh4_x86.tstate = TSTATE_NONE;
  1984                             	if( UNTRANSLATABLE(pc+2) ) {
  1985                             	    exit_block_emu(pc+2);
  1986                             	    return 2;
  1987                             	} else {
  1988                             	    sh4_translate_instruction(pc+2);
  1989                             	    exit_block_newpcset(pc+2);
  1990                             	    return 4;
  1994                                 break;
  1995                             case 0x1:
  1996                                 { /* TAS.B @Rn */
  1997                                 uint32_t Rn = ((ir>>8)&0xF); 
  1998                                 load_reg( R_EAX, Rn );
  1999                                 MMU_TRANSLATE_WRITE( R_EAX );
  2000                                 PUSH_realigned_r32( R_EAX );
  2001                                 MEM_READ_BYTE( R_EAX, R_EAX );
  2002                                 TEST_r8_r8( R_AL, R_AL );
  2003                                 SETE_t();
  2004                                 OR_imm8_r8( 0x80, R_AL );
  2005                                 POP_realigned_r32( R_ECX );
  2006                                 MEM_WRITE_BYTE( R_ECX, R_EAX );
  2007                                 sh4_x86.tstate = TSTATE_NONE;
  2009                                 break;
  2010                             case 0x2:
  2011                                 { /* JMP @Rn */
  2012                                 uint32_t Rn = ((ir>>8)&0xF); 
  2013                                 if( sh4_x86.in_delay_slot ) {
  2014                             	SLOTILLEGAL();
  2015                                 } else {
  2016                             	load_reg( R_ECX, Rn );
  2017                             	store_spreg( R_ECX, R_NEW_PC );
  2018                             	sh4_x86.in_delay_slot = DELAY_PC;
  2019                             	sh4_x86.branch_taken = TRUE;
  2020                             	if( UNTRANSLATABLE(pc+2) ) {
  2021                             	    exit_block_emu(pc+2);
  2022                             	    return 2;
  2023                             	} else {
  2024                             	    sh4_translate_instruction(pc+2);
  2025                             	    exit_block_newpcset(pc+2);
  2026                             	    return 4;
  2030                                 break;
  2031                             default:
  2032                                 UNDEF();
  2033                                 break;
  2035                         break;
  2036                     case 0xC:
  2037                         { /* SHAD Rm, Rn */
  2038                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2039                         /* Annoyingly enough, not directly convertible */
  2040                         load_reg( R_EAX, Rn );
  2041                         load_reg( R_ECX, Rm );
  2042                         CMP_imm32_r32( 0, R_ECX );
  2043                         JGE_rel8(16, doshl);
  2045                         NEG_r32( R_ECX );      // 2
  2046                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2047                         JE_rel8( 4, emptysar);     // 2
  2048                         SAR_r32_CL( R_EAX );       // 2
  2049                         JMP_rel8(10, end);          // 2
  2051                         JMP_TARGET(emptysar);
  2052                         SAR_imm8_r32(31, R_EAX );  // 3
  2053                         JMP_rel8(5, end2);
  2055                         JMP_TARGET(doshl);
  2056                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2057                         SHL_r32_CL( R_EAX );       // 2
  2058                         JMP_TARGET(end);
  2059                         JMP_TARGET(end2);
  2060                         store_reg( R_EAX, Rn );
  2061                         sh4_x86.tstate = TSTATE_NONE;
  2063                         break;
  2064                     case 0xD:
  2065                         { /* SHLD Rm, Rn */
  2066                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2067                         load_reg( R_EAX, Rn );
  2068                         load_reg( R_ECX, Rm );
  2069                         CMP_imm32_r32( 0, R_ECX );
  2070                         JGE_rel8(15, doshl);
  2072                         NEG_r32( R_ECX );      // 2
  2073                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2074                         JE_rel8( 4, emptyshr );
  2075                         SHR_r32_CL( R_EAX );       // 2
  2076                         JMP_rel8(9, end);          // 2
  2078                         JMP_TARGET(emptyshr);
  2079                         XOR_r32_r32( R_EAX, R_EAX );
  2080                         JMP_rel8(5, end2);
  2082                         JMP_TARGET(doshl);
  2083                         AND_imm8_r8( 0x1F, R_CL ); // 3
  2084                         SHL_r32_CL( R_EAX );       // 2
  2085                         JMP_TARGET(end);
  2086                         JMP_TARGET(end2);
  2087                         store_reg( R_EAX, Rn );
  2088                         sh4_x86.tstate = TSTATE_NONE;
  2090                         break;
  2091                     case 0xE:
  2092                         switch( (ir&0x80) >> 7 ) {
  2093                             case 0x0:
  2094                                 switch( (ir&0x70) >> 4 ) {
  2095                                     case 0x0:
  2096                                         { /* LDC Rm, SR */
  2097                                         uint32_t Rm = ((ir>>8)&0xF); 
  2098                                         if( sh4_x86.in_delay_slot ) {
  2099                                     	SLOTILLEGAL();
  2100                                         } else {
  2101                                     	check_priv();
  2102                                     	load_reg( R_EAX, Rm );
  2103                                     	call_func1( sh4_write_sr, R_EAX );
  2104                                     	sh4_x86.priv_checked = FALSE;
  2105                                     	sh4_x86.fpuen_checked = FALSE;
  2106                                     	sh4_x86.tstate = TSTATE_NONE;
  2109                                         break;
  2110                                     case 0x1:
  2111                                         { /* LDC Rm, GBR */
  2112                                         uint32_t Rm = ((ir>>8)&0xF); 
  2113                                         load_reg( R_EAX, Rm );
  2114                                         store_spreg( R_EAX, R_GBR );
  2116                                         break;
  2117                                     case 0x2:
  2118                                         { /* LDC Rm, VBR */
  2119                                         uint32_t Rm = ((ir>>8)&0xF); 
  2120                                         check_priv();
  2121                                         load_reg( R_EAX, Rm );
  2122                                         store_spreg( R_EAX, R_VBR );
  2123                                         sh4_x86.tstate = TSTATE_NONE;
  2125                                         break;
  2126                                     case 0x3:
  2127                                         { /* LDC Rm, SSR */
  2128                                         uint32_t Rm = ((ir>>8)&0xF); 
  2129                                         check_priv();
  2130                                         load_reg( R_EAX, Rm );
  2131                                         store_spreg( R_EAX, R_SSR );
  2132                                         sh4_x86.tstate = TSTATE_NONE;
  2134                                         break;
  2135                                     case 0x4:
  2136                                         { /* LDC Rm, SPC */
  2137                                         uint32_t Rm = ((ir>>8)&0xF); 
  2138                                         check_priv();
  2139                                         load_reg( R_EAX, Rm );
  2140                                         store_spreg( R_EAX, R_SPC );
  2141                                         sh4_x86.tstate = TSTATE_NONE;
  2143                                         break;
  2144                                     default:
  2145                                         UNDEF();
  2146                                         break;
  2148                                 break;
  2149                             case 0x1:
  2150                                 { /* LDC Rm, Rn_BANK */
  2151                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  2152                                 check_priv();
  2153                                 load_reg( R_EAX, Rm );
  2154                                 store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
  2155                                 sh4_x86.tstate = TSTATE_NONE;
  2157                                 break;
  2159                         break;
  2160                     case 0xF:
  2161                         { /* MAC.W @Rm+, @Rn+ */
  2162                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2163                         if( Rm == Rn ) {
  2164                     	load_reg( R_EAX, Rm );
  2165                     	check_ralign16( R_EAX );
  2166                     	MMU_TRANSLATE_READ( R_EAX );
  2167                     	PUSH_realigned_r32( R_EAX );
  2168                     	load_reg( R_EAX, Rn );
  2169                     	ADD_imm8s_r32( 2, R_EAX );
  2170                     	MMU_TRANSLATE_READ_EXC( R_EAX, -5 );
  2171                     	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
  2172                     	// Note translate twice in case of page boundaries. Maybe worth
  2173                     	// adding a page-boundary check to skip the second translation
  2174                         } else {
  2175                     	load_reg( R_EAX, Rm );
  2176                     	check_ralign16( R_EAX );
  2177                     	MMU_TRANSLATE_READ( R_EAX );
  2178                     	load_reg( R_ECX, Rn );
  2179                     	check_ralign16( R_ECX );
  2180                     	PUSH_realigned_r32( R_EAX );
  2181                     	MMU_TRANSLATE_READ_EXC( R_ECX, -5 );
  2182                     	MOV_r32_r32( R_ECX, R_EAX );
  2183                     	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
  2184                     	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  2186                         MEM_READ_WORD( R_EAX, R_EAX );
  2187                         POP_r32( R_ECX );
  2188                         PUSH_r32( R_EAX );
  2189                         MEM_READ_WORD( R_ECX, R_EAX );
  2190                         POP_realigned_r32( R_ECX );
  2191                         IMUL_r32( R_ECX );
  2193                         load_spreg( R_ECX, R_S );
  2194                         TEST_r32_r32( R_ECX, R_ECX );
  2195                         JE_rel8( 47, nosat );
  2197                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2198                         JNO_rel8( 51, end );            // 2
  2199                         load_imm32( R_EDX, 1 );         // 5
  2200                         store_spreg( R_EDX, R_MACH );   // 6
  2201                         JS_rel8( 13, positive );        // 2
  2202                         load_imm32( R_EAX, 0x80000000 );// 5
  2203                         store_spreg( R_EAX, R_MACL );   // 6
  2204                         JMP_rel8( 25, end2 );           // 2
  2206                         JMP_TARGET(positive);
  2207                         load_imm32( R_EAX, 0x7FFFFFFF );// 5
  2208                         store_spreg( R_EAX, R_MACL );   // 6
  2209                         JMP_rel8( 12, end3);            // 2
  2211                         JMP_TARGET(nosat);
  2212                         ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  2213                         ADC_r32_sh4r( R_EDX, R_MACH );  // 6
  2214                         JMP_TARGET(end);
  2215                         JMP_TARGET(end2);
  2216                         JMP_TARGET(end3);
  2217                         sh4_x86.tstate = TSTATE_NONE;
  2219                         break;
  2221                 break;
  2222             case 0x5:
  2223                 { /* MOV.L @(disp, Rm), Rn */
  2224                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  2225                 load_reg( R_EAX, Rm );
  2226                 ADD_imm8s_r32( disp, R_EAX );
  2227                 check_ralign32( R_EAX );
  2228                 MMU_TRANSLATE_READ( R_EAX );
  2229                 MEM_READ_LONG( R_EAX, R_EAX );
  2230                 store_reg( R_EAX, Rn );
  2231                 sh4_x86.tstate = TSTATE_NONE;
  2233                 break;
  2234             case 0x6:
  2235                 switch( ir&0xF ) {
  2236                     case 0x0:
  2237                         { /* MOV.B @Rm, Rn */
  2238                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2239                         load_reg( R_EAX, Rm );
  2240                         MMU_TRANSLATE_READ( R_EAX );
  2241                         MEM_READ_BYTE( R_EAX, R_EAX );
  2242                         store_reg( R_EAX, Rn );
  2243                         sh4_x86.tstate = TSTATE_NONE;
  2245                         break;
  2246                     case 0x1:
  2247                         { /* MOV.W @Rm, Rn */
  2248                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2249                         load_reg( R_EAX, Rm );
  2250                         check_ralign16( R_EAX );
  2251                         MMU_TRANSLATE_READ( R_EAX );
  2252                         MEM_READ_WORD( R_EAX, R_EAX );
  2253                         store_reg( R_EAX, Rn );
  2254                         sh4_x86.tstate = TSTATE_NONE;
  2256                         break;
  2257                     case 0x2:
  2258                         { /* MOV.L @Rm, Rn */
  2259                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2260                         load_reg( R_EAX, Rm );
  2261                         check_ralign32( R_EAX );
  2262                         MMU_TRANSLATE_READ( R_EAX );
  2263                         MEM_READ_LONG( R_EAX, R_EAX );
  2264                         store_reg( R_EAX, Rn );
  2265                         sh4_x86.tstate = TSTATE_NONE;
  2267                         break;
  2268                     case 0x3:
  2269                         { /* MOV Rm, Rn */
  2270                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2271                         load_reg( R_EAX, Rm );
  2272                         store_reg( R_EAX, Rn );
  2274                         break;
  2275                     case 0x4:
  2276                         { /* MOV.B @Rm+, Rn */
  2277                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2278                         load_reg( R_EAX, Rm );
  2279                         MMU_TRANSLATE_READ( R_EAX );
  2280                         ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
  2281                         MEM_READ_BYTE( R_EAX, R_EAX );
  2282                         store_reg( R_EAX, Rn );
  2283                         sh4_x86.tstate = TSTATE_NONE;
  2285                         break;
  2286                     case 0x5:
  2287                         { /* MOV.W @Rm+, Rn */
  2288                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2289                         load_reg( R_EAX, Rm );
  2290                         check_ralign16( R_EAX );
  2291                         MMU_TRANSLATE_READ( R_EAX );
  2292                         ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  2293                         MEM_READ_WORD( R_EAX, R_EAX );
  2294                         store_reg( R_EAX, Rn );
  2295                         sh4_x86.tstate = TSTATE_NONE;
  2297                         break;
  2298                     case 0x6:
  2299                         { /* MOV.L @Rm+, Rn */
  2300                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2301                         load_reg( R_EAX, Rm );
  2302                         check_ralign32( R_EAX );
  2303                         MMU_TRANSLATE_READ( R_EAX );
  2304                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  2305                         MEM_READ_LONG( R_EAX, R_EAX );
  2306                         store_reg( R_EAX, Rn );
  2307                         sh4_x86.tstate = TSTATE_NONE;
  2309                         break;
  2310                     case 0x7:
  2311                         { /* NOT Rm, Rn */
  2312                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2313                         load_reg( R_EAX, Rm );
  2314                         NOT_r32( R_EAX );
  2315                         store_reg( R_EAX, Rn );
  2316                         sh4_x86.tstate = TSTATE_NONE;
  2318                         break;
  2319                     case 0x8:
  2320                         { /* SWAP.B Rm, Rn */
  2321                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2322                         load_reg( R_EAX, Rm );
  2323                         XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
  2324                         store_reg( R_EAX, Rn );
  2326                         break;
  2327                     case 0x9:
  2328                         { /* SWAP.W Rm, Rn */
  2329                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2330                         load_reg( R_EAX, Rm );
  2331                         MOV_r32_r32( R_EAX, R_ECX );
  2332                         SHL_imm8_r32( 16, R_ECX );
  2333                         SHR_imm8_r32( 16, R_EAX );
  2334                         OR_r32_r32( R_EAX, R_ECX );
  2335                         store_reg( R_ECX, Rn );
  2336                         sh4_x86.tstate = TSTATE_NONE;
  2338                         break;
  2339                     case 0xA:
  2340                         { /* NEGC Rm, Rn */
  2341                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2342                         load_reg( R_EAX, Rm );
  2343                         XOR_r32_r32( R_ECX, R_ECX );
  2344                         LDC_t();
  2345                         SBB_r32_r32( R_EAX, R_ECX );
  2346                         store_reg( R_ECX, Rn );
  2347                         SETC_t();
  2348                         sh4_x86.tstate = TSTATE_C;
  2350                         break;
  2351                     case 0xB:
  2352                         { /* NEG Rm, Rn */
  2353                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2354                         load_reg( R_EAX, Rm );
  2355                         NEG_r32( R_EAX );
  2356                         store_reg( R_EAX, Rn );
  2357                         sh4_x86.tstate = TSTATE_NONE;
  2359                         break;
  2360                     case 0xC:
  2361                         { /* EXTU.B Rm, Rn */
  2362                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2363                         load_reg( R_EAX, Rm );
  2364                         MOVZX_r8_r32( R_EAX, R_EAX );
  2365                         store_reg( R_EAX, Rn );
  2367                         break;
  2368                     case 0xD:
  2369                         { /* EXTU.W Rm, Rn */
  2370                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2371                         load_reg( R_EAX, Rm );
  2372                         MOVZX_r16_r32( R_EAX, R_EAX );
  2373                         store_reg( R_EAX, Rn );
  2375                         break;
  2376                     case 0xE:
  2377                         { /* EXTS.B Rm, Rn */
  2378                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2379                         load_reg( R_EAX, Rm );
  2380                         MOVSX_r8_r32( R_EAX, R_EAX );
  2381                         store_reg( R_EAX, Rn );
  2383                         break;
  2384                     case 0xF:
  2385                         { /* EXTS.W Rm, Rn */
  2386                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  2387                         load_reg( R_EAX, Rm );
  2388                         MOVSX_r16_r32( R_EAX, R_EAX );
  2389                         store_reg( R_EAX, Rn );
  2391                         break;
  2393                 break;
  2394             case 0x7:
  2395                 { /* ADD #imm, Rn */
  2396                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2397                 load_reg( R_EAX, Rn );
  2398                 ADD_imm8s_r32( imm, R_EAX );
  2399                 store_reg( R_EAX, Rn );
  2400                 sh4_x86.tstate = TSTATE_NONE;
  2402                 break;
  2403             case 0x8:
  2404                 switch( (ir&0xF00) >> 8 ) {
  2405                     case 0x0:
  2406                         { /* MOV.B R0, @(disp, Rn) */
  2407                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2408                         load_reg( R_EAX, Rn );
  2409                         ADD_imm32_r32( disp, R_EAX );
  2410                         MMU_TRANSLATE_WRITE( R_EAX );
  2411                         load_reg( R_EDX, 0 );
  2412                         MEM_WRITE_BYTE( R_EAX, R_EDX );
  2413                         sh4_x86.tstate = TSTATE_NONE;
  2415                         break;
  2416                     case 0x1:
  2417                         { /* MOV.W R0, @(disp, Rn) */
  2418                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2419                         load_reg( R_EAX, Rn );
  2420                         ADD_imm32_r32( disp, R_EAX );
  2421                         check_walign16( R_EAX );
  2422                         MMU_TRANSLATE_WRITE( R_EAX );
  2423                         load_reg( R_EDX, 0 );
  2424                         MEM_WRITE_WORD( R_EAX, R_EDX );
  2425                         sh4_x86.tstate = TSTATE_NONE;
  2427                         break;
  2428                     case 0x4:
  2429                         { /* MOV.B @(disp, Rm), R0 */
  2430                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  2431                         load_reg( R_EAX, Rm );
  2432                         ADD_imm32_r32( disp, R_EAX );
  2433                         MMU_TRANSLATE_READ( R_EAX );
  2434                         MEM_READ_BYTE( R_EAX, R_EAX );
  2435                         store_reg( R_EAX, 0 );
  2436                         sh4_x86.tstate = TSTATE_NONE;
  2438                         break;
  2439                     case 0x5:
  2440                         { /* MOV.W @(disp, Rm), R0 */
  2441                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  2442                         load_reg( R_EAX, Rm );
  2443                         ADD_imm32_r32( disp, R_EAX );
  2444                         check_ralign16( R_EAX );
  2445                         MMU_TRANSLATE_READ( R_EAX );
  2446                         MEM_READ_WORD( R_EAX, R_EAX );
  2447                         store_reg( R_EAX, 0 );
  2448                         sh4_x86.tstate = TSTATE_NONE;
  2450                         break;
  2451                     case 0x8:
  2452                         { /* CMP/EQ #imm, R0 */
  2453                         int32_t imm = SIGNEXT8(ir&0xFF); 
  2454                         load_reg( R_EAX, 0 );
  2455                         CMP_imm8s_r32(imm, R_EAX);
  2456                         SETE_t();
  2457                         sh4_x86.tstate = TSTATE_E;
  2459                         break;
  2460                     case 0x9:
  2461                         { /* BT disp */
  2462                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2463                         if( sh4_x86.in_delay_slot ) {
  2464                     	SLOTILLEGAL();
  2465                         } else {
  2466                     	sh4vma_t target = disp + pc + 4;
  2467                     	JF_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
  2468                     	exit_block_rel(target, pc+2 );
  2469                     	JMP_TARGET(nottaken);
  2470                     	return 2;
  2473                         break;
  2474                     case 0xB:
  2475                         { /* BF disp */
  2476                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2477                         if( sh4_x86.in_delay_slot ) {
  2478                     	SLOTILLEGAL();
  2479                         } else {
  2480                     	sh4vma_t target = disp + pc + 4;
  2481                     	JT_rel8( EXIT_BLOCK_REL_SIZE(target), nottaken );
  2482                     	exit_block_rel(target, pc+2 );
  2483                     	JMP_TARGET(nottaken);
  2484                     	return 2;
  2487                         break;
  2488                     case 0xD:
  2489                         { /* BT/S disp */
  2490                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2491                         if( sh4_x86.in_delay_slot ) {
  2492                     	SLOTILLEGAL();
  2493                         } else {
  2494                     	sh4_x86.in_delay_slot = DELAY_PC;
  2495                     	if( UNTRANSLATABLE(pc+2) ) {
  2496                     	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
  2497                     	    JF_rel8(6,nottaken);
  2498                     	    ADD_imm32_r32( disp, R_EAX );
  2499                     	    JMP_TARGET(nottaken);
  2500                     	    ADD_sh4r_r32( R_PC, R_EAX );
  2501                     	    store_spreg( R_EAX, R_NEW_PC );
  2502                     	    exit_block_emu(pc+2);
  2503                     	    sh4_x86.branch_taken = TRUE;
  2504                     	    return 2;
  2505                     	} else {
  2506                     	    if( sh4_x86.tstate == TSTATE_NONE ) {
  2507                     		CMP_imm8s_sh4r( 1, R_T );
  2508                     		sh4_x86.tstate = TSTATE_E;
  2510                     	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
  2511                     	    sh4_translate_instruction(pc+2);
  2512                     	    exit_block_rel( disp + pc + 4, pc+4 );
  2513                     	    // not taken
  2514                     	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2515                     	    sh4_translate_instruction(pc+2);
  2516                     	    return 4;
  2520                         break;
  2521                     case 0xF:
  2522                         { /* BF/S disp */
  2523                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  2524                         if( sh4_x86.in_delay_slot ) {
  2525                     	SLOTILLEGAL();
  2526                         } else {
  2527                     	sh4_x86.in_delay_slot = DELAY_PC;
  2528                     	if( UNTRANSLATABLE(pc+2) ) {
  2529                     	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
  2530                     	    JT_rel8(6,nottaken);
  2531                     	    ADD_imm32_r32( disp, R_EAX );
  2532                     	    JMP_TARGET(nottaken);
  2533                     	    ADD_sh4r_r32( R_PC, R_EAX );
  2534                     	    store_spreg( R_EAX, R_NEW_PC );
  2535                     	    exit_block_emu(pc+2);
  2536                     	    sh4_x86.branch_taken = TRUE;
  2537                     	    return 2;
  2538                     	} else {
  2539                     	    if( sh4_x86.tstate == TSTATE_NONE ) {
  2540                     		CMP_imm8s_sh4r( 1, R_T );
  2541                     		sh4_x86.tstate = TSTATE_E;
  2543                     	    sh4vma_t target = disp + pc + 4;
  2544                     	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
  2545                     	    sh4_translate_instruction(pc+2);
  2546                     	    exit_block_rel( target, pc+4 );
  2548                     	    // not taken
  2549                     	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
  2550                     	    sh4_translate_instruction(pc+2);
  2551                     	    return 4;
  2555                         break;
  2556                     default:
  2557                         UNDEF();
  2558                         break;
  2560                 break;
  2561             case 0x9:
  2562                 { /* MOV.W @(disp, PC), Rn */
  2563                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  2564                 if( sh4_x86.in_delay_slot ) {
  2565             	SLOTILLEGAL();
  2566                 } else {
  2567             	// See comments for MOV.L @(disp, PC), Rn
  2568             	uint32_t target = pc + disp + 4;
  2569             	if( IS_IN_ICACHE(target) ) {
  2570             	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
  2571             	    MOV_moff32_EAX( ptr );
  2572             	    MOVSX_r16_r32( R_EAX, R_EAX );
  2573             	} else {
  2574             	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
  2575             	    ADD_sh4r_r32( R_PC, R_EAX );
  2576             	    MMU_TRANSLATE_READ( R_EAX );
  2577             	    MEM_READ_WORD( R_EAX, R_EAX );
  2578             	    sh4_x86.tstate = TSTATE_NONE;
  2580             	store_reg( R_EAX, Rn );
  2583                 break;
  2584             case 0xA:
  2585                 { /* BRA disp */
  2586                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2587                 if( sh4_x86.in_delay_slot ) {
  2588             	SLOTILLEGAL();
  2589                 } else {
  2590             	sh4_x86.in_delay_slot = DELAY_PC;
  2591             	sh4_x86.branch_taken = TRUE;
  2592             	if( UNTRANSLATABLE(pc+2) ) {
  2593             	    load_spreg( R_EAX, R_PC );
  2594             	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
  2595             	    store_spreg( R_EAX, R_NEW_PC );
  2596             	    exit_block_emu(pc+2);
  2597             	    return 2;
  2598             	} else {
  2599             	    sh4_translate_instruction( pc + 2 );
  2600             	    exit_block_rel( disp + pc + 4, pc+4 );
  2601             	    return 4;
  2605                 break;
  2606             case 0xB:
  2607                 { /* BSR disp */
  2608                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  2609                 if( sh4_x86.in_delay_slot ) {
  2610             	SLOTILLEGAL();
  2611                 } else {
  2612             	load_spreg( R_EAX, R_PC );
  2613             	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
  2614             	store_spreg( R_EAX, R_PR );
  2615             	sh4_x86.in_delay_slot = DELAY_PC;
  2616             	sh4_x86.branch_taken = TRUE;
  2617             	sh4_x86.tstate = TSTATE_NONE;
  2618             	if( UNTRANSLATABLE(pc+2) ) {
  2619             	    ADD_imm32_r32( disp, R_EAX );
  2620             	    store_spreg( R_EAX, R_NEW_PC );
  2621             	    exit_block_emu(pc+2);
  2622             	    return 2;
  2623             	} else {
  2624             	    sh4_translate_instruction( pc + 2 );
  2625             	    exit_block_rel( disp + pc + 4, pc+4 );
  2626             	    return 4;
  2630                 break;
  2631             case 0xC:
  2632                 switch( (ir&0xF00) >> 8 ) {
  2633                     case 0x0:
  2634                         { /* MOV.B R0, @(disp, GBR) */
  2635                         uint32_t disp = (ir&0xFF); 
  2636                         load_spreg( R_EAX, R_GBR );
  2637                         ADD_imm32_r32( disp, R_EAX );
  2638                         MMU_TRANSLATE_WRITE( R_EAX );
  2639                         load_reg( R_EDX, 0 );
  2640                         MEM_WRITE_BYTE( R_EAX, R_EDX );
  2641                         sh4_x86.tstate = TSTATE_NONE;
  2643                         break;
  2644                     case 0x1:
  2645                         { /* MOV.W R0, @(disp, GBR) */
  2646                         uint32_t disp = (ir&0xFF)<<1; 
  2647                         load_spreg( R_EAX, R_GBR );
  2648                         ADD_imm32_r32( disp, R_EAX );
  2649                         check_walign16( R_EAX );
  2650                         MMU_TRANSLATE_WRITE( R_EAX );
  2651                         load_reg( R_EDX, 0 );
  2652                         MEM_WRITE_WORD( R_EAX, R_EDX );
  2653                         sh4_x86.tstate = TSTATE_NONE;
  2655                         break;
  2656                     case 0x2:
  2657                         { /* MOV.L R0, @(disp, GBR) */
  2658                         uint32_t disp = (ir&0xFF)<<2; 
  2659                         load_spreg( R_EAX, R_GBR );
  2660                         ADD_imm32_r32( disp, R_EAX );
  2661                         check_walign32( R_EAX );
  2662                         MMU_TRANSLATE_WRITE( R_EAX );
  2663                         load_reg( R_EDX, 0 );
  2664                         MEM_WRITE_LONG( R_EAX, R_EDX );
  2665                         sh4_x86.tstate = TSTATE_NONE;
  2667                         break;
  2668                     case 0x3:
  2669                         { /* TRAPA #imm */
  2670                         uint32_t imm = (ir&0xFF); 
  2671                         if( sh4_x86.in_delay_slot ) {
  2672                     	SLOTILLEGAL();
  2673                         } else {
  2674                     	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
  2675                     	ADD_r32_sh4r( R_ECX, R_PC );
  2676                     	load_imm32( R_EAX, imm );
  2677                     	call_func1( sh4_raise_trap, R_EAX );
  2678                     	sh4_x86.tstate = TSTATE_NONE;
  2679                     	exit_block_pcset(pc);
  2680                     	sh4_x86.branch_taken = TRUE;
  2681                     	return 2;
  2684                         break;
  2685                     case 0x4:
  2686                         { /* MOV.B @(disp, GBR), R0 */
  2687                         uint32_t disp = (ir&0xFF); 
  2688                         load_spreg( R_EAX, R_GBR );
  2689                         ADD_imm32_r32( disp, R_EAX );
  2690                         MMU_TRANSLATE_READ( R_EAX );
  2691                         MEM_READ_BYTE( R_EAX, R_EAX );
  2692                         store_reg( R_EAX, 0 );
  2693                         sh4_x86.tstate = TSTATE_NONE;
  2695                         break;
  2696                     case 0x5:
  2697                         { /* MOV.W @(disp, GBR), R0 */
  2698                         uint32_t disp = (ir&0xFF)<<1; 
  2699                         load_spreg( R_EAX, R_GBR );
  2700                         ADD_imm32_r32( disp, R_EAX );
  2701                         check_ralign16( R_EAX );
  2702                         MMU_TRANSLATE_READ( R_EAX );
  2703                         MEM_READ_WORD( R_EAX, R_EAX );
  2704                         store_reg( R_EAX, 0 );
  2705                         sh4_x86.tstate = TSTATE_NONE;
  2707                         break;
  2708                     case 0x6:
  2709                         { /* MOV.L @(disp, GBR), R0 */
  2710                         uint32_t disp = (ir&0xFF)<<2; 
  2711                         load_spreg( R_EAX, R_GBR );
  2712                         ADD_imm32_r32( disp, R_EAX );
  2713                         check_ralign32( R_EAX );
  2714                         MMU_TRANSLATE_READ( R_EAX );
  2715                         MEM_READ_LONG( R_EAX, R_EAX );
  2716                         store_reg( R_EAX, 0 );
  2717                         sh4_x86.tstate = TSTATE_NONE;
  2719                         break;
  2720                     case 0x7:
  2721                         { /* MOVA @(disp, PC), R0 */
  2722                         uint32_t disp = (ir&0xFF)<<2; 
  2723                         if( sh4_x86.in_delay_slot ) {
  2724                     	SLOTILLEGAL();
  2725                         } else {
  2726                     	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
  2727                     	ADD_sh4r_r32( R_PC, R_ECX );
  2728                     	store_reg( R_ECX, 0 );
  2729                     	sh4_x86.tstate = TSTATE_NONE;
  2732                         break;
  2733                     case 0x8:
  2734                         { /* TST #imm, R0 */
  2735                         uint32_t imm = (ir&0xFF); 
  2736                         load_reg( R_EAX, 0 );
  2737                         TEST_imm32_r32( imm, R_EAX );
  2738                         SETE_t();
  2739                         sh4_x86.tstate = TSTATE_E;
  2741                         break;
  2742                     case 0x9:
  2743                         { /* AND #imm, R0 */
  2744                         uint32_t imm = (ir&0xFF); 
  2745                         load_reg( R_EAX, 0 );
  2746                         AND_imm32_r32(imm, R_EAX); 
  2747                         store_reg( R_EAX, 0 );
  2748                         sh4_x86.tstate = TSTATE_NONE;
  2750                         break;
  2751                     case 0xA:
  2752                         { /* XOR #imm, R0 */
  2753                         uint32_t imm = (ir&0xFF); 
  2754                         load_reg( R_EAX, 0 );
  2755                         XOR_imm32_r32( imm, R_EAX );
  2756                         store_reg( R_EAX, 0 );
  2757                         sh4_x86.tstate = TSTATE_NONE;
  2759                         break;
  2760                     case 0xB:
  2761                         { /* OR #imm, R0 */
  2762                         uint32_t imm = (ir&0xFF); 
  2763                         load_reg( R_EAX, 0 );
  2764                         OR_imm32_r32(imm, R_EAX);
  2765                         store_reg( R_EAX, 0 );
  2766                         sh4_x86.tstate = TSTATE_NONE;
  2768                         break;
  2769                     case 0xC:
  2770                         { /* TST.B #imm, @(R0, GBR) */
  2771                         uint32_t imm = (ir&0xFF); 
  2772                         load_reg( R_EAX, 0);
  2773                         load_reg( R_ECX, R_GBR);
  2774                         ADD_r32_r32( R_ECX, R_EAX );
  2775                         MMU_TRANSLATE_READ( R_EAX );
  2776                         MEM_READ_BYTE( R_EAX, R_EAX );
  2777                         TEST_imm8_r8( imm, R_AL );
  2778                         SETE_t();
  2779                         sh4_x86.tstate = TSTATE_E;
  2781                         break;
  2782                     case 0xD:
  2783                         { /* AND.B #imm, @(R0, GBR) */
  2784                         uint32_t imm = (ir&0xFF); 
  2785                         load_reg( R_EAX, 0 );
  2786                         load_spreg( R_ECX, R_GBR );
  2787                         ADD_r32_r32( R_ECX, R_EAX );
  2788                         MMU_TRANSLATE_WRITE( R_EAX );
  2789                         PUSH_realigned_r32(R_EAX);
  2790                         MEM_READ_BYTE( R_EAX, R_EAX );
  2791                         POP_realigned_r32(R_ECX);
  2792                         AND_imm32_r32(imm, R_EAX );
  2793                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2794                         sh4_x86.tstate = TSTATE_NONE;
  2796                         break;
  2797                     case 0xE:
  2798                         { /* XOR.B #imm, @(R0, GBR) */
  2799                         uint32_t imm = (ir&0xFF); 
  2800                         load_reg( R_EAX, 0 );
  2801                         load_spreg( R_ECX, R_GBR );
  2802                         ADD_r32_r32( R_ECX, R_EAX );
  2803                         MMU_TRANSLATE_WRITE( R_EAX );
  2804                         PUSH_realigned_r32(R_EAX);
  2805                         MEM_READ_BYTE(R_EAX, R_EAX);
  2806                         POP_realigned_r32(R_ECX);
  2807                         XOR_imm32_r32( imm, R_EAX );
  2808                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2809                         sh4_x86.tstate = TSTATE_NONE;
  2811                         break;
  2812                     case 0xF:
  2813                         { /* OR.B #imm, @(R0, GBR) */
  2814                         uint32_t imm = (ir&0xFF); 
  2815                         load_reg( R_EAX, 0 );
  2816                         load_spreg( R_ECX, R_GBR );
  2817                         ADD_r32_r32( R_ECX, R_EAX );
  2818                         MMU_TRANSLATE_WRITE( R_EAX );
  2819                         PUSH_realigned_r32(R_EAX);
  2820                         MEM_READ_BYTE( R_EAX, R_EAX );
  2821                         POP_realigned_r32(R_ECX);
  2822                         OR_imm32_r32(imm, R_EAX );
  2823                         MEM_WRITE_BYTE( R_ECX, R_EAX );
  2824                         sh4_x86.tstate = TSTATE_NONE;
  2826                         break;
  2828                 break;
  2829             case 0xD:
  2830                 { /* MOV.L @(disp, PC), Rn */
  2831                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  2832                 if( sh4_x86.in_delay_slot ) {
  2833             	SLOTILLEGAL();
  2834                 } else {
  2835             	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
  2836             	if( IS_IN_ICACHE(target) ) {
  2837             	    // If the target address is in the same page as the code, it's
  2838             	    // pretty safe to just ref it directly and circumvent the whole
  2839             	    // memory subsystem. (this is a big performance win)
  2841             	    // FIXME: There's a corner-case that's not handled here when
  2842             	    // the current code-page is in the ITLB but not in the UTLB.
  2843             	    // (should generate a TLB miss although need to test SH4 
  2844             	    // behaviour to confirm) Unlikely to be anyone depending on this
  2845             	    // behaviour though.
  2846             	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
  2847             	    MOV_moff32_EAX( ptr );
  2848             	} else {
  2849             	    // Note: we use sh4r.pc for the calc as we could be running at a
  2850             	    // different virtual address than the translation was done with,
  2851             	    // but we can safely assume that the low bits are the same.
  2852             	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
  2853             	    ADD_sh4r_r32( R_PC, R_EAX );
  2854             	    MMU_TRANSLATE_READ( R_EAX );
  2855             	    MEM_READ_LONG( R_EAX, R_EAX );
  2856             	    sh4_x86.tstate = TSTATE_NONE;
  2858             	store_reg( R_EAX, Rn );
  2861                 break;
  2862             case 0xE:
  2863                 { /* MOV #imm, Rn */
  2864                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  2865                 load_imm32( R_EAX, imm );
  2866                 store_reg( R_EAX, Rn );
  2868                 break;
  2869             case 0xF:
  2870                 switch( ir&0xF ) {
  2871                     case 0x0:
  2872                         { /* FADD FRm, FRn */
  2873                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2874                         check_fpuen();
  2875                         load_spreg( R_ECX, R_FPSCR );
  2876                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2877                         load_fr_bank( R_EDX );
  2878                         JNE_rel8(13,doubleprec);
  2879                         push_fr(R_EDX, FRm);
  2880                         push_fr(R_EDX, FRn);
  2881                         FADDP_st(1);
  2882                         pop_fr(R_EDX, FRn);
  2883                         JMP_rel8(11,end);
  2884                         JMP_TARGET(doubleprec);
  2885                         push_dr(R_EDX, FRm);
  2886                         push_dr(R_EDX, FRn);
  2887                         FADDP_st(1);
  2888                         pop_dr(R_EDX, FRn);
  2889                         JMP_TARGET(end);
  2890                         sh4_x86.tstate = TSTATE_NONE;
  2892                         break;
  2893                     case 0x1:
  2894                         { /* FSUB FRm, FRn */
  2895                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2896                         check_fpuen();
  2897                         load_spreg( R_ECX, R_FPSCR );
  2898                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2899                         load_fr_bank( R_EDX );
  2900                         JNE_rel8(13, doubleprec);
  2901                         push_fr(R_EDX, FRn);
  2902                         push_fr(R_EDX, FRm);
  2903                         FSUBP_st(1);
  2904                         pop_fr(R_EDX, FRn);
  2905                         JMP_rel8(11, end);
  2906                         JMP_TARGET(doubleprec);
  2907                         push_dr(R_EDX, FRn);
  2908                         push_dr(R_EDX, FRm);
  2909                         FSUBP_st(1);
  2910                         pop_dr(R_EDX, FRn);
  2911                         JMP_TARGET(end);
  2912                         sh4_x86.tstate = TSTATE_NONE;
  2914                         break;
  2915                     case 0x2:
  2916                         { /* FMUL FRm, FRn */
  2917                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2918                         check_fpuen();
  2919                         load_spreg( R_ECX, R_FPSCR );
  2920                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2921                         load_fr_bank( R_EDX );
  2922                         JNE_rel8(13, doubleprec);
  2923                         push_fr(R_EDX, FRm);
  2924                         push_fr(R_EDX, FRn);
  2925                         FMULP_st(1);
  2926                         pop_fr(R_EDX, FRn);
  2927                         JMP_rel8(11, end);
  2928                         JMP_TARGET(doubleprec);
  2929                         push_dr(R_EDX, FRm);
  2930                         push_dr(R_EDX, FRn);
  2931                         FMULP_st(1);
  2932                         pop_dr(R_EDX, FRn);
  2933                         JMP_TARGET(end);
  2934                         sh4_x86.tstate = TSTATE_NONE;
  2936                         break;
  2937                     case 0x3:
  2938                         { /* FDIV FRm, FRn */
  2939                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2940                         check_fpuen();
  2941                         load_spreg( R_ECX, R_FPSCR );
  2942                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2943                         load_fr_bank( R_EDX );
  2944                         JNE_rel8(13, doubleprec);
  2945                         push_fr(R_EDX, FRn);
  2946                         push_fr(R_EDX, FRm);
  2947                         FDIVP_st(1);
  2948                         pop_fr(R_EDX, FRn);
  2949                         JMP_rel8(11, end);
  2950                         JMP_TARGET(doubleprec);
  2951                         push_dr(R_EDX, FRn);
  2952                         push_dr(R_EDX, FRm);
  2953                         FDIVP_st(1);
  2954                         pop_dr(R_EDX, FRn);
  2955                         JMP_TARGET(end);
  2956                         sh4_x86.tstate = TSTATE_NONE;
  2958                         break;
  2959                     case 0x4:
  2960                         { /* FCMP/EQ FRm, FRn */
  2961                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2962                         check_fpuen();
  2963                         load_spreg( R_ECX, R_FPSCR );
  2964                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2965                         load_fr_bank( R_EDX );
  2966                         JNE_rel8(8, doubleprec);
  2967                         push_fr(R_EDX, FRm);
  2968                         push_fr(R_EDX, FRn);
  2969                         JMP_rel8(6, end);
  2970                         JMP_TARGET(doubleprec);
  2971                         push_dr(R_EDX, FRm);
  2972                         push_dr(R_EDX, FRn);
  2973                         JMP_TARGET(end);
  2974                         FCOMIP_st(1);
  2975                         SETE_t();
  2976                         FPOP_st();
  2977                         sh4_x86.tstate = TSTATE_NONE;
  2979                         break;
  2980                     case 0x5:
  2981                         { /* FCMP/GT FRm, FRn */
  2982                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2983                         check_fpuen();
  2984                         load_spreg( R_ECX, R_FPSCR );
  2985                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  2986                         load_fr_bank( R_EDX );
  2987                         JNE_rel8(8, doubleprec);
  2988                         push_fr(R_EDX, FRm);
  2989                         push_fr(R_EDX, FRn);
  2990                         JMP_rel8(6, end);
  2991                         JMP_TARGET(doubleprec);
  2992                         push_dr(R_EDX, FRm);
  2993                         push_dr(R_EDX, FRn);
  2994                         JMP_TARGET(end);
  2995                         FCOMIP_st(1);
  2996                         SETA_t();
  2997                         FPOP_st();
  2998                         sh4_x86.tstate = TSTATE_NONE;
  3000                         break;
  3001                     case 0x6:
  3002                         { /* FMOV @(R0, Rm), FRn */
  3003                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  3004                         check_fpuen();
  3005                         load_reg( R_EAX, Rm );
  3006                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
  3007                         check_ralign32( R_EAX );
  3008                         MMU_TRANSLATE_READ( R_EAX );
  3009                         load_spreg( R_EDX, R_FPSCR );
  3010                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3011                         JNE_rel8(8 + MEM_READ_SIZE, doublesize);
  3012                         MEM_READ_LONG( R_EAX, R_EAX );
  3013                         load_fr_bank( R_EDX );
  3014                         store_fr( R_EDX, R_EAX, FRn );
  3015                         if( FRn&1 ) {
  3016                     	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
  3017                     	JMP_TARGET(doublesize);
  3018                     	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  3019                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  3020                     	load_xf_bank( R_EDX );
  3021                     	store_fr( R_EDX, R_ECX, FRn&0x0E );
  3022                     	store_fr( R_EDX, R_EAX, FRn|0x01 );
  3023                     	JMP_TARGET(end);
  3024                         } else {
  3025                     	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
  3026                     	JMP_TARGET(doublesize);
  3027                     	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  3028                     	load_fr_bank( R_EDX );
  3029                     	store_fr( R_EDX, R_ECX, FRn&0x0E );
  3030                     	store_fr( R_EDX, R_EAX, FRn|0x01 );
  3031                     	JMP_TARGET(end);
  3033                         sh4_x86.tstate = TSTATE_NONE;
  3035                         break;
  3036                     case 0x7:
  3037                         { /* FMOV FRm, @(R0, Rn) */
  3038                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3039                         check_fpuen();
  3040                         load_reg( R_EAX, Rn );
  3041                         ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
  3042                         check_walign32( R_EAX );
  3043                         MMU_TRANSLATE_WRITE( R_EAX );
  3044                         load_spreg( R_EDX, R_FPSCR );
  3045                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3046                         JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
  3047                         load_fr_bank( R_EDX );
  3048                         load_fr( R_EDX, R_ECX, FRm );
  3049                         MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
  3050                         if( FRm&1 ) {
  3051                     	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
  3052                     	JMP_TARGET(doublesize);
  3053                     	load_xf_bank( R_EDX );
  3054                     	load_fr( R_EDX, R_ECX, FRm&0x0E );
  3055                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  3056                     	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  3057                     	JMP_TARGET(end);
  3058                         } else {
  3059                     	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
  3060                     	JMP_TARGET(doublesize);
  3061                     	load_fr_bank( R_EDX );
  3062                     	load_fr( R_EDX, R_ECX, FRm&0x0E );
  3063                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  3064                     	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  3065                     	JMP_TARGET(end);
  3067                         sh4_x86.tstate = TSTATE_NONE;
  3069                         break;
  3070                     case 0x8:
  3071                         { /* FMOV @Rm, FRn */
  3072                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  3073                         check_fpuen();
  3074                         load_reg( R_EAX, Rm );
  3075                         check_ralign32( R_EAX );
  3076                         MMU_TRANSLATE_READ( R_EAX );
  3077                         load_spreg( R_EDX, R_FPSCR );
  3078                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3079                         JNE_rel8(8 + MEM_READ_SIZE, doublesize);
  3080                         MEM_READ_LONG( R_EAX, R_EAX );
  3081                         load_fr_bank( R_EDX );
  3082                         store_fr( R_EDX, R_EAX, FRn );
  3083                         if( FRn&1 ) {
  3084                     	JMP_rel8(21 + MEM_READ_DOUBLE_SIZE, end);
  3085                     	JMP_TARGET(doublesize);
  3086                     	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  3087                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  3088                     	load_xf_bank( R_EDX );
  3089                     	store_fr( R_EDX, R_ECX, FRn&0x0E );
  3090                     	store_fr( R_EDX, R_EAX, FRn|0x01 );
  3091                     	JMP_TARGET(end);
  3092                         } else {
  3093                     	JMP_rel8(9 + MEM_READ_DOUBLE_SIZE, end);
  3094                     	JMP_TARGET(doublesize);
  3095                     	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  3096                     	load_fr_bank( R_EDX );
  3097                     	store_fr( R_EDX, R_ECX, FRn&0x0E );
  3098                     	store_fr( R_EDX, R_EAX, FRn|0x01 );
  3099                     	JMP_TARGET(end);
  3101                         sh4_x86.tstate = TSTATE_NONE;
  3103                         break;
  3104                     case 0x9:
  3105                         { /* FMOV @Rm+, FRn */
  3106                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  3107                         check_fpuen();
  3108                         load_reg( R_EAX, Rm );
  3109                         check_ralign32( R_EAX );
  3110                         MMU_TRANSLATE_READ( R_EAX );
  3111                         load_spreg( R_EDX, R_FPSCR );
  3112                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3113                         JNE_rel8(12 + MEM_READ_SIZE, doublesize);
  3114                         ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  3115                         MEM_READ_LONG( R_EAX, R_EAX );
  3116                         load_fr_bank( R_EDX );
  3117                         store_fr( R_EDX, R_EAX, FRn );
  3118                         if( FRn&1 ) {
  3119                     	JMP_rel8(25 + MEM_READ_DOUBLE_SIZE, end);
  3120                     	JMP_TARGET(doublesize);
  3121                     	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
  3122                     	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  3123                     	load_spreg( R_EDX, R_FPSCR ); // assume read_long clobbered it
  3124                     	load_xf_bank( R_EDX );
  3125                     	store_fr( R_EDX, R_ECX, FRn&0x0E );
  3126                     	store_fr( R_EDX, R_EAX, FRn|0x01 );
  3127                     	JMP_TARGET(end);
  3128                         } else {
  3129                     	JMP_rel8(13 + MEM_READ_DOUBLE_SIZE, end);
  3130                     	ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
  3131                     	MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  3132                     	load_fr_bank( R_EDX );
  3133                     	store_fr( R_EDX, R_ECX, FRn&0x0E );
  3134                     	store_fr( R_EDX, R_EAX, FRn|0x01 );
  3135                     	JMP_TARGET(end);
  3137                         sh4_x86.tstate = TSTATE_NONE;
  3139                         break;
  3140                     case 0xA:
  3141                         { /* FMOV FRm, @Rn */
  3142                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3143                         check_fpuen();
  3144                         load_reg( R_EAX, Rn );
  3145                         check_walign32( R_EAX );
  3146                         MMU_TRANSLATE_WRITE( R_EAX );
  3147                         load_spreg( R_EDX, R_FPSCR );
  3148                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3149                         JNE_rel8(8 + MEM_WRITE_SIZE, doublesize);
  3150                         load_fr_bank( R_EDX );
  3151                         load_fr( R_EDX, R_ECX, FRm );
  3152                         MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
  3153                         if( FRm&1 ) {
  3154                     	JMP_rel8( 18 + MEM_WRITE_DOUBLE_SIZE, end );
  3155                     	JMP_TARGET(doublesize);
  3156                     	load_xf_bank( R_EDX );
  3157                     	load_fr( R_EDX, R_ECX, FRm&0x0E );
  3158                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  3159                     	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  3160                     	JMP_TARGET(end);
  3161                         } else {
  3162                     	JMP_rel8( 9 + MEM_WRITE_DOUBLE_SIZE, end );
  3163                     	JMP_TARGET(doublesize);
  3164                     	load_fr_bank( R_EDX );
  3165                     	load_fr( R_EDX, R_ECX, FRm&0x0E );
  3166                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  3167                     	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  3168                     	JMP_TARGET(end);
  3170                         sh4_x86.tstate = TSTATE_NONE;
  3172                         break;
  3173                     case 0xB:
  3174                         { /* FMOV FRm, @-Rn */
  3175                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3176                         check_fpuen();
  3177                         load_reg( R_EAX, Rn );
  3178                         check_walign32( R_EAX );
  3179                         load_spreg( R_EDX, R_FPSCR );
  3180                         TEST_imm32_r32( FPSCR_SZ, R_EDX );
  3181                         JNE_rel8(15 + MEM_WRITE_SIZE + MMU_TRANSLATE_SIZE, doublesize);
  3182                         ADD_imm8s_r32( -4, R_EAX );
  3183                         MMU_TRANSLATE_WRITE( R_EAX );
  3184                         load_fr_bank( R_EDX );
  3185                         load_fr( R_EDX, R_ECX, FRm );
  3186                         ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
  3187                         MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
  3188                         if( FRm&1 ) {
  3189                     	JMP_rel8( 25 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
  3190                     	JMP_TARGET(doublesize);
  3191                     	ADD_imm8s_r32(-8,R_EAX);
  3192                     	MMU_TRANSLATE_WRITE( R_EAX );
  3193                     	load_xf_bank( R_EDX );
  3194                     	load_fr( R_EDX, R_ECX, FRm&0x0E );
  3195                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  3196                     	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
  3197                     	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  3198                     	JMP_TARGET(end);
  3199                         } else {
  3200                     	JMP_rel8( 16 + MEM_WRITE_DOUBLE_SIZE + MMU_TRANSLATE_SIZE, end );
  3201                     	JMP_TARGET(doublesize);
  3202                     	ADD_imm8s_r32(-8,R_EAX);
  3203                     	MMU_TRANSLATE_WRITE( R_EAX );
  3204                     	load_fr_bank( R_EDX );
  3205                     	load_fr( R_EDX, R_ECX, FRm&0x0E );
  3206                     	load_fr( R_EDX, R_EDX, FRm|0x01 );
  3207                     	ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
  3208                     	MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  3209                     	JMP_TARGET(end);
  3211                         sh4_x86.tstate = TSTATE_NONE;
  3213                         break;
  3214                     case 0xC:
  3215                         { /* FMOV FRm, FRn */
  3216                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3217                         /* As horrible as this looks, it's actually covering 5 separate cases:
  3218                          * 1. 32-bit fr-to-fr (PR=0)
  3219                          * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
  3220                          * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
  3221                          * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
  3222                          * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
  3223                          */
  3224                         check_fpuen();
  3225                         load_spreg( R_ECX, R_FPSCR );
  3226                         load_fr_bank( R_EDX );
  3227                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
  3228                         JNE_rel8(8, doublesize);
  3229                         load_fr( R_EDX, R_EAX, FRm ); // PR=0 branch
  3230                         store_fr( R_EDX, R_EAX, FRn );
  3231                         if( FRm&1 ) {
  3232                     	JMP_rel8(24, end);
  3233                     	JMP_TARGET(doublesize);
  3234                     	load_xf_bank( R_ECX ); 
  3235                     	load_fr( R_ECX, R_EAX, FRm-1 );
  3236                     	if( FRn&1 ) {
  3237                     	    load_fr( R_ECX, R_EDX, FRm );
  3238                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  3239                     	    store_fr( R_ECX, R_EDX, FRn );
  3240                     	} else /* FRn&1 == 0 */ {
  3241                     	    load_fr( R_ECX, R_ECX, FRm );
  3242                     	    store_fr( R_EDX, R_EAX, FRn );
  3243                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  3245                     	JMP_TARGET(end);
  3246                         } else /* FRm&1 == 0 */ {
  3247                     	if( FRn&1 ) {
  3248                     	    JMP_rel8(24, end);
  3249                     	    load_xf_bank( R_ECX );
  3250                     	    load_fr( R_EDX, R_EAX, FRm );
  3251                     	    load_fr( R_EDX, R_EDX, FRm+1 );
  3252                     	    store_fr( R_ECX, R_EAX, FRn-1 );
  3253                     	    store_fr( R_ECX, R_EDX, FRn );
  3254                     	    JMP_TARGET(end);
  3255                     	} else /* FRn&1 == 0 */ {
  3256                     	    JMP_rel8(12, end);
  3257                     	    load_fr( R_EDX, R_EAX, FRm );
  3258                     	    load_fr( R_EDX, R_ECX, FRm+1 );
  3259                     	    store_fr( R_EDX, R_EAX, FRn );
  3260                     	    store_fr( R_EDX, R_ECX, FRn+1 );
  3261                     	    JMP_TARGET(end);
  3264                         sh4_x86.tstate = TSTATE_NONE;
  3266                         break;
  3267                     case 0xD:
  3268                         switch( (ir&0xF0) >> 4 ) {
  3269                             case 0x0:
  3270                                 { /* FSTS FPUL, FRn */
  3271                                 uint32_t FRn = ((ir>>8)&0xF); 
  3272                                 check_fpuen();
  3273                                 load_fr_bank( R_ECX );
  3274                                 load_spreg( R_EAX, R_FPUL );
  3275                                 store_fr( R_ECX, R_EAX, FRn );
  3276                                 sh4_x86.tstate = TSTATE_NONE;
  3278                                 break;
  3279                             case 0x1:
  3280                                 { /* FLDS FRm, FPUL */
  3281                                 uint32_t FRm = ((ir>>8)&0xF); 
  3282                                 check_fpuen();
  3283                                 load_fr_bank( R_ECX );
  3284                                 load_fr( R_ECX, R_EAX, FRm );
  3285                                 store_spreg( R_EAX, R_FPUL );
  3286                                 sh4_x86.tstate = TSTATE_NONE;
  3288                                 break;
  3289                             case 0x2:
  3290                                 { /* FLOAT FPUL, FRn */
  3291                                 uint32_t FRn = ((ir>>8)&0xF); 
  3292                                 check_fpuen();
  3293                                 load_spreg( R_ECX, R_FPSCR );
  3294                                 load_spreg(R_EDX, REG_OFFSET(fr_bank));
  3295                                 FILD_sh4r(R_FPUL);
  3296                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3297                                 JNE_rel8(5, doubleprec);
  3298                                 pop_fr( R_EDX, FRn );
  3299                                 JMP_rel8(3, end);
  3300                                 JMP_TARGET(doubleprec);
  3301                                 pop_dr( R_EDX, FRn );
  3302                                 JMP_TARGET(end);
  3303                                 sh4_x86.tstate = TSTATE_NONE;
  3305                                 break;
  3306                             case 0x3:
  3307                                 { /* FTRC FRm, FPUL */
  3308                                 uint32_t FRm = ((ir>>8)&0xF); 
  3309                                 check_fpuen();
  3310                                 load_spreg( R_ECX, R_FPSCR );
  3311                                 load_fr_bank( R_EDX );
  3312                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3313                                 JNE_rel8(5, doubleprec);
  3314                                 push_fr( R_EDX, FRm );
  3315                                 JMP_rel8(3, doop);
  3316                                 JMP_TARGET(doubleprec);
  3317                                 push_dr( R_EDX, FRm );
  3318                                 JMP_TARGET( doop );
  3319                                 load_imm32( R_ECX, (uint32_t)&max_int );
  3320                                 FILD_r32ind( R_ECX );
  3321                                 FCOMIP_st(1);
  3322                                 JNA_rel8( 32, sat );
  3323                                 load_imm32( R_ECX, (uint32_t)&min_int );  // 5
  3324                                 FILD_r32ind( R_ECX );           // 2
  3325                                 FCOMIP_st(1);                   // 2
  3326                                 JAE_rel8( 21, sat2 );            // 2
  3327                                 load_imm32( R_EAX, (uint32_t)&save_fcw );
  3328                                 FNSTCW_r32ind( R_EAX );
  3329                                 load_imm32( R_EDX, (uint32_t)&trunc_fcw );
  3330                                 FLDCW_r32ind( R_EDX );
  3331                                 FISTP_sh4r(R_FPUL);             // 3
  3332                                 FLDCW_r32ind( R_EAX );
  3333                                 JMP_rel8( 9, end );             // 2
  3335                                 JMP_TARGET(sat);
  3336                                 JMP_TARGET(sat2);
  3337                                 MOV_r32ind_r32( R_ECX, R_ECX ); // 2
  3338                                 store_spreg( R_ECX, R_FPUL );
  3339                                 FPOP_st();
  3340                                 JMP_TARGET(end);
  3341                                 sh4_x86.tstate = TSTATE_NONE;
  3343                                 break;
  3344                             case 0x4:
  3345                                 { /* FNEG FRn */
  3346                                 uint32_t FRn = ((ir>>8)&0xF); 
  3347                                 check_fpuen();
  3348                                 load_spreg( R_ECX, R_FPSCR );
  3349                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3350                                 load_fr_bank( R_EDX );
  3351                                 JNE_rel8(10, doubleprec);
  3352                                 push_fr(R_EDX, FRn);
  3353                                 FCHS_st0();
  3354                                 pop_fr(R_EDX, FRn);
  3355                                 JMP_rel8(8, end);
  3356                                 JMP_TARGET(doubleprec);
  3357                                 push_dr(R_EDX, FRn);
  3358                                 FCHS_st0();
  3359                                 pop_dr(R_EDX, FRn);
  3360                                 JMP_TARGET(end);
  3361                                 sh4_x86.tstate = TSTATE_NONE;
  3363                                 break;
  3364                             case 0x5:
  3365                                 { /* FABS FRn */
  3366                                 uint32_t FRn = ((ir>>8)&0xF); 
  3367                                 check_fpuen();
  3368                                 load_spreg( R_ECX, R_FPSCR );
  3369                                 load_fr_bank( R_EDX );
  3370                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3371                                 JNE_rel8(10, doubleprec);
  3372                                 push_fr(R_EDX, FRn); // 3
  3373                                 FABS_st0(); // 2
  3374                                 pop_fr( R_EDX, FRn); //3
  3375                                 JMP_rel8(8,end); // 2
  3376                                 JMP_TARGET(doubleprec);
  3377                                 push_dr(R_EDX, FRn);
  3378                                 FABS_st0();
  3379                                 pop_dr(R_EDX, FRn);
  3380                                 JMP_TARGET(end);
  3381                                 sh4_x86.tstate = TSTATE_NONE;
  3383                                 break;
  3384                             case 0x6:
  3385                                 { /* FSQRT FRn */
  3386                                 uint32_t FRn = ((ir>>8)&0xF); 
  3387                                 check_fpuen();
  3388                                 load_spreg( R_ECX, R_FPSCR );
  3389                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3390                                 load_fr_bank( R_EDX );
  3391                                 JNE_rel8(10, doubleprec);
  3392                                 push_fr(R_EDX, FRn);
  3393                                 FSQRT_st0();
  3394                                 pop_fr(R_EDX, FRn);
  3395                                 JMP_rel8(8, end);
  3396                                 JMP_TARGET(doubleprec);
  3397                                 push_dr(R_EDX, FRn);
  3398                                 FSQRT_st0();
  3399                                 pop_dr(R_EDX, FRn);
  3400                                 JMP_TARGET(end);
  3401                                 sh4_x86.tstate = TSTATE_NONE;
  3403                                 break;
  3404                             case 0x7:
  3405                                 { /* FSRRA FRn */
  3406                                 uint32_t FRn = ((ir>>8)&0xF); 
  3407                                 check_fpuen();
  3408                                 load_spreg( R_ECX, R_FPSCR );
  3409                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3410                                 load_fr_bank( R_EDX );
  3411                                 JNE_rel8(12, end); // PR=0 only
  3412                                 FLD1_st0();
  3413                                 push_fr(R_EDX, FRn);
  3414                                 FSQRT_st0();
  3415                                 FDIVP_st(1);
  3416                                 pop_fr(R_EDX, FRn);
  3417                                 JMP_TARGET(end);
  3418                                 sh4_x86.tstate = TSTATE_NONE;
  3420                                 break;
  3421                             case 0x8:
  3422                                 { /* FLDI0 FRn */
  3423                                 uint32_t FRn = ((ir>>8)&0xF); 
  3424                                 /* IFF PR=0 */
  3425                                   check_fpuen();
  3426                                   load_spreg( R_ECX, R_FPSCR );
  3427                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3428                                   JNE_rel8(8, end);
  3429                                   XOR_r32_r32( R_EAX, R_EAX );
  3430                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3431                                   store_fr( R_ECX, R_EAX, FRn );
  3432                                   JMP_TARGET(end);
  3433                                   sh4_x86.tstate = TSTATE_NONE;
  3435                                 break;
  3436                             case 0x9:
  3437                                 { /* FLDI1 FRn */
  3438                                 uint32_t FRn = ((ir>>8)&0xF); 
  3439                                 /* IFF PR=0 */
  3440                                   check_fpuen();
  3441                                   load_spreg( R_ECX, R_FPSCR );
  3442                                   TEST_imm32_r32( FPSCR_PR, R_ECX );
  3443                                   JNE_rel8(11, end);
  3444                                   load_imm32(R_EAX, 0x3F800000);
  3445                                   load_spreg( R_ECX, REG_OFFSET(fr_bank) );
  3446                                   store_fr( R_ECX, R_EAX, FRn );
  3447                                   JMP_TARGET(end);
  3448                                   sh4_x86.tstate = TSTATE_NONE;
  3450                                 break;
  3451                             case 0xA:
  3452                                 { /* FCNVSD FPUL, FRn */
  3453                                 uint32_t FRn = ((ir>>8)&0xF); 
  3454                                 check_fpuen();
  3455                                 load_spreg( R_ECX, R_FPSCR );
  3456                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3457                                 JE_rel8(9, end); // only when PR=1
  3458                                 load_fr_bank( R_ECX );
  3459                                 push_fpul();
  3460                                 pop_dr( R_ECX, FRn );
  3461                                 JMP_TARGET(end);
  3462                                 sh4_x86.tstate = TSTATE_NONE;
  3464                                 break;
  3465                             case 0xB:
  3466                                 { /* FCNVDS FRm, FPUL */
  3467                                 uint32_t FRm = ((ir>>8)&0xF); 
  3468                                 check_fpuen();
  3469                                 load_spreg( R_ECX, R_FPSCR );
  3470                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3471                                 JE_rel8(9, end); // only when PR=1
  3472                                 load_fr_bank( R_ECX );
  3473                                 push_dr( R_ECX, FRm );
  3474                                 pop_fpul();
  3475                                 JMP_TARGET(end);
  3476                                 sh4_x86.tstate = TSTATE_NONE;
  3478                                 break;
  3479                             case 0xE:
  3480                                 { /* FIPR FVm, FVn */
  3481                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  3482                                 check_fpuen();
  3483                                 load_spreg( R_ECX, R_FPSCR );
  3484                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3485                                 JNE_rel8(44, doubleprec);
  3487                                 load_fr_bank( R_ECX );
  3488                                 push_fr( R_ECX, FVm<<2 );
  3489                                 push_fr( R_ECX, FVn<<2 );
  3490                                 FMULP_st(1);
  3491                                 push_fr( R_ECX, (FVm<<2)+1);
  3492                                 push_fr( R_ECX, (FVn<<2)+1);
  3493                                 FMULP_st(1);
  3494                                 FADDP_st(1);
  3495                                 push_fr( R_ECX, (FVm<<2)+2);
  3496                                 push_fr( R_ECX, (FVn<<2)+2);
  3497                                 FMULP_st(1);
  3498                                 FADDP_st(1);
  3499                                 push_fr( R_ECX, (FVm<<2)+3);
  3500                                 push_fr( R_ECX, (FVn<<2)+3);
  3501                                 FMULP_st(1);
  3502                                 FADDP_st(1);
  3503                                 pop_fr( R_ECX, (FVn<<2)+3);
  3504                                 JMP_TARGET(doubleprec);
  3505                                 sh4_x86.tstate = TSTATE_NONE;
  3507                                 break;
  3508                             case 0xF:
  3509                                 switch( (ir&0x100) >> 8 ) {
  3510                                     case 0x0:
  3511                                         { /* FSCA FPUL, FRn */
  3512                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  3513                                         check_fpuen();
  3514                                         load_spreg( R_ECX, R_FPSCR );
  3515                                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3516                                         JNE_rel8( CALL_FUNC2_SIZE + 9, doubleprec );
  3517                                         load_fr_bank( R_ECX );
  3518                                         ADD_imm8s_r32( (FRn&0x0E)<<2, R_ECX );
  3519                                         load_spreg( R_EDX, R_FPUL );
  3520                                         call_func2( sh4_fsca, R_EDX, R_ECX );
  3521                                         JMP_TARGET(doubleprec);
  3522                                         sh4_x86.tstate = TSTATE_NONE;
  3524                                         break;
  3525                                     case 0x1:
  3526                                         switch( (ir&0x200) >> 9 ) {
  3527                                             case 0x0:
  3528                                                 { /* FTRV XMTRX, FVn */
  3529                                                 uint32_t FVn = ((ir>>10)&0x3); 
  3530                                                 check_fpuen();
  3531                                                 load_spreg( R_ECX, R_FPSCR );
  3532                                                 TEST_imm32_r32( FPSCR_PR, R_ECX );
  3533                                                 JNE_rel8( 18 + CALL_FUNC2_SIZE, doubleprec );
  3534                                                 load_fr_bank( R_EDX );                 // 3
  3535                                                 ADD_imm8s_r32( FVn<<4, R_EDX );        // 3
  3536                                                 load_xf_bank( R_ECX );                 // 12
  3537                                                 call_func2( sh4_ftrv, R_EDX, R_ECX );  // 12
  3538                                                 JMP_TARGET(doubleprec);
  3539                                                 sh4_x86.tstate = TSTATE_NONE;
  3541                                                 break;
  3542                                             case 0x1:
  3543                                                 switch( (ir&0xC00) >> 10 ) {
  3544                                                     case 0x0:
  3545                                                         { /* FSCHG */
  3546                                                         check_fpuen();
  3547                                                         load_spreg( R_ECX, R_FPSCR );
  3548                                                         XOR_imm32_r32( FPSCR_SZ, R_ECX );
  3549                                                         store_spreg( R_ECX, R_FPSCR );
  3550                                                         sh4_x86.tstate = TSTATE_NONE;
  3552                                                         break;
  3553                                                     case 0x2:
  3554                                                         { /* FRCHG */
  3555                                                         check_fpuen();
  3556                                                         load_spreg( R_ECX, R_FPSCR );
  3557                                                         XOR_imm32_r32( FPSCR_FR, R_ECX );
  3558                                                         store_spreg( R_ECX, R_FPSCR );
  3559                                                         update_fr_bank( R_ECX );
  3560                                                         sh4_x86.tstate = TSTATE_NONE;
  3562                                                         break;
  3563                                                     case 0x3:
  3564                                                         { /* UNDEF */
  3565                                                         if( sh4_x86.in_delay_slot ) {
  3566                                                     	SLOTILLEGAL();
  3567                                                         } else {
  3568                                                     	JMP_exc(EXC_ILLEGAL);
  3569                                                     	return 2;
  3572                                                         break;
  3573                                                     default:
  3574                                                         UNDEF();
  3575                                                         break;
  3577                                                 break;
  3579                                         break;
  3581                                 break;
  3582                             default:
  3583                                 UNDEF();
  3584                                 break;
  3586                         break;
  3587                     case 0xE:
  3588                         { /* FMAC FR0, FRm, FRn */
  3589                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  3590                         check_fpuen();
  3591                         load_spreg( R_ECX, R_FPSCR );
  3592                         load_spreg( R_EDX, REG_OFFSET(fr_bank));
  3593                         TEST_imm32_r32( FPSCR_PR, R_ECX );
  3594                         JNE_rel8(18, doubleprec);
  3595                         push_fr( R_EDX, 0 );
  3596                         push_fr( R_EDX, FRm );
  3597                         FMULP_st(1);
  3598                         push_fr( R_EDX, FRn );
  3599                         FADDP_st(1);
  3600                         pop_fr( R_EDX, FRn );
  3601                         JMP_rel8(16, end);
  3602                         JMP_TARGET(doubleprec);
  3603                         push_dr( R_EDX, 0 );
  3604                         push_dr( R_EDX, FRm );
  3605                         FMULP_st(1);
  3606                         push_dr( R_EDX, FRn );
  3607                         FADDP_st(1);
  3608                         pop_dr( R_EDX, FRn );
  3609                         JMP_TARGET(end);
  3610                         sh4_x86.tstate = TSTATE_NONE;
  3612                         break;
  3613                     default:
  3614                         UNDEF();
  3615                         break;
  3617                 break;
  3620     sh4_x86.in_delay_slot = DELAY_NONE;
  3621     return 0;
.