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lxdream.org :: lxdream/src/sh4/sh4core.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.h
changeset 564:dc7b5ffb0535
prev561:533f6b478071
next569:a1c49e1e8776
author nkeynes
date Tue Jan 01 08:37:26 2008 +0000 (14 years ago)
branchlxdream-mmu
permissions -rw-r--r--
last change Refactor sh4core.h to extract the "public" material into a new sh4.h
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     1 /**
     2  * $Id$
     3  * 
     4  * This file defines the internal functions exported/used by the SH4 core, 
     5  * except for disassembly functions defined in sh4dasm.h
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #ifndef sh4core_H
    21 #define sh4core_H 1
    23 #include <glib/gtypes.h>
    24 #include <stdint.h>
    25 #include <stdio.h>
    26 #include "mem.h"
    27 #include "sh4/sh4.h"
    29 #ifdef __cplusplus
    30 extern "C" {
    31 #endif
    33 /* Breakpoint data structure */
    34 extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    35 extern int sh4_breakpoint_count;
    37 /* SH4 module functions */
    38 void sh4_init( void );
    39 void sh4_reset( void );
    40 void sh4_run( void );
    41 void sh4_stop( void );
    43 /* SH4 peripheral module functions */
    44 void CPG_reset( void );
    45 void DMAC_reset( void );
    46 void DMAC_run_slice( uint32_t );
    47 void DMAC_save_state( FILE * );
    48 int DMAC_load_state( FILE * );
    49 void INTC_reset( void );
    50 void INTC_save_state( FILE *f );
    51 int INTC_load_state( FILE *f );
    52 void MMU_init( void );
    53 void MMU_reset( void );
    54 void MMU_save_state( FILE *f );
    55 int MMU_load_state( FILE *f );
    56 void MMU_ldtlb();
    57 void SCIF_reset( void );
    58 void SCIF_run_slice( uint32_t );
    59 void SCIF_save_state( FILE *f );
    60 int SCIF_load_state( FILE *f );
    61 void SCIF_update_line_speed(void);
    62 void TMU_reset( void );
    63 void TMU_run_slice( uint32_t );
    64 void TMU_save_state( FILE * );
    65 int TMU_load_state( FILE * );
    66 void TMU_update_clocks( void );
    68 /* SH4 instruction support methods */
    69 void sh4_sleep( void );
    70 void sh4_fsca( uint32_t angle, float *fr );
    71 void sh4_ftrv( float *fv, float *xmtrx );
    72 uint32_t sh4_read_sr(void);
    73 void sh4_write_sr(uint32_t val);
    74 void signsat48(void);
    76 /* SH4 Memory */
    77 uint64_t mmu_vma_to_phys_read( sh4addr_t addr );
    78 uint64_t mmu_vma_to_phys_write( sh4addr_t addr );
    79 uint64_t mmu_vma_to_phys_exec( sh4addr_t addr );
    81 int64_t sh4_read_quad( sh4addr_t addr );
    82 int64_t sh4_read_long( sh4addr_t addr );
    83 int64_t sh4_read_word( sh4addr_t addr );
    84 int64_t sh4_read_byte( sh4addr_t addr );
    85 void sh4_write_quad( sh4addr_t addr, uint64_t val );
    86 int32_t sh4_write_long( sh4addr_t addr, uint32_t val );
    87 int32_t sh4_write_word( sh4addr_t addr, uint32_t val );
    88 int32_t sh4_write_byte( sh4addr_t addr, uint32_t val );
    89 int32_t sh4_read_phys_word( sh4addr_t addr );
    90 void sh4_flush_store_queue( sh4addr_t addr );
    91 sh4ptr_t sh4_get_region_by_vma( sh4addr_t addr );
    93 /* SH4 Exceptions */
    94 #define EXC_POWER_RESET     0x000 /* reset vector */
    95 #define EXC_MANUAL_RESET    0x020 /* reset vector */
    96 #define EXC_TLB_MISS_READ   0x040 /* TLB vector */
    97 #define EXC_TLB_MISS_WRITE  0x060 /* TLB vector */
    98 #define EXC_INIT_PAGE_WRITE 0x080
    99 #define EXC_TLB_PROT_READ   0x0A0
   100 #define EXC_TLB_PROT_WRITE  0x0C0
   101 #define EXC_DATA_ADDR_READ  0x0E0
   102 #define EXC_DATA_ADDR_WRITE 0x100
   103 #define EXC_TLB_MULTI_HIT   0x140
   104 #define EXC_SLOT_ILLEGAL    0x1A0
   105 #define EXC_ILLEGAL         0x180
   106 #define EXC_TRAP            0x160
   107 #define EXC_FPU_DISABLED    0x800
   108 #define EXC_SLOT_FPU_DISABLED 0x820
   110 #define EXV_EXCEPTION    0x100  /* General exception vector */
   111 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
   112 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
   114 gboolean sh4_raise_exception( int );
   115 gboolean sh4_raise_reset( int );
   116 gboolean sh4_raise_trap( int );
   117 gboolean sh4_raise_slot_exception( int, int );
   118 gboolean sh4_raise_tlb_exception( int );
   119 void sh4_accept_interrupt( void );
   121 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
   122 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
   123 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
   124 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
   125 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
   126 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
   127 #define ZEROEXT32(n) ((int64_t)((uint64_t)((uint32_t)(n))))
   129 /* Status Register (SR) bits */
   130 #define SR_MD    0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ 
   131 #define SR_RB    0x20000000 /* Register bank (priviledged mode only) */
   132 #define SR_BL    0x10000000 /* Exception/interupt block (1 = masked) */
   133 #define SR_FD    0x00008000 /* FPU disable */
   134 #define SR_M     0x00000200
   135 #define SR_Q     0x00000100
   136 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
   137 #define SR_S     0x00000002 /* Saturation operation for MAC instructions */
   138 #define SR_T     0x00000001 /* True/false or carry/borrow */
   139 #define SR_MASK  0x700083F3
   140 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
   142 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
   143 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
   144 #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
   146 #define FPSCR_FR     0x00200000 /* FPU register bank */
   147 #define FPSCR_SZ     0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
   148 #define FPSCR_PR     0x00080000 /* Precision (0=32 bites, 1=64 bits) */
   149 #define FPSCR_DN     0x00040000 /* Denormalization mode (1 = treat as 0) */
   150 #define FPSCR_CAUSE  0x0003F000
   151 #define FPSCR_ENABLE 0x00000F80
   152 #define FPSCR_FLAG   0x0000007C
   153 #define FPSCR_RM     0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
   155 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
   156 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
   157 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
   159 #define FR(x) sh4r.fr_bank[(x)^1]
   160 #define DRF(x) ((double *)sh4r.fr_bank)[x]
   161 #define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1]
   162 #define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x]
   163 #define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x]
   164 #define DR(x) DRb((x>>1), (x&1))
   165 #define FPULf   *((float *)&sh4r.fpul)
   166 #define FPULi    (sh4r.fpul)
   168 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
   170 #ifdef __cplusplus
   171 }
   172 #endif
   173 #endif
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