2 * $Id: aica.c,v 1.9 2005-12-26 11:52:56 nkeynes Exp $
4 * This is the core sound system (ie the bit which does the actual work)
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #define MODULE aica_module
27 MMIO_REGION_READ_DEFFN( AICA0 )
28 MMIO_REGION_READ_DEFFN( AICA1 )
29 MMIO_REGION_READ_DEFFN( AICA2 )
31 void aica_init( void );
32 void aica_reset( void );
33 void aica_start( void );
34 void aica_stop( void );
35 void aica_save_state( FILE *f );
36 int aica_load_state( FILE *f );
37 uint32_t aica_run_slice( uint32_t );
40 struct dreamcast_module aica_module = { "AICA", aica_init, aica_reset,
41 aica_start, aica_run_slice, aica_stop,
42 aica_save_state, aica_load_state };
45 * Initialize the AICA subsystem. Note requires that
47 void aica_init( void )
49 register_io_regions( mmio_list_spu );
56 void aica_reset( void )
61 void aica_start( void )
66 uint32_t aica_run_slice( uint32_t nanosecs )
68 /* Run arm instructions */
69 int reset = MMIO_READ( AICA2, AICA_RESET );
70 if( (reset & 1) == 0 ) {
72 nanosecs = arm_run_slice( nanosecs );
74 /* Generate audio buffer */
78 void aica_stop( void )
83 void aica_save_state( FILE *f )
88 int aica_load_state( FILE *f )
90 return arm_load_state( f );
93 /** Channel register structure:
95 * 04 4 Waveform address lo (16 bits)
96 * 08 4 Loop start address
97 * 0C 4 Loop end address
98 * 10 4 Volume envelope
100 * 18 4 Frequency (floating point)
113 /* Write to channels 0-31 */
114 void mmio_region_AICA0_write( uint32_t reg, uint32_t val )
116 // aica_write_channel( reg >> 7, reg % 128, val );
117 MMIO_WRITE( AICA0, reg, val );
118 // DEBUG( "AICA0 Write %08X => %08X", val, reg );
121 /* Write to channels 32-64 */
122 void mmio_region_AICA1_write( uint32_t reg, uint32_t val )
124 // aica_write_channel( (reg >> 7) + 32, reg % 128, val );
125 MMIO_WRITE( AICA1, reg, val );
126 // DEBUG( "AICA1 Write %08X => %08X", val, reg );
129 /* General registers */
130 void mmio_region_AICA2_write( uint32_t reg, uint32_t val )
135 tmp = MMIO_READ( AICA2, AICA_RESET );
136 if( (tmp & 1) == 1 && (val & 1) == 0 ) {
137 /* ARM enabled - execute a core reset */
138 DEBUG( "ARM enabled" );
140 } else if( (tmp&1) == 0 && (val&1) == 1 ) {
141 DEBUG( "ARM disabled" );
143 MMIO_WRITE( AICA2, AICA_RESET, val );
146 MMIO_WRITE( AICA2, reg, val );
.