lxdream 0.9.1| filename | src/pvr2/pvr2.c |
| changeset | 191:df4441cf3128 |
| prev | 189:615b70cfd729 |
| next | 193:31151fcc3cb7 |
| author | nkeynes |
| date | Wed Aug 02 06:24:08 2006 +0000 (17 years ago) |
| permissions | -rw-r--r-- |
| last change | Add more register masks (in line with test case) Rename renderer registers for consistency |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: pvr2.c,v 1.29 2006-08-02 06:24:08 nkeynes Exp $
3 *
4 * PVR2 (Video) Core module implementation and MMIO registers.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18 #define MODULE pvr2_module
20 #include "dream.h"
21 #include "display.h"
22 #include "mem.h"
23 #include "asic.h"
24 #include "pvr2/pvr2.h"
25 #include "sh4/sh4core.h"
26 #define MMIO_IMPL
27 #include "pvr2/pvr2mmio.h"
29 char *video_base;
31 static void pvr2_init( void );
32 static void pvr2_reset( void );
33 static uint32_t pvr2_run_slice( uint32_t );
34 static void pvr2_save_state( FILE *f );
35 static int pvr2_load_state( FILE *f );
37 void pvr2_display_frame( void );
39 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
41 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
42 pvr2_run_slice, NULL,
43 pvr2_save_state, pvr2_load_state };
46 display_driver_t display_driver = NULL;
48 struct video_timing {
49 int fields_per_second;
50 int total_lines;
51 int retrace_lines;
52 int line_time_ns;
53 };
55 struct video_timing pal_timing = { 50, 625, 65, 32000 };
56 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
58 struct pvr2_state {
59 uint32_t frame_count;
60 uint32_t line_count;
61 uint32_t line_remainder;
62 uint32_t irq_vpos1;
63 uint32_t irq_vpos2;
64 gboolean retrace;
65 struct video_timing timing;
66 } pvr2_state;
68 struct video_buffer video_buffer[2];
69 int video_buffer_idx = 0;
71 static void pvr2_init( void )
72 {
73 register_io_region( &mmio_region_PVR2 );
74 register_io_region( &mmio_region_PVR2PAL );
75 register_io_region( &mmio_region_PVR2TA );
76 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
77 texcache_init();
78 pvr2_reset();
79 }
81 static void pvr2_reset( void )
82 {
83 pvr2_state.line_count = 0;
84 pvr2_state.line_remainder = 0;
85 pvr2_state.irq_vpos1 = 0;
86 pvr2_state.irq_vpos2 = 0;
87 pvr2_state.retrace = FALSE;
88 pvr2_state.timing = ntsc_timing;
89 video_buffer_idx = 0;
91 pvr2_ta_init();
92 pvr2_render_init();
93 texcache_flush();
94 }
96 static void pvr2_save_state( FILE *f )
97 {
98 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
99 }
101 static int pvr2_load_state( FILE *f )
102 {
103 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
104 return 1;
105 return 0;
106 }
108 static uint32_t pvr2_run_slice( uint32_t nanosecs )
109 {
110 pvr2_state.line_remainder += nanosecs;
111 while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
112 pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
114 pvr2_state.line_count++;
115 if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
116 asic_event( EVENT_RETRACE );
117 pvr2_state.line_count = 0;
118 pvr2_state.retrace = TRUE;
119 }
121 if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
122 asic_event( EVENT_SCANLINE1 );
123 }
124 if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
125 asic_event( EVENT_SCANLINE2 );
126 }
128 if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
129 if( pvr2_state.retrace ) {
130 pvr2_display_frame();
131 pvr2_state.retrace = FALSE;
132 }
133 }
134 }
135 return nanosecs;
136 }
138 int pvr2_get_frame_count()
139 {
140 return pvr2_state.frame_count;
141 }
143 /**
144 * Display the next frame, copying the current contents of video ram to
145 * the window. If the video configuration has changed, first recompute the
146 * new frame size/depth.
147 */
148 void pvr2_display_frame( void )
149 {
150 uint32_t display_addr = MMIO_READ( PVR2, DISPADDR1 );
152 int dispsize = MMIO_READ( PVR2, DISPSIZE );
153 int dispmode = MMIO_READ( PVR2, DISPMODE );
154 int vidcfg = MMIO_READ( PVR2, DISPCFG );
155 int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
156 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
157 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
158 gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
159 gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
160 video_buffer_t buffer = &video_buffer[video_buffer_idx];
161 video_buffer_idx = !video_buffer_idx;
162 video_buffer_t last = &video_buffer[video_buffer_idx];
163 buffer->rowstride = (vid_ppl + vid_stride) << 2;
164 buffer->data = video_base + MMIO_READ( PVR2, DISPADDR1 );
165 buffer->vres = vid_lpf;
166 if( interlaced ) buffer->vres <<= 1;
167 switch( (dispmode & DISPMODE_COL) >> 2 ) {
168 case 0:
169 buffer->colour_format = COLFMT_ARGB1555;
170 buffer->hres = vid_ppl << 1;
171 break;
172 case 1:
173 buffer->colour_format = COLFMT_RGB565;
174 buffer->hres = vid_ppl << 1;
175 break;
176 case 2:
177 buffer->colour_format = COLFMT_RGB888;
178 buffer->hres = (vid_ppl << 2) / 3;
179 break;
180 case 3:
181 buffer->colour_format = COLFMT_ARGB8888;
182 buffer->hres = vid_ppl;
183 break;
184 }
186 if( buffer->hres <=8 )
187 buffer->hres = 640;
188 if( buffer->vres <=8 )
189 buffer->vres = 480;
190 if( display_driver != NULL ) {
191 if( buffer->hres != last->hres ||
192 buffer->vres != last->vres ||
193 buffer->colour_format != last->colour_format) {
194 display_driver->set_display_format( buffer->hres, buffer->vres,
195 buffer->colour_format );
196 }
197 if( !bEnabled ) {
198 display_driver->display_blank_frame( 0 );
199 } else if( MMIO_READ( PVR2, DISPCFG2 ) & 0x08 ) { /* Blanked */
200 uint32_t colour = MMIO_READ( PVR2, DISPBORDER );
201 display_driver->display_blank_frame( colour );
202 } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
203 display_driver->display_frame( buffer );
204 }
205 }
206 pvr2_state.frame_count++;
207 }
209 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
210 {
211 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
212 MMIO_WRITE( PVR2, reg, val );
213 /* I don't want to hear about these */
214 return;
215 }
217 switch(reg) {
218 case PVRID:
219 case PVRVER:
220 case GUNPOS:
221 case TA_POLYPOS:
222 case TA_LISTPOS:
223 /* Readonly registers */
224 break;
225 case RENDER_START:
226 if( val == 0xFFFFFFFF )
227 pvr2_render_scene();
228 break;
229 case PVRUNK1:
230 MMIO_WRITE( PVR2, reg, val&0x000007FF );
231 break;
232 case RENDER_POLYBASE:
233 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
234 break;
235 case RENDER_TSPCFG:
236 MMIO_WRITE( PVR2, reg, val&0x00010101 );
237 break;
238 case DISPBORDER:
239 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
240 break;
241 case DISPMODE:
242 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
243 break;
244 case RENDER_MODE:
245 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
246 break;
247 case RENDER_SIZE:
248 MMIO_WRITE( PVR2, reg, val&0x000001FF );
249 break;
250 case DISPADDR1:
251 val &= 0x00FFFFFC;
252 MMIO_WRITE( PVR2, reg, val );
253 if( pvr2_state.retrace ) {
254 pvr2_display_frame();
255 pvr2_state.retrace = FALSE;
256 }
257 break;
258 case DISPADDR2:
259 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
260 break;
261 case DISPSIZE:
262 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
263 break;
264 case RENDER_ADDR1:
265 case RENDER_ADDR2:
266 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
267 break;
268 case RENDER_HCLIP:
269 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
270 break;
271 case RENDER_VCLIP:
272 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
273 break;
274 case HPOS_IRQ:
275 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
276 break;
277 case VPOS_IRQ:
278 val = val & 0x03FF03FF;
279 pvr2_state.irq_vpos1 = (val >> 16);
280 pvr2_state.irq_vpos2 = val & 0x03FF;
281 MMIO_WRITE( PVR2, reg, val );
282 break;
283 case RENDER_SHADOW:
284 MMIO_WRITE( PVR2, reg, val&0x000001FF );
285 break;
286 case RENDER_OBJCFG:
287 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
288 break;
289 case RENDER_TSPCLIP:
290 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
291 break;
292 case RENDER_BGPLANE:
293 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
294 break;
295 case RENDER_ISPCFG:
296 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
297 break;
298 case TA_TILEBASE:
299 case TA_TILEEND:
300 case TA_LISTBASE:
301 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
302 break;
303 case RENDER_TILEBASE:
304 case TA_POLYBASE:
305 case TA_POLYEND:
306 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
307 break;
308 case TA_TILESIZE:
309 MMIO_WRITE( PVR2, reg, val&0x000F003F );
310 break;
311 case TA_TILECFG:
312 MMIO_WRITE( PVR2, reg, val&0x00133333 );
313 break;
314 case TA_INIT:
315 if( val & 0x80000000 )
316 pvr2_ta_init();
317 break;
319 /* Nonexistent registers (as far as we know, anyway) */
320 case 0x01C:
321 case 0x024:
322 case 0x028:
323 case 0x058:
324 break;
325 default:
326 MMIO_WRITE( PVR2, reg, val );
327 }
328 }
330 MMIO_REGION_READ_FN( PVR2, reg )
331 {
332 switch( reg ) {
333 case BEAMPOS:
334 return sh4r.icount&0x20 ? 0x2000 : 1;
335 default:
336 return MMIO_READ( PVR2, reg );
337 }
338 }
340 MMIO_REGION_DEFFNS( PVR2PAL )
342 void pvr2_set_base_address( uint32_t base )
343 {
344 mmio_region_PVR2_write( DISPADDR1, base );
345 }
350 int32_t mmio_region_PVR2TA_read( uint32_t reg )
351 {
352 return 0xFFFFFFFF;
353 }
355 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
356 {
357 pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
358 }
361 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
362 {
363 int bank_flag = (destaddr & 0x04) >> 2;
364 uint32_t *banks[2];
365 uint32_t *dwsrc;
366 int i;
368 destaddr = destaddr & 0x7FFFFF;
369 if( destaddr + length > 0x800000 ) {
370 length = 0x800000 - destaddr;
371 }
373 for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
374 texcache_invalidate_page( i );
375 }
377 banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
378 banks[1] = banks[0] + 0x100000;
379 if( bank_flag )
380 banks[0]++;
382 /* Handle non-aligned start of source */
383 if( destaddr & 0x03 ) {
384 char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
385 for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
386 *dest++ = *src++;
387 }
388 bank_flag = !bank_flag;
389 }
391 dwsrc = (uint32_t *)src;
392 while( length >= 4 ) {
393 *banks[bank_flag]++ = *dwsrc++;
394 bank_flag = !bank_flag;
395 length -= 4;
396 }
398 /* Handle non-aligned end of source */
399 if( length ) {
400 src = (char *)dwsrc;
401 char *dest = (char *)banks[bank_flag];
402 while( length-- > 0 ) {
403 *dest++ = *src++;
404 }
405 }
407 }
409 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
410 {
411 int bank_flag = (srcaddr & 0x04) >> 2;
412 uint32_t *banks[2];
413 uint32_t *dwdest;
414 int i;
416 srcaddr = srcaddr & 0x7FFFFF;
417 if( srcaddr + length > 0x800000 )
418 length = 0x800000 - srcaddr;
420 banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
421 banks[1] = banks[0] + 0x100000;
422 if( bank_flag )
423 banks[0]++;
425 /* Handle non-aligned start of source */
426 if( srcaddr & 0x03 ) {
427 char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
428 for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
429 *dest++ = *src++;
430 }
431 bank_flag = !bank_flag;
432 }
434 dwdest = (uint32_t *)dest;
435 while( length >= 4 ) {
436 *dwdest++ = *banks[bank_flag]++;
437 bank_flag = !bank_flag;
438 length -= 4;
439 }
441 /* Handle non-aligned end of source */
442 if( length ) {
443 dest = (char *)dwdest;
444 char *src = (char *)banks[bank_flag];
445 while( length-- > 0 ) {
446 *dest++ = *src++;
447 }
448 }
449 }
451 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f )
452 {
453 char tmp[length];
454 pvr2_vram64_read( tmp, addr, length );
455 fwrite_dump( tmp, length, f );
456 }
.