filename | src/pvr2/pvr2.h |
changeset | 189:615b70cfd729 |
prev | 161:408b9210395f |
next | 219:dfd3292143f2 |
author | nkeynes |
date | Wed Aug 02 06:24:08 2006 +0000 (17 years ago) |
permissions | -rw-r--r-- |
last change | Add more register masks (in line with test case) Rename renderer registers for consistency |
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1 /**
2 * $Id: pvr2.h,v 1.15 2006-08-02 04:06:45 nkeynes Exp $
3 *
4 * PVR2 (video chip) functions and macros.
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #include "dream.h"
20 #include "mem.h"
21 #include "display.h"
22 #include "pvr2/pvr2mmio.h"
23 #include <GL/gl.h>
25 typedef unsigned int pvraddr_t;
26 typedef unsigned int pvr64addr_t;
28 #define DISPMODE_DE 0x00000001 /* Display enable */
29 #define DISPMODE_SD 0x00000002 /* Scan double */
30 #define DISPMODE_COL 0x0000000C /* Colour mode */
31 #define DISPMODE_CD 0x08000000 /* Clock double */
33 #define COLFMT_RGB15 0x00000000
34 #define COLFMT_RGB16 0x00000004
35 #define COLFMT_RGB24 0x00000008
36 #define COLFMT_RGB32 0x0000000C
38 #define DISPSIZE_MODULO 0x3FF00000 /* line skip +1 (32-bit words)*/
39 #define DISPSIZE_LPF 0x000FFC00 /* lines per field */
40 #define DISPSIZE_PPL 0x000003FF /* pixel words (32 bit) per line */
42 #define DISPCFG_VP 0x00000001 /* V-sync polarity */
43 #define DISPCFG_HP 0x00000002 /* H-sync polarity */
44 #define DISPCFG_I 0x00000010 /* Interlace enable */
45 #define DISPCFG_BS 0x000000C0 /* Broadcast standard */
46 #define DISPCFG_VO 0x00000100 /* Video output enable */
48 #define BS_NTSC 0x00000000
49 #define BS_PAL 0x00000040
50 #define BS_PALM 0x00000080 /* ? */
51 #define BS_PALN 0x000000C0 /* ? */
53 #define PVR2_RAM_BASE 0x05000000
54 #define PVR2_RAM_BASE_INT 0x04000000
55 #define PVR2_RAM_SIZE (8 * 1024 * 1024)
56 #define PVR2_RAM_PAGES (PVR2_RAM_SIZE>>12)
57 #define PVR2_RAM_MASK 0x7FFFFF
59 void pvr2_next_frame( void );
60 void pvr2_set_base_address( uint32_t );
61 int pvr2_get_frame_count( void );
63 #define PVR2_CMD_END_OF_LIST 0x00
64 #define PVR2_CMD_USER_CLIP 0x20
65 #define PVR2_CMD_POLY_OPAQUE 0x80
66 #define PVR2_CMD_MOD_OPAQUE 0x81
67 #define PVR2_CMD_POLY_TRANS 0x82
68 #define PVR2_CMD_MOD_TRANS 0x83
69 #define PVR2_CMD_POLY_PUNCHOUT 0x84
70 #define PVR2_CMD_VERTEX 0xE0
71 #define PVR2_CMD_VERTEX_LAST 0xF0
73 #define PVR2_POLY_TEXTURED 0x00000008
74 #define PVR2_POLY_SPECULAR 0x00000004
75 #define PVR2_POLY_SHADED 0x00000002
76 #define PVR2_POLY_UV_16BIT 0x00000001
78 #define PVR2_POLY_MODE_CLAMP_RGB 0x00200000
79 #define PVR2_POLY_MODE_ALPHA 0x00100000
80 #define PVR2_POLY_MODE_TEXALPHA 0x00080000
81 #define PVR2_POLY_MODE_FLIP_S 0x00040000
82 #define PVR2_POLY_MODE_FLIP_T 0x00020000
83 #define PVR2_POLY_MODE_CLAMP_S 0x00010000
84 #define PVR2_POLY_MODE_CLAMP_T 0x00008000
86 #define PVR2_TEX_FORMAT_ARGB1555 0x00000000
87 #define PVR2_TEX_FORMAT_RGB565 0x08000000
88 #define PVR2_TEX_FORMAT_ARGB4444 0x10000000
89 #define PVR2_TEX_FORMAT_YUV422 0x18000000
90 #define PVR2_TEX_FORMAT_BUMPMAP 0x20000000
91 #define PVR2_TEX_FORMAT_IDX4 0x28000000
92 #define PVR2_TEX_FORMAT_IDX8 0x30000000
94 #define PVR2_TEX_MIPMAP 0x80000000
95 #define PVR2_TEX_COMPRESSED 0x40000000
96 #define PVR2_TEX_FORMAT_MASK 0x38000000
97 #define PVR2_TEX_UNTWIDDLED 0x04000000
99 #define PVR2_TEX_ADDR(x) ( ((x)&0x01FFFFF)<<3 );
100 #define PVR2_TEX_IS_MIPMAPPED(x) ( (x) & PVR2_TEX_MIPMAP )
101 #define PVR2_TEX_IS_COMPRESSED(x) ( (x) & PVR2_TEX_COMPRESSED )
102 #define PVR2_TEX_IS_TWIDDLED(x) (((x) & PVR2_TEX_UNTWIDDLED) == 0)
104 /****************************** Frame Buffer *****************************/
106 /**
107 * Write to the interleaved memory address space (aka 64-bit address space).
108 */
109 void pvr2_vram64_write( sh4addr_t dest, char *src, uint32_t length );
111 /**
112 * Read from the interleaved memory address space (aka 64-bit address space)
113 */
114 void pvr2_vram64_read( char *dest, sh4addr_t src, uint32_t length );
116 /**
117 * Dump a portion of vram to a stream from the interleaved memory address
118 * space.
119 */
120 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f );
122 /**************************** Tile Accelerator ***************************/
123 /**
124 * Process the data in the supplied buffer as an array of TA command lists.
125 * Any excess bytes are held pending until a complete list is sent
126 */
127 void pvr2_ta_write( char *buf, uint32_t length );
130 /**
131 * (Re)initialize the tile accelerator in preparation for the next scene.
132 * Normally called immediately before commencing polygon transmission.
133 */
134 void pvr2_ta_init( void );
136 /********************************* Renderer ******************************/
138 /**
139 * Initialize the rendering pipeline.
140 * @return TRUE on success, FALSE on failure.
141 */
142 gboolean pvr2_render_init( void );
144 /**
145 * Invalidate any caching on the supplied SH4 address
146 */
147 gboolean pvr2_render_invalidate( sh4addr_t addr );
149 /**
150 * Render the current scene stored in PVR ram to the GL back buffer.
151 */
152 void pvr2_render_scene( void );
154 /**
155 * Display the scene rendered to the supplied address.
156 * @return TRUE if there was an available render that was displayed,
157 * otherwise FALSE (and no action was taken)
158 */
159 gboolean pvr2_render_display_frame( uint32_t address );
161 /****************************** Texture Cache ****************************/
163 /**
164 * Initialize the texture cache.
165 */
166 void texcache_init( void );
168 /**
169 * Initialize the GL side of the texture cache (texture ids and such).
170 */
171 void texcache_gl_init( void );
173 /**
174 * Flush all textures and delete. The cache will be non-functional until
175 * the next call to texcache_init(). This would typically be done if
176 * switching GL targets.
177 */
178 void texcache_shutdown( void );
180 /**
181 * Evict all textures contained in the page identified by a texture address.
182 */
183 void texcache_invalidate_page( uint32_t texture_addr );
185 /**
186 * Return a texture ID for the texture specified at the supplied address
187 * and given parameters (the same sequence of bytes could in theory have
188 * multiple interpretations). We use the texture address as the primary
189 * index, but allow for multiple instances at each address. The texture
190 * will be bound to the GL_TEXTURE_2D target before being returned.
191 *
192 * If the texture has already been bound, return the ID to which it was
193 * bound. Otherwise obtain an unused texture ID and set it up appropriately.
194 */
195 GLuint texcache_get_texture( uint32_t texture_addr, int width, int height,
196 int mode );
.