filename | src/sh4/sh4core.h |
changeset | 591:7b9612fd2395 |
prev | 589:045ba6eb6df1 |
next | 597:87cbdf62aa35 |
author | nkeynes |
date | Mon Jan 21 11:59:46 2008 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Fix MAC.L/MAC.W stack issues Fix various recovery-table issues |
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1 /**
2 * $Id$
3 *
4 * This file defines the internal functions exported/used by the SH4 core,
5 * except for disassembly functions defined in sh4dasm.h
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #ifndef sh4core_H
21 #define sh4core_H 1
23 #include <glib/gtypes.h>
24 #include <stdint.h>
25 #include <stdio.h>
26 #include "mem.h"
27 #include "sh4/sh4.h"
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
33 /* Breakpoint data structure */
34 extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
35 extern int sh4_breakpoint_count;
36 extern sh4ptr_t sh4_main_ram;
37 extern gboolean sh4_starting;
39 /**
40 * Cached direct pointer to the current instruction page. If AT is on, this
41 * is derived from the ITLB, otherwise this will be the entire memory region.
42 * This is actually a fairly useful optimization, as we can make a lot of
43 * assumptions about the "current page" that we can't make in general for
44 * arbitrary virtual addresses.
45 */
46 struct sh4_icache_struct {
47 sh4ptr_t page; // Page pointer (NULL if no page)
48 sh4vma_t page_vma; // virtual address of the page.
49 sh4addr_t page_ppa; // physical address of the page
50 uint32_t mask; // page mask
51 };
52 extern struct sh4_icache_struct sh4_icache;
54 /**
55 * Test if a given address is contained in the current icache entry
56 */
57 #define IS_IN_ICACHE(addr) (sh4_icache.page_vma == ((addr) & sh4_icache.mask))
58 /**
59 * Return a pointer for the given vma, under the assumption that it is
60 * actually contained in the current icache entry.
61 */
62 #define GET_ICACHE_PTR(addr) (sh4_icache.page + ((addr)-sh4_icache.page_vma))
63 /**
64 * Return the physical (external) address for the given vma, assuming that it is
65 * actually contained in the current icache entry.
66 */
67 #define GET_ICACHE_PHYS(addr) (sh4_icache.page_ppa + ((addr)-sh4_icache.page_vma))
69 /**
70 * Return the virtual (vma) address for the first address past the end of the
71 * cache entry. Assumes that there is in fact a current icache entry.
72 */
73 #define GET_ICACHE_END() (sh4_icache.page_vma + (~sh4_icache.mask) + 1)
75 /* SH4 module functions */
76 void sh4_init( void );
77 void sh4_reset( void );
78 void sh4_run( void );
79 void sh4_stop( void );
81 /* SH4 peripheral module functions */
82 void CPG_reset( void );
83 void DMAC_reset( void );
84 void DMAC_run_slice( uint32_t );
85 void DMAC_save_state( FILE * );
86 int DMAC_load_state( FILE * );
87 void INTC_reset( void );
88 void INTC_save_state( FILE *f );
89 int INTC_load_state( FILE *f );
90 void MMU_init( void );
91 void MMU_reset( void );
92 void MMU_save_state( FILE *f );
93 int MMU_load_state( FILE *f );
94 void MMU_ldtlb();
95 void SCIF_reset( void );
96 void SCIF_run_slice( uint32_t );
97 void SCIF_save_state( FILE *f );
98 int SCIF_load_state( FILE *f );
99 void SCIF_update_line_speed(void);
100 void TMU_reset( void );
101 void TMU_run_slice( uint32_t );
102 void TMU_save_state( FILE * );
103 int TMU_load_state( FILE * );
104 void TMU_update_clocks( void );
106 /* SH4 instruction support methods */
107 void sh4_sleep( void );
108 void sh4_fsca( uint32_t angle, float *fr );
109 void sh4_ftrv( float *fv, float *xmtrx );
110 uint32_t sh4_read_sr(void);
111 void sh4_write_sr(uint32_t val);
112 void signsat48(void);
114 /* SH4 Memory */
115 #define MMU_VMA_ERROR 0x8000000
116 /**
117 * Update the sh4_icache structure to contain the specified vma. If the vma
118 * cannot be resolved, an MMU exception is raised and the function returns
119 * FALSE. Otherwise, returns TRUE and updates sh4_icache accordingly.
120 * Note: If the vma resolves to a non-memory area, sh4_icache will be
121 * invalidated, but the function will still return TRUE.
122 * @return FALSE if an MMU exception was raised, otherwise TRUE.
123 */
124 gboolean mmu_update_icache( sh4vma_t addr );
126 /**
127 * Resolve a virtual address through the TLB for a read operation, returning
128 * the resultant P4 or external address. If the resolution fails, the
129 * appropriate MMU exception is raised and the value MMU_VMA_ERROR is returned.
130 * @return An external address (0x00000000-0x1FFFFFFF), a P4 address
131 * (0xE0000000 - 0xFFFFFFFF), or MMU_VMA_ERROR.
132 */
133 sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr );
134 sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr );
136 int64_t sh4_read_quad( sh4addr_t addr );
137 int32_t sh4_read_long( sh4addr_t addr );
138 int32_t sh4_read_word( sh4addr_t addr );
139 int32_t sh4_read_byte( sh4addr_t addr );
140 void sh4_write_quad( sh4addr_t addr, uint64_t val );
141 void sh4_write_long( sh4addr_t addr, uint32_t val );
142 void sh4_write_word( sh4addr_t addr, uint32_t val );
143 void sh4_write_byte( sh4addr_t addr, uint32_t val );
144 int32_t sh4_read_phys_word( sh4addr_t addr );
145 gboolean sh4_flush_store_queue( sh4addr_t addr );
147 /* SH4 Exceptions */
148 #define EXC_POWER_RESET 0x000 /* reset vector */
149 #define EXC_MANUAL_RESET 0x020 /* reset vector */
150 #define EXC_TLB_MISS_READ 0x040 /* TLB vector */
151 #define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */
152 #define EXC_INIT_PAGE_WRITE 0x080
153 #define EXC_TLB_PROT_READ 0x0A0
154 #define EXC_TLB_PROT_WRITE 0x0C0
155 #define EXC_DATA_ADDR_READ 0x0E0
156 #define EXC_DATA_ADDR_WRITE 0x100
157 #define EXC_TLB_MULTI_HIT 0x140
158 #define EXC_SLOT_ILLEGAL 0x1A0
159 #define EXC_ILLEGAL 0x180
160 #define EXC_TRAP 0x160
161 #define EXC_FPU_DISABLED 0x800
162 #define EXC_SLOT_FPU_DISABLED 0x820
164 #define EXV_EXCEPTION 0x100 /* General exception vector */
165 #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */
166 #define EXV_INTERRUPT 0x600 /* External interrupt vector */
168 gboolean sh4_raise_exception( int );
169 gboolean sh4_raise_reset( int );
170 gboolean sh4_raise_trap( int );
171 gboolean sh4_raise_slot_exception( int, int );
172 gboolean sh4_raise_tlb_exception( int );
173 void sh4_accept_interrupt( void );
175 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
176 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
177 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
178 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
179 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
180 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
181 #define ZEROEXT32(n) ((int64_t)((uint64_t)((uint32_t)(n))))
183 /* Status Register (SR) bits */
184 #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
185 #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
186 #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
187 #define SR_FD 0x00008000 /* FPU disable */
188 #define SR_M 0x00000200
189 #define SR_Q 0x00000100
190 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
191 #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
192 #define SR_T 0x00000001 /* True/false or carry/borrow */
193 #define SR_MASK 0x700083F3
194 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
195 #define SR_MDRB 0x60000000 /* MD+RB mask for convenience */
197 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
198 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
199 #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot)
201 #define FPSCR_FR 0x00200000 /* FPU register bank */
202 #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
203 #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
204 #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
205 #define FPSCR_CAUSE 0x0003F000
206 #define FPSCR_ENABLE 0x00000F80
207 #define FPSCR_FLAG 0x0000007C
208 #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
210 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
211 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
212 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
214 #define FR(x) sh4r.fr_bank[(x)^1]
215 #define DRF(x) ((double *)sh4r.fr_bank)[x]
216 #define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1]
217 #define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x]
218 #define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x]
219 #define DR(x) DRb((x>>1), (x&1))
220 #define FPULf *((float *)&sh4r.fpul)
221 #define FPULi (sh4r.fpul)
223 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
225 #ifdef __cplusplus
226 }
227 #endif
228 #endif
.