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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 511:e02fb1af6fff
prev502:c4ecae2b1b5e
next545:fdcdcd8b9fd1
author nkeynes
date Wed Nov 14 10:23:28 2007 +0000 (12 years ago)
permissions -rw-r--r--
last change Fix validation of render buffer count when loading save state
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     1 /**
     2  * $Id: pvr2.c,v 1.50 2007-11-14 10:23:28 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include <assert.h>
    21 #include "dream.h"
    22 #include "eventq.h"
    23 #include "display.h"
    24 #include "mem.h"
    25 #include "asic.h"
    26 #include "clock.h"
    27 #include "pvr2/pvr2.h"
    28 #include "sh4/sh4core.h"
    29 #define MMIO_IMPL
    30 #include "pvr2/pvr2mmio.h"
    32 unsigned char *video_base;
    34 #define MAX_RENDER_BUFFERS 4
    36 #define HPOS_PER_FRAME 0
    37 #define HPOS_PER_LINECOUNT 1
    39 static void pvr2_init( void );
    40 static void pvr2_reset( void );
    41 static uint32_t pvr2_run_slice( uint32_t );
    42 static void pvr2_save_state( FILE *f );
    43 static int pvr2_load_state( FILE *f );
    44 static void pvr2_update_raster_posn( uint32_t nanosecs );
    45 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
    46 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
    47 static render_buffer_t pvr2_next_render_buffer( );
    48 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
    49 uint32_t pvr2_get_sync_status();
    51 void pvr2_display_frame( void );
    53 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
    55 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    56 					pvr2_run_slice, NULL,
    57 					pvr2_save_state, pvr2_load_state };
    60 display_driver_t display_driver = NULL;
    62 struct pvr2_state {
    63     uint32_t frame_count;
    64     uint32_t line_count;
    65     uint32_t line_remainder;
    66     uint32_t cycles_run; /* Cycles already executed prior to main time slice */
    67     uint32_t irq_hpos_line;
    68     uint32_t irq_hpos_line_count;
    69     uint32_t irq_hpos_mode;
    70     uint32_t irq_hpos_time_ns; /* Time within the line */
    71     uint32_t irq_vpos1;
    72     uint32_t irq_vpos2;
    73     uint32_t odd_even_field; /* 1 = odd, 0 = even */
    74     gboolean palette_changed; /* TRUE if palette has changed since last render */
    75     gchar *save_next_render_filename;
    76     /* timing */
    77     uint32_t dot_clock;
    78     uint32_t total_lines;
    79     uint32_t line_size;
    80     uint32_t line_time_ns;
    81     uint32_t vsync_lines;
    82     uint32_t hsync_width_ns;
    83     uint32_t front_porch_ns;
    84     uint32_t back_porch_ns;
    85     uint32_t retrace_start_line;
    86     uint32_t retrace_end_line;
    87     gboolean interlaced;
    88 } pvr2_state;
    90 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
    91 static int render_buffer_count = 0;
    92 static render_buffer_t displayed_render_buffer = NULL;
    94 /**
    95  * Event handler for the hpos callback
    96  */
    97 static void pvr2_hpos_callback( int eventid ) {
    98     asic_event( eventid );
    99     pvr2_update_raster_posn(sh4r.slice_cycle);
   100     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
   101 	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
   102 	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   103 	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   104 	}
   105     }
   106     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
   107 				  pvr2_state.irq_hpos_time_ns );
   108 }
   110 /**
   111  * Event handler for the scanline callbacks. Fires the corresponding
   112  * ASIC event, and resets the timer for the next field.
   113  */
   114 static void pvr2_scanline_callback( int eventid ) {
   115     asic_event( eventid );
   116     pvr2_update_raster_posn(sh4r.slice_cycle);
   117     if( eventid == EVENT_SCANLINE1 ) {
   118 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
   119     } else {
   120 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
   121     }
   122 }
   124 static void pvr2_init( void )
   125 {
   126     int i;
   127     register_io_region( &mmio_region_PVR2 );
   128     register_io_region( &mmio_region_PVR2PAL );
   129     register_io_region( &mmio_region_PVR2TA );
   130     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
   131     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
   132     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
   133     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
   134     texcache_init();
   135     pvr2_reset();
   136     pvr2_ta_reset();
   137     pvr2_state.save_next_render_filename = NULL;
   138     for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
   139 	render_buffers[i] = NULL;
   140     }
   141     render_buffer_count = 0;
   142     displayed_render_buffer = NULL;
   143 }
   145 static void pvr2_reset( void )
   146 {
   147     int i;
   148     pvr2_state.line_count = 0;
   149     pvr2_state.line_remainder = 0;
   150     pvr2_state.cycles_run = 0;
   151     pvr2_state.irq_vpos1 = 0;
   152     pvr2_state.irq_vpos2 = 0;
   153     pvr2_state.dot_clock = PVR2_DOT_CLOCK;
   154     pvr2_state.back_porch_ns = 4000;
   155     pvr2_state.palette_changed = FALSE;
   156     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
   157     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
   158     mmio_region_PVR2_write( YUV_ADDR, 0 );
   159     mmio_region_PVR2_write( YUV_CFG, 0 );
   161     pvr2_ta_init();
   162     texcache_flush();
   163     if( display_driver ) {
   164 	display_driver->display_blank(0);
   165 	for( i=0; i<render_buffer_count; i++ ) {
   166 	    display_driver->destroy_render_buffer(render_buffers[i]);
   167 	    render_buffers[i] = NULL;
   168 	}
   169 	render_buffer_count = 0;
   170     }
   171 }
   173 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
   174 {
   175     struct frame_buffer fbuf;
   177     fbuf.width = buffer->width;
   178     fbuf.height = buffer->height;
   179     fbuf.rowstride = fbuf.width*3;
   180     fbuf.colour_format = COLFMT_BGR888;
   181     fbuf.inverted = buffer->inverted;
   182     fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
   184     display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
   185     write_png_to_stream( f, &fbuf );
   186     g_free( fbuf.data );
   188     fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   189     fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   190     fwrite( &buffer->address, sizeof(buffer->address), 1, f );
   191     fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
   192     fwrite( &buffer->flushed, sizeof(buffer->flushed), 1, f );
   194 }
   196 render_buffer_t pvr2_load_render_buffer( FILE *f )
   197 {
   198     frame_buffer_t frame = read_png_from_stream( f );
   199     if( frame == NULL ) {
   200 	return NULL;
   201     }
   203     render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
   204     assert( buffer != NULL );
   205     fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
   206     fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
   207     fread( &buffer->address, sizeof(buffer->address), 1, f );
   208     fread( &buffer->scale, sizeof(buffer->scale), 1, f );
   209     fread( &buffer->flushed, sizeof(buffer->flushed), 1, f );
   210     return buffer;
   211 }
   216 void pvr2_save_render_buffers( FILE *f )
   217 {
   218     int i;
   219     fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
   220     if( displayed_render_buffer != NULL ) {
   221 	i = 1;
   222 	fwrite( &i, sizeof(i), 1, f );
   223 	pvr2_save_render_buffer( f, displayed_render_buffer );
   224     } else {
   225 	i = 0;
   226 	fwrite( &i, sizeof(i), 1, f );
   227     }
   229     for( i=0; i<render_buffer_count; i++ ) {
   230 	if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
   231 	    pvr2_save_render_buffer( f, render_buffers[i] );
   232 	}
   233     }
   234 }
   236 gboolean pvr2_load_render_buffers( FILE *f )
   237 {
   238     uint32_t count;
   239     int i, has_frontbuffer;
   241     fread( &count, sizeof(count), 1, f );
   242     if( count > MAX_RENDER_BUFFERS ) {
   243 	return FALSE;
   244     }
   245     fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
   246     for( i=0; i<render_buffer_count; i++ ) {
   247 	display_driver->destroy_render_buffer(render_buffers[i]);
   248 	render_buffers[i] = NULL;
   249     }
   250     render_buffer_count = 0;
   252     if( has_frontbuffer ) {
   253 	displayed_render_buffer = pvr2_load_render_buffer(f);
   254 	display_driver->display_render_buffer( displayed_render_buffer );
   255 	count--;
   256     }
   258     for( i=0; i<count; i++ ) {
   259 	if( pvr2_load_render_buffer( f ) == NULL ) {
   260 	    return FALSE;
   261 	}
   262     }
   263     return TRUE;
   264 }
   267 static void pvr2_save_state( FILE *f )
   268 {
   269     pvr2_save_render_buffers( f );
   270     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
   271     pvr2_ta_save_state( f );
   272     pvr2_yuv_save_state( f );
   273 }
   275 static int pvr2_load_state( FILE *f )
   276 {
   277     if( !pvr2_load_render_buffers(f) )
   278 	return 1;
   279     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   280 	return 1;
   281     if( pvr2_ta_load_state(f) ) {
   282 	return 1;
   283     }
   284     return pvr2_yuv_load_state(f);
   285 }
   287 /**
   288  * Update the current raster position to the given number of nanoseconds,
   289  * relative to the last time slice. (ie the raster will be adjusted forward
   290  * by nanosecs - nanosecs_already_run_this_timeslice)
   291  */
   292 static void pvr2_update_raster_posn( uint32_t nanosecs )
   293 {
   294     uint32_t old_line_count = pvr2_state.line_count;
   295     if( pvr2_state.line_time_ns == 0 ) {
   296 	return; /* do nothing */
   297     }
   298     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
   299     pvr2_state.cycles_run = nanosecs;
   300     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
   301 	pvr2_state.line_count ++;
   302 	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
   303     }
   305     if( pvr2_state.line_count >= pvr2_state.total_lines ) {
   306 	pvr2_state.line_count -= pvr2_state.total_lines;
   307 	if( pvr2_state.interlaced ) {
   308 	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
   309 	}
   310     }
   311     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
   312 	(old_line_count < pvr2_state.retrace_end_line ||
   313 	 old_line_count > pvr2_state.line_count) ) {
   314 	pvr2_state.frame_count++;
   315 	pvr2_display_frame();
   316     }
   317 }
   319 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   320 {
   321     pvr2_update_raster_posn( nanosecs );
   322     pvr2_state.cycles_run = 0;
   323     return nanosecs;
   324 }
   326 int pvr2_get_frame_count() 
   327 {
   328     return pvr2_state.frame_count;
   329 }
   331 render_buffer_t pvr2_get_front_buffer()
   332 {
   333     return displayed_render_buffer;
   334 }
   336 gboolean pvr2_save_next_scene( const gchar *filename )
   337 {
   338     if( pvr2_state.save_next_render_filename != NULL ) {
   339 	g_free( pvr2_state.save_next_render_filename );
   340     } 
   341     pvr2_state.save_next_render_filename = g_strdup(filename);
   342     return TRUE;
   343 }
   347 /**
   348  * Display the next frame, copying the current contents of video ram to
   349  * the window. If the video configuration has changed, first recompute the
   350  * new frame size/depth.
   351  */
   352 void pvr2_display_frame( void )
   353 {
   354     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   355     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
   356     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   358     if( display_driver == NULL ) {
   359 	return; /* can't really do anything much */
   360     } else if( !bEnabled ) {
   361 	/* Output disabled == black */
   362 	display_driver->display_blank( 0 ); 
   363 	displayed_render_buffer = NULL;
   364     } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
   365 	/* Enabled but blanked - border colour */
   366 	uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
   367 	display_driver->display_blank( colour );
   368 	displayed_render_buffer = NULL;
   369     } else {
   370 	/* Real output - determine dimensions etc */
   371 	struct frame_buffer fbuf;
   372 	uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
   373 	int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
   374 	int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   376 	fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
   377 	fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
   378 	fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   379 	fbuf.size = vid_ppl << 2 * fbuf.height;
   380 	fbuf.rowstride = (vid_ppl + vid_stride) << 2;
   382 	/* Determine the field to display, and deinterlace if possible */
   383 	if( pvr2_state.interlaced ) {
   384 	    if( vid_ppl == vid_stride ) { /* Magic deinterlace */
   385 		fbuf.height = fbuf.height << 1;
   386 		fbuf.rowstride = vid_ppl << 2;
   387 		fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   388 	    } else { 
   389 		/* Just display the field as is, folks. This is slightly tricky -
   390 		 * we pick the field based on which frame is about to come through,
   391 		 * which may not be the same as the odd_even_field.
   392 		 */
   393 		gboolean oddfield = pvr2_state.odd_even_field;
   394 		if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
   395 		    oddfield = !oddfield;
   396 		}
   397 		if( oddfield ) {
   398 		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   399 		} else {
   400 		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
   401 		}
   402 	    }
   403 	} else {
   404 	    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   405 	}
   406 	fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
   407 	fbuf.inverted = FALSE;
   408 	fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
   410 	render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
   411 	if( rbuf == NULL ) {
   412 	    rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
   413 	}
   414 	displayed_render_buffer = rbuf;
   415 	if( rbuf != NULL ) {
   416 	    display_driver->display_render_buffer( rbuf );
   417 	}
   418     }
   419 }
   421 /**
   422  * This has to handle every single register individually as they all get masked 
   423  * off differently (and its easier to do it at write time)
   424  */
   425 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   426 {
   427     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   428         MMIO_WRITE( PVR2, reg, val );
   429         return;
   430     }
   432     switch(reg) {
   433     case PVRID:
   434     case PVRVER:
   435     case GUNPOS: /* Read only registers */
   436 	break;
   437     case PVRRESET:
   438 	val &= 0x00000007; /* Do stuff? */
   439 	MMIO_WRITE( PVR2, reg, val );
   440 	break;
   441     case RENDER_START: /* Don't really care what value */
   442 	if( pvr2_state.save_next_render_filename != NULL ) {
   443 	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
   444 		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
   445 	    }
   446 	    g_free( pvr2_state.save_next_render_filename );
   447 	    pvr2_state.save_next_render_filename = NULL;
   448 	}
   449 	render_buffer_t buffer = pvr2_next_render_buffer();
   450 	if( buffer != NULL ) {
   451 	    pvr2_render_scene( buffer );
   452 	}
   453 	asic_event( EVENT_PVR_RENDER_DONE );
   454 	break;
   455     case RENDER_POLYBASE:
   456     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   457     	break;
   458     case RENDER_TSPCFG:
   459     	MMIO_WRITE( PVR2, reg, val&0x00010101 );
   460     	break;
   461     case DISP_BORDER:
   462     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   463     	break;
   464     case DISP_MODE:
   465     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   466     	break;
   467     case RENDER_MODE:
   468     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   469     	break;
   470     case RENDER_SIZE:
   471     	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   472     	break;
   473     case DISP_ADDR1:
   474 	val &= 0x00FFFFFC;
   475 	MMIO_WRITE( PVR2, reg, val );
   476 	pvr2_update_raster_posn(sh4r.slice_cycle);
   477 	break;
   478     case DISP_ADDR2:
   479     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   480 	pvr2_update_raster_posn(sh4r.slice_cycle);
   481     	break;
   482     case DISP_SIZE:
   483     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   484     	break;
   485     case RENDER_ADDR1:
   486     case RENDER_ADDR2:
   487     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   488     	break;
   489     case RENDER_HCLIP:
   490 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   491 	break;
   492     case RENDER_VCLIP:
   493 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   494 	break;
   495     case DISP_HPOSIRQ:
   496 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   497 	pvr2_state.irq_hpos_line = val & 0x03FF;
   498 	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
   499 	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
   500 	switch( pvr2_state.irq_hpos_mode ) {
   501 	case 3: /* Reserved - treat as 0 */
   502 	case 0: /* Once per frame at specified line */
   503 	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
   504 	    break;
   505 	case 2: /* Once per line - as per-line-count */
   506 	    pvr2_state.irq_hpos_line = 1;
   507 	    pvr2_state.irq_hpos_mode = 1;
   508 	case 1: /* Once per N lines */
   509 	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
   510 	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
   511 		pvr2_state.irq_hpos_line_count;
   512 	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   513 		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   514 	    }
   515 	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
   516 	}
   517 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
   518 					  pvr2_state.irq_hpos_time_ns );
   519 	break;
   520     case DISP_VPOSIRQ:
   521 	val = val & 0x03FF03FF;
   522 	pvr2_state.irq_vpos1 = (val >> 16);
   523 	pvr2_state.irq_vpos2 = val & 0x03FF;
   524 	pvr2_update_raster_posn(sh4r.slice_cycle);
   525 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   526 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   527 	MMIO_WRITE( PVR2, reg, val );
   528 	break;
   529     case RENDER_NEARCLIP:
   530 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   531 	break;
   532     case RENDER_SHADOW:
   533 	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   534 	break;
   535     case RENDER_OBJCFG:
   536     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   537     	break;
   538     case RENDER_TSPCLIP:
   539     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   540     	break;
   541     case RENDER_FARCLIP:
   542 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   543 	break;
   544     case RENDER_BGPLANE:
   545     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   546     	break;
   547     case RENDER_ISPCFG:
   548     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   549     	break;
   550     case VRAM_CFG1:
   551 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   552 	break;
   553     case VRAM_CFG2:
   554 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   555 	break;
   556     case VRAM_CFG3:
   557 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   558 	break;
   559     case RENDER_FOGTBLCOL:
   560     case RENDER_FOGVRTCOL:
   561 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   562 	break;
   563     case RENDER_FOGCOEFF:
   564 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   565 	break;
   566     case RENDER_CLAMPHI:
   567     case RENDER_CLAMPLO:
   568 	MMIO_WRITE( PVR2, reg, val );
   569 	break;
   570     case RENDER_TEXSIZE:
   571 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   572 	break;
   573     case RENDER_PALETTE:
   574 	MMIO_WRITE( PVR2, reg, val&0x00000003 );
   575 	break;
   577 	/********** CRTC registers *************/
   578     case DISP_HBORDER:
   579     case DISP_VBORDER:
   580 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   581 	break;
   582     case DISP_TOTAL:
   583 	val = val & 0x03FF03FF;
   584 	MMIO_WRITE( PVR2, reg, val );
   585 	pvr2_update_raster_posn(sh4r.slice_cycle);
   586 	pvr2_state.total_lines = (val >> 16) + 1;
   587 	pvr2_state.line_size = (val & 0x03FF) + 1;
   588 	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
   589 	pvr2_state.retrace_end_line = 0x2A;
   590 	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
   591 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   592 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   593 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
   594 					  pvr2_state.irq_hpos_time_ns );
   595 	break;
   596     case DISP_SYNCCFG:
   597 	MMIO_WRITE( PVR2, reg, val&0x000003FF );
   598 	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
   599 	break;
   600     case DISP_SYNCTIME:
   601 	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
   602 	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
   603 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   604 	break;
   605     case DISP_CFG2:
   606 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   607 	break;
   608     case DISP_HPOS:
   609 	val = val & 0x03FF;
   610 	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
   611 	MMIO_WRITE( PVR2, reg, val );
   612 	break;
   613     case DISP_VPOS:
   614 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   615 	break;
   617 	/*********** Tile accelerator registers ***********/
   618     case TA_POLYPOS:
   619     case TA_LISTPOS:
   620 	/* Readonly registers */
   621 	break;
   622     case TA_TILEBASE:
   623     case TA_LISTEND:
   624     case TA_LISTBASE:
   625 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   626 	break;
   627     case RENDER_TILEBASE:
   628     case TA_POLYBASE:
   629     case TA_POLYEND:
   630 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   631 	break;
   632     case TA_TILESIZE:
   633 	MMIO_WRITE( PVR2, reg, val&0x000F003F );
   634 	break;
   635     case TA_TILECFG:
   636 	MMIO_WRITE( PVR2, reg, val&0x00133333 );
   637 	break;
   638     case TA_INIT:
   639 	if( val & 0x80000000 )
   640 	    pvr2_ta_init();
   641 	break;
   642     case TA_REINIT:
   643 	break;
   644 	/**************** Scaler registers? ****************/
   645     case RENDER_SCALER:
   646 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   647 	break;
   649     case YUV_ADDR:
   650 	val = val & 0x00FFFFF8;
   651 	MMIO_WRITE( PVR2, reg, val );
   652 	pvr2_yuv_init( val );
   653 	break;
   654     case YUV_CFG:
   655 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   656 	pvr2_yuv_set_config(val);
   657 	break;
   659 	/**************** Unknowns ***************/
   660     case PVRUNK1:
   661     	MMIO_WRITE( PVR2, reg, val&0x000007FF );
   662     	break;
   663     case PVRUNK2:
   664 	MMIO_WRITE( PVR2, reg, val&0x00000007 );
   665 	break;
   666     case PVRUNK3:
   667 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   668 	break;
   669     case PVRUNK5:
   670 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   671 	break;
   672     case PVRUNK6:
   673 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   674 	break;
   675     case PVRUNK7:
   676 	MMIO_WRITE( PVR2, reg, val&0x00000001 );
   677 	break;
   678     }
   679 }
   681 /**
   682  * Calculate the current read value of the syncstat register, using
   683  * the current SH4 clock time as an offset from the last timeslice.
   684  * The register reads (LSB to MSB) as:
   685  *     0..9  Current scan line
   686  *     10    Odd/even field (1 = odd, 0 = even)
   687  *     11    Display active (including border and overscan)
   688  *     12    Horizontal sync off
   689  *     13    Vertical sync off
   690  * Note this method is probably incorrect for anything other than straight
   691  * interlaced PAL/NTSC, and needs further testing. 
   692  */
   693 uint32_t pvr2_get_sync_status()
   694 {
   695     pvr2_update_raster_posn(sh4r.slice_cycle);
   696     uint32_t result = pvr2_state.line_count;
   698     if( pvr2_state.odd_even_field ) {
   699 	result |= 0x0400;
   700     }
   701     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
   702 	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
   703 	    result |= 0x1000; /* !HSYNC */
   704 	}
   705 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   706 	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
   707 		result |= 0x2800; /* Display active */
   708 	    } else {
   709 		result |= 0x2000; /* Front porch */
   710 	    }
   711 	}
   712     } else {
   713 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   714 	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
   715 		result |= 0x3800; /* Display active */
   716 	    } else {
   717 		result |= 0x3000;
   718 	    }
   719 	} else {
   720 	    result |= 0x1000; /* Back porch */
   721 	}
   722     }
   723     return result;
   724 }
   726 /**
   727  * Schedule a "scanline" event. This actually goes off at
   728  * 2 * line in even fields and 2 * line + 1 in odd fields.
   729  * Otherwise this behaves as per pvr2_schedule_line_event().
   730  * The raster position should be updated before calling this
   731  * method.
   732  * @param eventid Event to fire at the specified time
   733  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
   734  *  displays). 
   735  * @param hpos_ns Nanoseconds into the line at which to fire.
   736  */
   737 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
   738 {
   739     uint32_t field = pvr2_state.odd_even_field;
   740     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
   741 	field = !field;
   742     }
   743     if( hpos_ns > pvr2_state.line_time_ns ) {
   744 	hpos_ns = pvr2_state.line_time_ns;
   745     }
   747     line <<= 1;
   748     if( field ) {
   749 	line += 1;
   750     }
   752     if( line < pvr2_state.total_lines ) {
   753 	uint32_t lines;
   754 	uint32_t time;
   755 	if( line <= pvr2_state.line_count ) {
   756 	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
   757 	} else {
   758 	    lines = (line - pvr2_state.line_count);
   759 	}
   760 	if( lines <= minimum_lines ) {
   761 	    lines += pvr2_state.total_lines;
   762 	}
   763 	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
   764 	event_schedule( eventid, time );
   765     } else {
   766 	event_cancel( eventid );
   767     }
   768 }
   770 MMIO_REGION_READ_FN( PVR2, reg )
   771 {
   772     switch( reg ) {
   773         case DISP_SYNCSTAT:
   774             return pvr2_get_sync_status();
   775         default:
   776             return MMIO_READ( PVR2, reg );
   777     }
   778 }
   780 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
   781 {
   782     MMIO_WRITE( PVR2PAL, reg, val );
   783     pvr2_state.palette_changed = TRUE;
   784 }
   786 void pvr2_check_palette_changed()
   787 {
   788     if( pvr2_state.palette_changed ) {
   789 	texcache_invalidate_palette();
   790 	pvr2_state.palette_changed = FALSE;
   791     }
   792 }
   794 MMIO_REGION_READ_DEFFN( PVR2PAL );
   796 void pvr2_set_base_address( uint32_t base ) 
   797 {
   798     mmio_region_PVR2_write( DISP_ADDR1, base );
   799 }
   804 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   805 {
   806     return 0xFFFFFFFF;
   807 }
   809 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   810 {
   811     pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
   812 }
   814 /**
   815  * Find the render buffer corresponding to the requested output frame
   816  * (does not consider texture renders). 
   817  * @return the render_buffer if found, or null if no such buffer.
   818  *
   819  * Note: Currently does not consider "partial matches", ie partial
   820  * frame overlap - it probably needs to do this.
   821  */
   822 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
   823 {
   824     int i;
   825     for( i=0; i<render_buffer_count; i++ ) {
   826 	if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
   827 	    return render_buffers[i];
   828 	}
   829     }
   830     return NULL;
   831 }
   833 /**
   834  * Allocate a render buffer with the requested parameters.
   835  * The order of preference is:
   836  *   1. An existing buffer with the same address. (not flushed unless the new
   837  * size is smaller than the old one).
   838  *   2. An existing buffer with the same size chosen by LRU order. Old buffer
   839  *       is flushed to vram.
   840  *   3. A new buffer if one can be created.
   841  *   4. The current display buff
   842  * Note: The current display field(s) will never be overwritten except as a last
   843  * resort.
   844  */
   845 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
   846 {
   847     int i;
   848     render_buffer_t result = NULL;
   850     /* Check existing buffers for an available buffer */
   851     for( i=0; i<render_buffer_count; i++ ) {
   852 	if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
   853 	    /* needs to be the right dimensions */
   854 	    if( render_buffers[i]->address == render_addr ) {
   855 		if( displayed_render_buffer == render_buffers[i] ) {
   856 		    /* Same address, but we can't use it because the
   857 		     * display has it. Mark it as unaddressed for later.
   858 		     */
   859 		    render_buffers[i]->address = -1;
   860 		} else {
   861 		    /* perfect */
   862 		    result = render_buffers[i];
   863 		    break;
   864 		}
   865 	    } else if( render_buffers[i]->address == -1 && result == NULL && 
   866 		       displayed_render_buffer != render_buffers[i] ) {
   867 		result = render_buffers[i];
   868 	    }
   870 	} else if( render_buffers[i]->address == render_addr ) {
   871 	    /* right address, wrong size - if it's larger, flush it, otherwise 
   872 	     * nuke it quietly */
   873 	    if( render_buffers[i]->width * render_buffers[i]->height >
   874 		width*height ) {
   875 		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
   876 	    }
   877 	    render_buffers[i]->address = -1;
   878 	}
   879     }
   881     /* Nothing available - make one */
   882     if( result == NULL ) {
   883 	if( render_buffer_count == MAX_RENDER_BUFFERS ) {
   884 	    /* maximum buffers reached - need to throw one away */
   885 	    uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
   886 	    uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
   887 	    for( i=0; i<render_buffer_count; i++ ) {
   888 		if( render_buffers[i]->address != field1_addr &&
   889 		    render_buffers[i]->address != field2_addr &&
   890 		    render_buffers[i] != displayed_render_buffer ) {
   891 		    /* Never throw away the current "front buffer(s)" */
   892 		    result = render_buffers[i];
   893 		    if( !result->flushed ) {
   894 			pvr2_render_buffer_copy_to_sh4( result );
   895 		    }
   896 		    if( result->width != width || result->height != height ) {
   897 			display_driver->destroy_render_buffer(render_buffers[i]);
   898 			result = display_driver->create_render_buffer(width,height);
   899 			render_buffers[i] = result;
   900 		    }
   901 		    break;
   902 		}
   903 	    }
   904 	} else {
   905 	    result = display_driver->create_render_buffer(width,height);
   906 	    if( result != NULL ) { 
   907 		render_buffers[render_buffer_count++] = result;
   908 	    }
   909 	}
   910     }
   912     if( result != NULL ) {
   913 	result->address = render_addr;
   914     }
   915     return result;
   916 }
   918 /**
   919  * Allocate a render buffer based on the current rendering settings
   920  */
   921 render_buffer_t pvr2_next_render_buffer()
   922 {
   923     render_buffer_t result = NULL;
   924     uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
   925     uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
   926     uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
   927     uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
   929     if( render_addr & 0x01000000 ) { /* vram64 */
   930 	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
   931     } else { /* vram32 */
   932 	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
   933     }
   935     int width, height;
   936     int colour_format = pvr2_render_colour_format[render_mode&0x07];
   937     pvr2_render_getsize( &width, &height );
   939     result = pvr2_alloc_render_buffer( render_addr, width, height );
   940     /* Setup the buffer */
   941     if( result != NULL ) {
   942 	result->rowstride = render_stride;
   943 	result->colour_format = colour_format;
   944 	result->scale = render_scale;
   945 	result->size = width * height * colour_formats[colour_format].bpp;
   946 	result->flushed = FALSE;
   947 	result->inverted = TRUE; // render buffers are inverted normally
   948     }
   949     return result;
   950 }
   952 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
   953 {
   954     render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
   955     if( result != NULL ) {
   956 	int bpp = colour_formats[frame->colour_format].bpp;
   957 	result->rowstride = frame->rowstride;
   958 	result->colour_format = frame->colour_format;
   959 	result->scale = 0x400;
   960 	result->size = frame->width * frame->height * bpp;
   961 	result->flushed = TRUE;
   962 	result->inverted = frame->inverted;
   963 	display_driver->load_frame_buffer( frame, result );
   964     }
   965     return result;
   966 }
   969 /**
   970  * Invalidate any caching on the supplied address. Specifically, if it falls
   971  * within any of the render buffers, flush the buffer back to PVR2 ram.
   972  */
   973 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
   974 {
   975     int i;
   976     address = address & 0x1FFFFFFF;
   977     for( i=0; i<render_buffer_count; i++ ) {
   978 	uint32_t bufaddr = render_buffers[i]->address;
   979 	if( bufaddr != -1 && bufaddr <= address && 
   980 	    (bufaddr + render_buffers[i]->size) > address ) {
   981 	    if( !render_buffers[i]->flushed ) {
   982 		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
   983 		render_buffers[i]->flushed = TRUE;
   984 	    }
   985 	    if( isWrite ) {
   986 		render_buffers[i]->address = -1; /* Invalid */
   987 	    }
   988 	    return TRUE; /* should never have overlapping buffers */
   989 	}
   990     }
   991     return FALSE;
   992 }
.