lxdream.org :: lxdream/src/sh4/sh4core.c r561:533f6b478071

tree revision 562:e598411b640b lxdream-mmu

filename	src/sh4/sh4core.c
changeset	561:533f6b478071
prev	559:06714bc64271
next	569:a1c49e1e8776
author	nkeynes
date	Tue Jan 01 05:48:06 2008 +0000 (16 years ago)
branch	lxdream-mmu
permissions	-rw-r--r--
last change	Add configure and command-line parameters to perform IO tracing

view

     1 /**

     2  * $Id$

     3  *

     4  * SH4 emulation core, and parent module for all the SH4 peripheral

     5  * modules.

     6  *

     7  * Copyright (c) 2005 Nathan Keynes.

     8  *

     9  * This program is free software; you can redistribute it and/or modify

    10  * it under the terms of the GNU General Public License as published by

    11  * the Free Software Foundation; either version 2 of the License, or

    12  * (at your option) any later version.

    13  *

    14  * This program is distributed in the hope that it will be useful,

    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    17  * GNU General Public License for more details.

    18  */

    20 #define MODULE sh4_module

    21 #include <math.h>

    22 #include "dream.h"

    23 #include "dreamcast.h"

    24 #include "eventq.h"

    25 #include "mem.h"

    26 #include "clock.h"

    27 #include "syscall.h"

    28 #include "sh4/sh4core.h"

    29 #include "sh4/sh4mmio.h"

    30 #include "sh4/intc.h"

    32 #define SH4_CALLTRACE 1

    34 #define MAX_INT 0x7FFFFFFF

    35 #define MIN_INT 0x80000000

    36 #define MAX_INTF 2147483647.0

    37 #define MIN_INTF -2147483648.0

    39 /********************** SH4 Module Definition ****************************/

    41 uint16_t *sh4_icache = NULL;

    42 uint32_t sh4_icache_addr = 0;

    44 uint32_t sh4_run_slice( uint32_t nanosecs )

    45 {

    46     int i;

    47     sh4r.slice_cycle = 0;

    49     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {

    50 	if( sh4r.event_pending < nanosecs ) {

    51 	    sh4r.sh4_state = SH4_STATE_RUNNING;

    52 	    sh4r.slice_cycle = sh4r.event_pending;

    53 	}

    54     }

    56     if( sh4_breakpoint_count == 0 ) {

    57 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

    58 	    if( SH4_EVENT_PENDING() ) {

    59 		if( sh4r.event_types & PENDING_EVENT ) {

    60 		    event_execute();

    61 		}

    62 		/* Eventq execute may (quite likely) deliver an immediate IRQ */

    63 		if( sh4r.event_types & PENDING_IRQ ) {

    64 		    sh4_accept_interrupt();

    65 		}

    66 	    }

    67 	    if( !sh4_execute_instruction() ) {

    68 		break;

    69 	    }

    70 	}

    71     } else {

    72 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {

    73 	    if( SH4_EVENT_PENDING() ) {

    74 		if( sh4r.event_types & PENDING_EVENT ) {

    75 		    event_execute();

    76 		}

    77 		/* Eventq execute may (quite likely) deliver an immediate IRQ */

    78 		if( sh4r.event_types & PENDING_IRQ ) {

    79 		    sh4_accept_interrupt();

    80 		}

    81 	    }

    83 	    if( !sh4_execute_instruction() )

    84 		break;

    85 #ifdef ENABLE_DEBUG_MODE

    86 	    for( i=0; i<sh4_breakpoint_count; i++ ) {

    87 		if( sh4_breakpoints[i].address == sh4r.pc ) {

    88 		    break;

    89 		}

    90 	    }

    91 	    if( i != sh4_breakpoint_count ) {

    92 		dreamcast_stop();

    93 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )

    94 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );

    95 		break;

    96 	    }

    97 #endif

    98 	}

    99     }

   101     /* If we aborted early, but the cpu is still technically running,

   102      * we're doing a hard abort - cut the timeslice back to what we

   103      * actually executed

   104      */

   105     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {

   106 	nanosecs = sh4r.slice_cycle;

   107     }

   108     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {

   109 	TMU_run_slice( nanosecs );

   110 	SCIF_run_slice( nanosecs );

   111     }

   112     return nanosecs;

   113 }

   115 /********************** SH4 emulation core  ****************************/

   117 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)

   118 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)

   120 #if(SH4_CALLTRACE == 1)

   121 #define MAX_CALLSTACK 32

   122 static struct call_stack {

   123     sh4addr_t call_addr;

   124     sh4addr_t target_addr;

   125     sh4addr_t stack_pointer;

   126 } call_stack[MAX_CALLSTACK];

   128 static int call_stack_depth = 0;

   129 int sh4_call_trace_on = 0;

   131 static inline void trace_call( sh4addr_t source, sh4addr_t dest )

   132 {

   133     if( call_stack_depth < MAX_CALLSTACK ) {

   134 	call_stack[call_stack_depth].call_addr = source;

   135 	call_stack[call_stack_depth].target_addr = dest;

   136 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];

   137     }

   138     call_stack_depth++;

   139 }

   141 static inline void trace_return( sh4addr_t source, sh4addr_t dest )

   142 {

   143     if( call_stack_depth > 0 ) {

   144 	call_stack_depth--;

   145     }

   146 }

   148 void fprint_stack_trace( FILE *f )

   149 {

   150     int i = call_stack_depth -1;

   151     if( i >= MAX_CALLSTACK )

   152 	i = MAX_CALLSTACK - 1;

   153     for( ; i >= 0; i-- ) {

   154 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",

   155 		 (call_stack_depth - i), call_stack[i].call_addr,

   156 		 call_stack[i].target_addr, call_stack[i].stack_pointer );

   157     }

   158 }

   160 #define TRACE_CALL( source, dest ) trace_call(source, dest)

   161 #define TRACE_RETURN( source, dest ) trace_return(source, dest)

   162 #else

   163 #define TRACE_CALL( dest, rts )

   164 #define TRACE_RETURN( source, dest )

   165 #endif

   167 #define MEM_READ_BYTE( addr, val ) memtmp = sh4_read_byte(addr); if( memtmp >> 32 ) { return TRUE; } else { val = ((uint32_t)memtmp); }

   168 #define MEM_READ_WORD( addr, val ) memtmp = sh4_read_word(addr); if( memtmp >> 32 ) { return TRUE; } else { val = ((uint32_t)memtmp); }

   169 #define MEM_READ_LONG( addr, val ) memtmp = sh4_read_long(addr); if( memtmp >> 32 ) { return TRUE; } else { val = ((uint32_t)memtmp); }

   170 #define MEM_WRITE_BYTE( addr, val ) if( sh4_write_byte(addr, val) ) { return TRUE; }

   171 #define MEM_WRITE_WORD( addr, val ) if( sh4_write_word(addr, val) ) { return TRUE; }

   172 #define MEM_WRITE_LONG( addr, val ) if( sh4_write_long(addr, val) ) { return TRUE; }

   174 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)

   176 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );

   177 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );

   179 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )

   180 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

   181 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )

   182 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

   183 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )

   185 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }

   186 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }

   187 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)

   189 static void sh4_write_float( uint32_t addr, int reg )

   190 {

   191     if( IS_FPU_DOUBLESIZE() ) {

   192 	if( reg & 1 ) {

   193 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );

   194 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );

   195 	} else {

   196 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) );

   197 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );

   198 	}

   199     } else {

   200 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );

   201     }

   202 }

   204 static void sh4_read_float( uint32_t addr, int reg )

   205 {

   206     if( IS_FPU_DOUBLESIZE() ) {

   207 	if( reg & 1 ) {

   208 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);

   209 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);

   210 	} else {

   211 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);

   212 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);

   213 	}

   214     } else {

   215 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);

   216     }

   217 }

   219 gboolean sh4_execute_instruction( void )

   220 {

   221     uint32_t pc;

   222     unsigned short ir;

   223     uint32_t tmp;

   224     float ftmp;

   225     double dtmp;

   226     int64_t memtmp; // temporary holder for memory reads

   228 #define R0 sh4r.r[0]

   229     pc = sh4r.pc;

   230     if( pc > 0xFFFFFF00 ) {

   231 	/* SYSCALL Magic */

   232 	syscall_invoke( pc );

   233 	sh4r.in_delay_slot = 0;

   234 	pc = sh4r.pc = sh4r.pr;

   235 	sh4r.new_pc = sh4r.pc + 2;

   236     }

   237     CHECKRALIGN16(pc);

   239     /* Read instruction */

   240     uint32_t pageaddr = pc >> 12;

   241     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {

   242 	ir = sh4_icache[(pc&0xFFF)>>1];

   243     } else {

   244 	sh4_icache = (uint16_t *)mem_get_page(pc);

   245 	if( ((uintptr_t)sh4_icache) < MAX_IO_REGIONS ) {

   246 	    /* If someone's actually been so daft as to try to execute out of an IO

   247 	     * region, fallback on the full-blown memory read

   248 	     */

   249 	    sh4_icache = NULL;

   250 	    MEM_READ_WORD(pc, ir);

   251 	} else {

   252 	    sh4_icache_addr = pageaddr;

   253 	    ir = sh4_icache[(pc&0xFFF)>>1];

   254 	}

   255     }

   256         switch( (ir&0xF000) >> 12 ) {

   257             case 0x0:

   258                 switch( ir&0xF ) {

   259                     case 0x2:

   260                         switch( (ir&0x80) >> 7 ) {

   261                             case 0x0:

   262                                 switch( (ir&0x70) >> 4 ) {

   263                                     case 0x0:

   264                                         { /* STC SR, Rn */

   265                                         uint32_t Rn = ((ir>>8)&0xF);

   266                                         CHECKPRIV();

   267                                         sh4r.r[Rn] = sh4_read_sr();

   268                                         }

   269                                         break;

   270                                     case 0x1:

   271                                         { /* STC GBR, Rn */

   272                                         uint32_t Rn = ((ir>>8)&0xF);

   273                                         CHECKPRIV();

   274                                         sh4r.r[Rn] = sh4r.gbr;

   275                                         }

   276                                         break;

   277                                     case 0x2:

   278                                         { /* STC VBR, Rn */

   279                                         uint32_t Rn = ((ir>>8)&0xF);

   280                                         CHECKPRIV();

   281                                         sh4r.r[Rn] = sh4r.vbr;

   282                                         }

   283                                         break;

   284                                     case 0x3:

   285                                         { /* STC SSR, Rn */

   286                                         uint32_t Rn = ((ir>>8)&0xF);

   287                                         CHECKPRIV();

   288                                         sh4r.r[Rn] = sh4r.ssr;

   289                                         }

   290                                         break;

   291                                     case 0x4:

   292                                         { /* STC SPC, Rn */

   293                                         uint32_t Rn = ((ir>>8)&0xF);

   294                                         CHECKPRIV();

   295                                         sh4r.r[Rn] = sh4r.spc;

   296                                         }

   297                                         break;

   298                                     default:

   299                                         UNDEF();

   300                                         break;

   301                                 }

   302                                 break;

   303                             case 0x1:

   304                                 { /* STC Rm_BANK, Rn */

   305                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

   306                                 CHECKPRIV();

   307                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];

   308                                 }

   309                                 break;

   310                         }

   311                         break;

   312                     case 0x3:

   313                         switch( (ir&0xF0) >> 4 ) {

   314                             case 0x0:

   315                                 { /* BSRF Rn */

   316                                 uint32_t Rn = ((ir>>8)&0xF);

   317                                 CHECKSLOTILLEGAL();

   318                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );

   319                                 sh4r.in_delay_slot = 1;

   320                                 sh4r.pr = sh4r.pc + 4;

   321                                 sh4r.pc = sh4r.new_pc;

   322                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];

   323                                 TRACE_CALL( pc, sh4r.new_pc );

   324                                 return TRUE;

   325                                 }

   326                                 break;

   327                             case 0x2:

   328                                 { /* BRAF Rn */

   329                                 uint32_t Rn = ((ir>>8)&0xF);

   330                                 CHECKSLOTILLEGAL();

   331                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );

   332                                 sh4r.in_delay_slot = 1;

   333                                 sh4r.pc = sh4r.new_pc;

   334                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];

   335                                 return TRUE;

   336                                 }

   337                                 break;

   338                             case 0x8:

   339                                 { /* PREF @Rn */

   340                                 uint32_t Rn = ((ir>>8)&0xF);

   341                                 tmp = sh4r.r[Rn];

   342                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {

   343                            	 sh4_flush_store_queue(tmp);

   344                                 }

   345                                 }

   346                                 break;

   347                             case 0x9:

   348                                 { /* OCBI @Rn */

   349                                 uint32_t Rn = ((ir>>8)&0xF);

   350                                 }

   351                                 break;

   352                             case 0xA:

   353                                 { /* OCBP @Rn */

   354                                 uint32_t Rn = ((ir>>8)&0xF);

   355                                 }

   356                                 break;

   357                             case 0xB:

   358                                 { /* OCBWB @Rn */

   359                                 uint32_t Rn = ((ir>>8)&0xF);

   360                                 }

   361                                 break;

   362                             case 0xC:

   363                                 { /* MOVCA.L R0, @Rn */

   364                                 uint32_t Rn = ((ir>>8)&0xF);

   365                                 tmp = sh4r.r[Rn];

   366                                 CHECKWALIGN32(tmp);

   367                                 MEM_WRITE_LONG( tmp, R0 );

   368                                 }

   369                                 break;

   370                             default:

   371                                 UNDEF();

   372                                 break;

   373                         }

   374                         break;

   375                     case 0x4:

   376                         { /* MOV.B Rm, @(R0, Rn) */

   377                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   378                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   379                         }

   380                         break;

   381                     case 0x5:

   382                         { /* MOV.W Rm, @(R0, Rn) */

   383                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   384                         CHECKWALIGN16( R0 + sh4r.r[Rn] );

   385                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   386                         }

   387                         break;

   388                     case 0x6:

   389                         { /* MOV.L Rm, @(R0, Rn) */

   390                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   391                         CHECKWALIGN32( R0 + sh4r.r[Rn] );

   392                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );

   393                         }

   394                         break;

   395                     case 0x7:

   396                         { /* MUL.L Rm, Rn */

   397                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   398                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   399                                                (sh4r.r[Rm] * sh4r.r[Rn]);

   400                         }

   401                         break;

   402                     case 0x8:

   403                         switch( (ir&0xFF0) >> 4 ) {

   404                             case 0x0:

   405                                 { /* CLRT */

   406                                 sh4r.t = 0;

   407                                 }

   408                                 break;

   409                             case 0x1:

   410                                 { /* SETT */

   411                                 sh4r.t = 1;

   412                                 }

   413                                 break;

   414                             case 0x2:

   415                                 { /* CLRMAC */

   416                                 sh4r.mac = 0;

   417                                 }

   418                                 break;

   419                             case 0x3:

   420                                 { /* LDTLB */

   421                                 MMU_ldtlb();

   422                                 }

   423                                 break;

   424                             case 0x4:

   425                                 { /* CLRS */

   426                                 sh4r.s = 0;

   427                                 }

   428                                 break;

   429                             case 0x5:

   430                                 { /* SETS */

   431                                 sh4r.s = 1;

   432                                 }

   433                                 break;

   434                             default:

   435                                 UNDEF();

   436                                 break;

   437                         }

   438                         break;

   439                     case 0x9:

   440                         switch( (ir&0xF0) >> 4 ) {

   441                             case 0x0:

   442                                 { /* NOP */

   443                                 /* NOP */

   444                                 }

   445                                 break;

   446                             case 0x1:

   447                                 { /* DIV0U */

   448                                 sh4r.m = sh4r.q = sh4r.t = 0;

   449                                 }

   450                                 break;

   451                             case 0x2:

   452                                 { /* MOVT Rn */

   453                                 uint32_t Rn = ((ir>>8)&0xF);

   454                                 sh4r.r[Rn] = sh4r.t;

   455                                 }

   456                                 break;

   457                             default:

   458                                 UNDEF();

   459                                 break;

   460                         }

   461                         break;

   462                     case 0xA:

   463                         switch( (ir&0xF0) >> 4 ) {

   464                             case 0x0:

   465                                 { /* STS MACH, Rn */

   466                                 uint32_t Rn = ((ir>>8)&0xF);

   467                                 sh4r.r[Rn] = (sh4r.mac>>32);

   468                                 }

   469                                 break;

   470                             case 0x1:

   471                                 { /* STS MACL, Rn */

   472                                 uint32_t Rn = ((ir>>8)&0xF);

   473                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;

   474                                 }

   475                                 break;

   476                             case 0x2:

   477                                 { /* STS PR, Rn */

   478                                 uint32_t Rn = ((ir>>8)&0xF);

   479                                 sh4r.r[Rn] = sh4r.pr;

   480                                 }

   481                                 break;

   482                             case 0x3:

   483                                 { /* STC SGR, Rn */

   484                                 uint32_t Rn = ((ir>>8)&0xF);

   485                                 CHECKPRIV();

   486                                 sh4r.r[Rn] = sh4r.sgr;

   487                                 }

   488                                 break;

   489                             case 0x5:

   490                                 { /* STS FPUL, Rn */

   491                                 uint32_t Rn = ((ir>>8)&0xF);

   492                                 sh4r.r[Rn] = sh4r.fpul;

   493                                 }

   494                                 break;

   495                             case 0x6:

   496                                 { /* STS FPSCR, Rn */

   497                                 uint32_t Rn = ((ir>>8)&0xF);

   498                                 sh4r.r[Rn] = sh4r.fpscr;

   499                                 }

   500                                 break;

   501                             case 0xF:

   502                                 { /* STC DBR, Rn */

   503                                 uint32_t Rn = ((ir>>8)&0xF);

   504                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;

   505                                 }

   506                                 break;

   507                             default:

   508                                 UNDEF();

   509                                 break;

   510                         }

   511                         break;

   512                     case 0xB:

   513                         switch( (ir&0xFF0) >> 4 ) {

   514                             case 0x0:

   515                                 { /* RTS */

   516                                 CHECKSLOTILLEGAL();

   517                                 CHECKDEST( sh4r.pr );

   518                                 sh4r.in_delay_slot = 1;

   519                                 sh4r.pc = sh4r.new_pc;

   520                                 sh4r.new_pc = sh4r.pr;

   521                                 TRACE_RETURN( pc, sh4r.new_pc );

   522                                 return TRUE;

   523                                 }

   524                                 break;

   525                             case 0x1:

   526                                 { /* SLEEP */

   527                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {

   528                             	sh4r.sh4_state = SH4_STATE_STANDBY;

   529                                 } else {

   530                             	sh4r.sh4_state = SH4_STATE_SLEEP;

   531                                 }

   532                                 return FALSE; /* Halt CPU */

   533                                 }

   534                                 break;

   535                             case 0x2:

   536                                 { /* RTE */

   537                                 CHECKPRIV();

   538                                 CHECKDEST( sh4r.spc );

   539                                 CHECKSLOTILLEGAL();

   540                                 sh4r.in_delay_slot = 1;

   541                                 sh4r.pc = sh4r.new_pc;

   542                                 sh4r.new_pc = sh4r.spc;

   543                                 sh4_write_sr( sh4r.ssr );

   544                                 return TRUE;

   545                                 }

   546                                 break;

   547                             default:

   548                                 UNDEF();

   549                                 break;

   550                         }

   551                         break;

   552                     case 0xC:

   553                         { /* MOV.B @(R0, Rm), Rn */

   554                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   555                         MEM_READ_BYTE( R0 + sh4r.r[Rm], sh4r.r[Rn] );

   556                         }

   557                         break;

   558                     case 0xD:

   559                         { /* MOV.W @(R0, Rm), Rn */

   560                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   561                         CHECKRALIGN16( R0 + sh4r.r[Rm] );

   562                            MEM_READ_WORD( R0 + sh4r.r[Rm], sh4r.r[Rn] );

   563                         }

   564                         break;

   565                     case 0xE:

   566                         { /* MOV.L @(R0, Rm), Rn */

   567                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   568                         CHECKRALIGN32( R0 + sh4r.r[Rm] );

   569                            MEM_READ_LONG( R0 + sh4r.r[Rm], sh4r.r[Rn] );

   570                         }

   571                         break;

   572                     case 0xF:

   573                         { /* MAC.L @Rm+, @Rn+ */

   574                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   575                         CHECKRALIGN32( sh4r.r[Rm] );

   576                         CHECKRALIGN32( sh4r.r[Rn] );

   577                         MEM_READ_LONG(sh4r.r[Rn], tmp);

   578                         int64_t tmpl = SIGNEXT32(tmp);

   579                         sh4r.r[Rn] += 4;

   580                         MEM_READ_LONG(sh4r.r[Rm], tmp);

   581                         tmpl = tmpl * SIGNEXT32(tmp) + sh4r.mac;

   582                         sh4r.r[Rm] += 4;

   583                         if( sh4r.s ) {

   584                             /* 48-bit Saturation. Yuch */

   585                             if( tmpl < (int64_t)0xFFFF800000000000LL )

   586                                 tmpl = 0xFFFF800000000000LL;

   587                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )

   588                                 tmpl = 0x00007FFFFFFFFFFFLL;

   589                         }

   590                         sh4r.mac = tmpl;

   591                         }

   592                         break;

   593                     default:

   594                         UNDEF();

   595                         break;

   596                 }

   597                 break;

   598             case 0x1:

   599                 { /* MOV.L Rm, @(disp, Rn) */

   600                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

   601                 tmp = sh4r.r[Rn] + disp;

   602                 CHECKWALIGN32( tmp );

   603                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );

   604                 }

   605                 break;

   606             case 0x2:

   607                 switch( ir&0xF ) {

   608                     case 0x0:

   609                         { /* MOV.B Rm, @Rn */

   610                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   611                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );

   612                         }

   613                         break;

   614                     case 0x1:

   615                         { /* MOV.W Rm, @Rn */

   616                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   617                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );

   618                         }

   619                         break;

   620                     case 0x2:

   621                         { /* MOV.L Rm, @Rn */

   622                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   623                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );

   624                         }

   625                         break;

   626                     case 0x4:

   627                         { /* MOV.B Rm, @-Rn */

   628                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   629                         sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );

   630                         }

   631                         break;

   632                     case 0x5:

   633                         { /* MOV.W Rm, @-Rn */

   634                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   635                         sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );

   636                         }

   637                         break;

   638                     case 0x6:

   639                         { /* MOV.L Rm, @-Rn */

   640                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   641                         sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );

   642                         }

   643                         break;

   644                     case 0x7:

   645                         { /* DIV0S Rm, Rn */

   646                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   647                         sh4r.q = sh4r.r[Rn]>>31;

   648                         sh4r.m = sh4r.r[Rm]>>31;

   649                         sh4r.t = sh4r.q ^ sh4r.m;

   650                         }

   651                         break;

   652                     case 0x8:

   653                         { /* TST Rm, Rn */

   654                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   655                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);

   656                         }

   657                         break;

   658                     case 0x9:

   659                         { /* AND Rm, Rn */

   660                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   661                         sh4r.r[Rn] &= sh4r.r[Rm];

   662                         }

   663                         break;

   664                     case 0xA:

   665                         { /* XOR Rm, Rn */

   666                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   667                         sh4r.r[Rn] ^= sh4r.r[Rm];

   668                         }

   669                         break;

   670                     case 0xB:

   671                         { /* OR Rm, Rn */

   672                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   673                         sh4r.r[Rn] |= sh4r.r[Rm];

   674                         }

   675                         break;

   676                     case 0xC:

   677                         { /* CMP/STR Rm, Rn */

   678                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   679                         /* set T = 1 if any byte in RM & RN is the same */

   680                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];

   681                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||

   682                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;

   683                         }

   684                         break;

   685                     case 0xD:

   686                         { /* XTRCT Rm, Rn */

   687                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   688                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);

   689                         }

   690                         break;

   691                     case 0xE:

   692                         { /* MULU.W Rm, Rn */

   693                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   694                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   695                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));

   696                         }

   697                         break;

   698                     case 0xF:

   699                         { /* MULS.W Rm, Rn */

   700                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   701                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |

   702                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));

   703                         }

   704                         break;

   705                     default:

   706                         UNDEF();

   707                         break;

   708                 }

   709                 break;

   710             case 0x3:

   711                 switch( ir&0xF ) {

   712                     case 0x0:

   713                         { /* CMP/EQ Rm, Rn */

   714                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   715                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );

   716                         }

   717                         break;

   718                     case 0x2:

   719                         { /* CMP/HS Rm, Rn */

   720                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   721                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );

   722                         }

   723                         break;

   724                     case 0x3:

   725                         { /* CMP/GE Rm, Rn */

   726                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   727                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );

   728                         }

   729                         break;

   730                     case 0x4:

   731                         { /* DIV1 Rm, Rn */

   732                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   733                         /* This is derived from the sh4 manual with some simplifications */

   734                         uint32_t tmp0, tmp1, tmp2, dir;

   736                         dir = sh4r.q ^ sh4r.m;

   737                         sh4r.q = (sh4r.r[Rn] >> 31);

   738                         tmp2 = sh4r.r[Rm];

   739                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;

   740                         tmp0 = sh4r.r[Rn];

   741                         if( dir ) {

   742                              sh4r.r[Rn] += tmp2;

   743                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );

   744                         } else {

   745                              sh4r.r[Rn] -= tmp2;

   746                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );

   747                         }

   748                         sh4r.q ^= sh4r.m ^ tmp1;

   749                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );

   750                         }

   751                         break;

   752                     case 0x5:

   753                         { /* DMULU.L Rm, Rn */

   754                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   755                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);

   756                         }

   757                         break;

   758                     case 0x6:

   759                         { /* CMP/HI Rm, Rn */

   760                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   761                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );

   762                         }

   763                         break;

   764                     case 0x7:

   765                         { /* CMP/GT Rm, Rn */

   766                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   767                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );

   768                         }

   769                         break;

   770                     case 0x8:

   771                         { /* SUB Rm, Rn */

   772                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   773                         sh4r.r[Rn] -= sh4r.r[Rm];

   774                         }

   775                         break;

   776                     case 0xA:

   777                         { /* SUBC Rm, Rn */

   778                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   779                         tmp = sh4r.r[Rn];

   780                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;

   781                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));

   782                         }

   783                         break;

   784                     case 0xB:

   785                         UNIMP(ir); /* SUBV Rm, Rn */

   786                         break;

   787                     case 0xC:

   788                         { /* ADD Rm, Rn */

   789                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   790                         sh4r.r[Rn] += sh4r.r[Rm];

   791                         }

   792                         break;

   793                     case 0xD:

   794                         { /* DMULS.L Rm, Rn */

   795                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   796                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);

   797                         }

   798                         break;

   799                     case 0xE:

   800                         { /* ADDC Rm, Rn */

   801                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   802                         tmp = sh4r.r[Rn];

   803                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;

   804                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );

   805                         }

   806                         break;

   807                     case 0xF:

   808                         { /* ADDV Rm, Rn */

   809                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

   810                         tmp = sh4r.r[Rn] + sh4r.r[Rm];

   811                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );

   812                         sh4r.r[Rn] = tmp;

   813                         }

   814                         break;

   815                     default:

   816                         UNDEF();

   817                         break;

   818                 }

   819                 break;

   820             case 0x4:

   821                 switch( ir&0xF ) {

   822                     case 0x0:

   823                         switch( (ir&0xF0) >> 4 ) {

   824                             case 0x0:

   825                                 { /* SHLL Rn */

   826                                 uint32_t Rn = ((ir>>8)&0xF);

   827                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;

   828                                 }

   829                                 break;

   830                             case 0x1:

   831                                 { /* DT Rn */

   832                                 uint32_t Rn = ((ir>>8)&0xF);

   833                                 sh4r.r[Rn] --;

   834                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );

   835                                 }

   836                                 break;

   837                             case 0x2:

   838                                 { /* SHAL Rn */

   839                                 uint32_t Rn = ((ir>>8)&0xF);

   840                                 sh4r.t = sh4r.r[Rn] >> 31;

   841                                 sh4r.r[Rn] <<= 1;

   842                                 }

   843                                 break;

   844                             default:

   845                                 UNDEF();

   846                                 break;

   847                         }

   848                         break;

   849                     case 0x1:

   850                         switch( (ir&0xF0) >> 4 ) {

   851                             case 0x0:

   852                                 { /* SHLR Rn */

   853                                 uint32_t Rn = ((ir>>8)&0xF);

   854                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;

   855                                 }

   856                                 break;

   857                             case 0x1:

   858                                 { /* CMP/PZ Rn */

   859                                 uint32_t Rn = ((ir>>8)&0xF);

   860                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );

   861                                 }

   862                                 break;

   863                             case 0x2:

   864                                 { /* SHAR Rn */

   865                                 uint32_t Rn = ((ir>>8)&0xF);

   866                                 sh4r.t = sh4r.r[Rn] & 0x00000001;

   867                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;

   868                                 }

   869                                 break;

   870                             default:

   871                                 UNDEF();

   872                                 break;

   873                         }

   874                         break;

   875                     case 0x2:

   876                         switch( (ir&0xF0) >> 4 ) {

   877                             case 0x0:

   878                                 { /* STS.L MACH, @-Rn */

   879                                 uint32_t Rn = ((ir>>8)&0xF);

   880                                 sh4r.r[Rn] -= 4;

   881                                 CHECKWALIGN32( sh4r.r[Rn] );

   882                                 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );

   883                                 }

   884                                 break;

   885                             case 0x1:

   886                                 { /* STS.L MACL, @-Rn */

   887                                 uint32_t Rn = ((ir>>8)&0xF);

   888                                 sh4r.r[Rn] -= 4;

   889                                 CHECKWALIGN32( sh4r.r[Rn] );

   890                                 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );

   891                                 }

   892                                 break;

   893                             case 0x2:

   894                                 { /* STS.L PR, @-Rn */

   895                                 uint32_t Rn = ((ir>>8)&0xF);

   896                                 sh4r.r[Rn] -= 4;

   897                                 CHECKWALIGN32( sh4r.r[Rn] );

   898                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );

   899                                 }

   900                                 break;

   901                             case 0x3:

   902                                 { /* STC.L SGR, @-Rn */

   903                                 uint32_t Rn = ((ir>>8)&0xF);

   904                                 CHECKPRIV();

   905                                 sh4r.r[Rn] -= 4;

   906                                 CHECKWALIGN32( sh4r.r[Rn] );

   907                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );

   908                                 }

   909                                 break;

   910                             case 0x5:

   911                                 { /* STS.L FPUL, @-Rn */

   912                                 uint32_t Rn = ((ir>>8)&0xF);

   913                                 sh4r.r[Rn] -= 4;

   914                                 CHECKWALIGN32( sh4r.r[Rn] );

   915                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );

   916                                 }

   917                                 break;

   918                             case 0x6:

   919                                 { /* STS.L FPSCR, @-Rn */

   920                                 uint32_t Rn = ((ir>>8)&0xF);

   921                                 sh4r.r[Rn] -= 4;

   922                                 CHECKWALIGN32( sh4r.r[Rn] );

   923                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );

   924                                 }

   925                                 break;

   926                             case 0xF:

   927                                 { /* STC.L DBR, @-Rn */

   928                                 uint32_t Rn = ((ir>>8)&0xF);

   929                                 CHECKPRIV();

   930                                 sh4r.r[Rn] -= 4;

   931                                 CHECKWALIGN32( sh4r.r[Rn] );

   932                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );

   933                                 }

   934                                 break;

   935                             default:

   936                                 UNDEF();

   937                                 break;

   938                         }

   939                         break;

   940                     case 0x3:

   941                         switch( (ir&0x80) >> 7 ) {

   942                             case 0x0:

   943                                 switch( (ir&0x70) >> 4 ) {

   944                                     case 0x0:

   945                                         { /* STC.L SR, @-Rn */

   946                                         uint32_t Rn = ((ir>>8)&0xF);

   947                                         CHECKPRIV();

   948                                         sh4r.r[Rn] -= 4;

   949                                         CHECKWALIGN32( sh4r.r[Rn] );

   950                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );

   951                                         }

   952                                         break;

   953                                     case 0x1:

   954                                         { /* STC.L GBR, @-Rn */

   955                                         uint32_t Rn = ((ir>>8)&0xF);

   956                                         sh4r.r[Rn] -= 4;

   957                                         CHECKWALIGN32( sh4r.r[Rn] );

   958                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );

   959                                         }

   960                                         break;

   961                                     case 0x2:

   962                                         { /* STC.L VBR, @-Rn */

   963                                         uint32_t Rn = ((ir>>8)&0xF);

   964                                         CHECKPRIV();

   965                                         sh4r.r[Rn] -= 4;

   966                                         CHECKWALIGN32( sh4r.r[Rn] );

   967                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );

   968                                         }

   969                                         break;

   970                                     case 0x3:

   971                                         { /* STC.L SSR, @-Rn */

   972                                         uint32_t Rn = ((ir>>8)&0xF);

   973                                         CHECKPRIV();

   974                                         sh4r.r[Rn] -= 4;

   975                                         CHECKWALIGN32( sh4r.r[Rn] );

   976                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );

   977                                         }

   978                                         break;

   979                                     case 0x4:

   980                                         { /* STC.L SPC, @-Rn */

   981                                         uint32_t Rn = ((ir>>8)&0xF);

   982                                         CHECKPRIV();

   983                                         sh4r.r[Rn] -= 4;

   984                                         CHECKWALIGN32( sh4r.r[Rn] );

   985                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );

   986                                         }

   987                                         break;

   988                                     default:

   989                                         UNDEF();

   990                                         break;

   991                                 }

   992                                 break;

   993                             case 0x1:

   994                                 { /* STC.L Rm_BANK, @-Rn */

   995                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);

   996                                 CHECKPRIV();

   997                                 sh4r.r[Rn] -= 4;

   998                                 CHECKWALIGN32( sh4r.r[Rn] );

   999                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );

  1000                                 }

  1001                                 break;

  1002                         }

  1003                         break;

  1004                     case 0x4:

  1005                         switch( (ir&0xF0) >> 4 ) {

  1006                             case 0x0:

  1007                                 { /* ROTL Rn */

  1008                                 uint32_t Rn = ((ir>>8)&0xF);

  1009                                 sh4r.t = sh4r.r[Rn] >> 31;

  1010                                 sh4r.r[Rn] <<= 1;

  1011                                 sh4r.r[Rn] |= sh4r.t;

  1012                                 }

  1013                                 break;

  1014                             case 0x2:

  1015                                 { /* ROTCL Rn */

  1016                                 uint32_t Rn = ((ir>>8)&0xF);

  1017                                 tmp = sh4r.r[Rn] >> 31;

  1018                                 sh4r.r[Rn] <<= 1;

  1019                                 sh4r.r[Rn] |= sh4r.t;

  1020                                 sh4r.t = tmp;

  1021                                 }

  1022                                 break;

  1023                             default:

  1024                                 UNDEF();

  1025                                 break;

  1026                         }

  1027                         break;

  1028                     case 0x5:

  1029                         switch( (ir&0xF0) >> 4 ) {

  1030                             case 0x0:

  1031                                 { /* ROTR Rn */

  1032                                 uint32_t Rn = ((ir>>8)&0xF);

  1033                                 sh4r.t = sh4r.r[Rn] & 0x00000001;

  1034                                 sh4r.r[Rn] >>= 1;

  1035                                 sh4r.r[Rn] |= (sh4r.t << 31);

  1036                                 }

  1037                                 break;

  1038                             case 0x1:

  1039                                 { /* CMP/PL Rn */

  1040                                 uint32_t Rn = ((ir>>8)&0xF);

  1041                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );

  1042                                 }

  1043                                 break;

  1044                             case 0x2:

  1045                                 { /* ROTCR Rn */

  1046                                 uint32_t Rn = ((ir>>8)&0xF);

  1047                                 tmp = sh4r.r[Rn] & 0x00000001;

  1048                                 sh4r.r[Rn] >>= 1;

  1049                                 sh4r.r[Rn] |= (sh4r.t << 31 );

  1050                                 sh4r.t = tmp;

  1051                                 }

  1052                                 break;

  1053                             default:

  1054                                 UNDEF();

  1055                                 break;

  1056                         }

  1057                         break;

  1058                     case 0x6:

  1059                         switch( (ir&0xF0) >> 4 ) {

  1060                             case 0x0:

  1061                                 { /* LDS.L @Rm+, MACH */

  1062                                 uint32_t Rm = ((ir>>8)&0xF);

  1063                                 CHECKRALIGN32( sh4r.r[Rm] );

  1064                                 MEM_READ_LONG(sh4r.r[Rm], tmp);

  1065                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

  1066                             	(((uint64_t)tmp)<<32);

  1067                                 sh4r.r[Rm] += 4;

  1068                                 }

  1069                                 break;

  1070                             case 0x1:

  1071                                 { /* LDS.L @Rm+, MACL */

  1072                                 uint32_t Rm = ((ir>>8)&0xF);

  1073                                 CHECKRALIGN32( sh4r.r[Rm] );

  1074                                 MEM_READ_LONG(sh4r.r[Rm], tmp);

  1075                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1076                                            (uint64_t)((uint32_t)tmp);

  1077                                 sh4r.r[Rm] += 4;

  1078                                 }

  1079                                 break;

  1080                             case 0x2:

  1081                                 { /* LDS.L @Rm+, PR */

  1082                                 uint32_t Rm = ((ir>>8)&0xF);

  1083                                 CHECKRALIGN32( sh4r.r[Rm] );

  1084                                 MEM_READ_LONG( sh4r.r[Rm], sh4r.pr );

  1085                                 sh4r.r[Rm] += 4;

  1086                                 }

  1087                                 break;

  1088                             case 0x3:

  1089                                 { /* LDC.L @Rm+, SGR */

  1090                                 uint32_t Rm = ((ir>>8)&0xF);

  1091                                 CHECKPRIV();

  1092                                 CHECKRALIGN32( sh4r.r[Rm] );

  1093                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.sgr);

  1094                                 sh4r.r[Rm] +=4;

  1095                                 }

  1096                                 break;

  1097                             case 0x5:

  1098                                 { /* LDS.L @Rm+, FPUL */

  1099                                 uint32_t Rm = ((ir>>8)&0xF);

  1100                                 CHECKRALIGN32( sh4r.r[Rm] );

  1101                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);

  1102                                 sh4r.r[Rm] +=4;

  1103                                 }

  1104                                 break;

  1105                             case 0x6:

  1106                                 { /* LDS.L @Rm+, FPSCR */

  1107                                 uint32_t Rm = ((ir>>8)&0xF);

  1108                                 CHECKRALIGN32( sh4r.r[Rm] );

  1109                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);

  1110                                 sh4r.r[Rm] +=4;

  1111                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];

  1112                                 }

  1113                                 break;

  1114                             case 0xF:

  1115                                 { /* LDC.L @Rm+, DBR */

  1116                                 uint32_t Rm = ((ir>>8)&0xF);

  1117                                 CHECKPRIV();

  1118                                 CHECKRALIGN32( sh4r.r[Rm] );

  1119                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.dbr);

  1120                                 sh4r.r[Rm] +=4;

  1121                                 }

  1122                                 break;

  1123                             default:

  1124                                 UNDEF();

  1125                                 break;

  1126                         }

  1127                         break;

  1128                     case 0x7:

  1129                         switch( (ir&0x80) >> 7 ) {

  1130                             case 0x0:

  1131                                 switch( (ir&0x70) >> 4 ) {

  1132                                     case 0x0:

  1133                                         { /* LDC.L @Rm+, SR */

  1134                                         uint32_t Rm = ((ir>>8)&0xF);

  1135                                         CHECKSLOTILLEGAL();

  1136                                         CHECKPRIV();

  1137                                         CHECKWALIGN32( sh4r.r[Rm] );

  1138                                         MEM_READ_LONG(sh4r.r[Rm], tmp);

  1139                                         sh4_write_sr( tmp );

  1140                                         sh4r.r[Rm] +=4;

  1141                                         }

  1142                                         break;

  1143                                     case 0x1:

  1144                                         { /* LDC.L @Rm+, GBR */

  1145                                         uint32_t Rm = ((ir>>8)&0xF);

  1146                                         CHECKRALIGN32( sh4r.r[Rm] );

  1147                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.gbr);

  1148                                         sh4r.r[Rm] +=4;

  1149                                         }

  1150                                         break;

  1151                                     case 0x2:

  1152                                         { /* LDC.L @Rm+, VBR */

  1153                                         uint32_t Rm = ((ir>>8)&0xF);

  1154                                         CHECKPRIV();

  1155                                         CHECKRALIGN32( sh4r.r[Rm] );

  1156                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.vbr);

  1157                                         sh4r.r[Rm] +=4;

  1158                                         }

  1159                                         break;

  1160                                     case 0x3:

  1161                                         { /* LDC.L @Rm+, SSR */

  1162                                         uint32_t Rm = ((ir>>8)&0xF);

  1163                                         CHECKPRIV();

  1164                                         CHECKRALIGN32( sh4r.r[Rm] );

  1165                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.ssr);

  1166                                         sh4r.r[Rm] +=4;

  1167                                         }

  1168                                         break;

  1169                                     case 0x4:

  1170                                         { /* LDC.L @Rm+, SPC */

  1171                                         uint32_t Rm = ((ir>>8)&0xF);

  1172                                         CHECKPRIV();

  1173                                         CHECKRALIGN32( sh4r.r[Rm] );

  1174                                         MEM_READ_LONG(sh4r.r[Rm], sh4r.spc);

  1175                                         sh4r.r[Rm] +=4;

  1176                                         }

  1177                                         break;

  1178                                     default:

  1179                                         UNDEF();

  1180                                         break;

  1181                                 }

  1182                                 break;

  1183                             case 0x1:

  1184                                 { /* LDC.L @Rm+, Rn_BANK */

  1185                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1186                                 CHECKPRIV();

  1187                                 CHECKRALIGN32( sh4r.r[Rm] );

  1188                                 MEM_READ_LONG( sh4r.r[Rm], sh4r.r_bank[Rn_BANK] );

  1189                                 sh4r.r[Rm] += 4;

  1190                                 }

  1191                                 break;

  1192                         }

  1193                         break;

  1194                     case 0x8:

  1195                         switch( (ir&0xF0) >> 4 ) {

  1196                             case 0x0:

  1197                                 { /* SHLL2 Rn */

  1198                                 uint32_t Rn = ((ir>>8)&0xF);

  1199                                 sh4r.r[Rn] <<= 2;

  1200                                 }

  1201                                 break;

  1202                             case 0x1:

  1203                                 { /* SHLL8 Rn */

  1204                                 uint32_t Rn = ((ir>>8)&0xF);

  1205                                 sh4r.r[Rn] <<= 8;

  1206                                 }

  1207                                 break;

  1208                             case 0x2:

  1209                                 { /* SHLL16 Rn */

  1210                                 uint32_t Rn = ((ir>>8)&0xF);

  1211                                 sh4r.r[Rn] <<= 16;

  1212                                 }

  1213                                 break;

  1214                             default:

  1215                                 UNDEF();

  1216                                 break;

  1217                         }

  1218                         break;

  1219                     case 0x9:

  1220                         switch( (ir&0xF0) >> 4 ) {

  1221                             case 0x0:

  1222                                 { /* SHLR2 Rn */

  1223                                 uint32_t Rn = ((ir>>8)&0xF);

  1224                                 sh4r.r[Rn] >>= 2;

  1225                                 }

  1226                                 break;

  1227                             case 0x1:

  1228                                 { /* SHLR8 Rn */

  1229                                 uint32_t Rn = ((ir>>8)&0xF);

  1230                                 sh4r.r[Rn] >>= 8;

  1231                                 }

  1232                                 break;

  1233                             case 0x2:

  1234                                 { /* SHLR16 Rn */

  1235                                 uint32_t Rn = ((ir>>8)&0xF);

  1236                                 sh4r.r[Rn] >>= 16;

  1237                                 }

  1238                                 break;

  1239                             default:

  1240                                 UNDEF();

  1241                                 break;

  1242                         }

  1243                         break;

  1244                     case 0xA:

  1245                         switch( (ir&0xF0) >> 4 ) {

  1246                             case 0x0:

  1247                                 { /* LDS Rm, MACH */

  1248                                 uint32_t Rm = ((ir>>8)&0xF);

  1249                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |

  1250                                            (((uint64_t)sh4r.r[Rm])<<32);

  1251                                 }

  1252                                 break;

  1253                             case 0x1:

  1254                                 { /* LDS Rm, MACL */

  1255                                 uint32_t Rm = ((ir>>8)&0xF);

  1256                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1257                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));

  1258                                 }

  1259                                 break;

  1260                             case 0x2:

  1261                                 { /* LDS Rm, PR */

  1262                                 uint32_t Rm = ((ir>>8)&0xF);

  1263                                 sh4r.pr = sh4r.r[Rm];

  1264                                 }

  1265                                 break;

  1266                             case 0x3:

  1267                                 { /* LDC Rm, SGR */

  1268                                 uint32_t Rm = ((ir>>8)&0xF);

  1269                                 CHECKPRIV();

  1270                                 sh4r.sgr = sh4r.r[Rm];

  1271                                 }

  1272                                 break;

  1273                             case 0x5:

  1274                                 { /* LDS Rm, FPUL */

  1275                                 uint32_t Rm = ((ir>>8)&0xF);

  1276                                 sh4r.fpul = sh4r.r[Rm];

  1277                                 }

  1278                                 break;

  1279                             case 0x6:

  1280                                 { /* LDS Rm, FPSCR */

  1281                                 uint32_t Rm = ((ir>>8)&0xF);

  1282                                 sh4r.fpscr = sh4r.r[Rm];

  1283                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];

  1284                                 }

  1285                                 break;

  1286                             case 0xF:

  1287                                 { /* LDC Rm, DBR */

  1288                                 uint32_t Rm = ((ir>>8)&0xF);

  1289                                 CHECKPRIV();

  1290                                 sh4r.dbr = sh4r.r[Rm];

  1291                                 }

  1292                                 break;

  1293                             default:

  1294                                 UNDEF();

  1295                                 break;

  1296                         }

  1297                         break;

  1298                     case 0xB:

  1299                         switch( (ir&0xF0) >> 4 ) {

  1300                             case 0x0:

  1301                                 { /* JSR @Rn */

  1302                                 uint32_t Rn = ((ir>>8)&0xF);

  1303                                 CHECKDEST( sh4r.r[Rn] );

  1304                                 CHECKSLOTILLEGAL();

  1305                                 sh4r.in_delay_slot = 1;

  1306                                 sh4r.pc = sh4r.new_pc;

  1307                                 sh4r.new_pc = sh4r.r[Rn];

  1308                                 sh4r.pr = pc + 4;

  1309                                 TRACE_CALL( pc, sh4r.new_pc );

  1310                                 return TRUE;

  1311                                 }

  1312                                 break;

  1313                             case 0x1:

  1314                                 { /* TAS.B @Rn */

  1315                                 uint32_t Rn = ((ir>>8)&0xF);

  1316                                 MEM_READ_BYTE( sh4r.r[Rn], tmp );

  1317                                 sh4r.t = ( tmp == 0 ? 1 : 0 );

  1318                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );

  1319                                 }

  1320                                 break;

  1321                             case 0x2:

  1322                                 { /* JMP @Rn */

  1323                                 uint32_t Rn = ((ir>>8)&0xF);

  1324                                 CHECKDEST( sh4r.r[Rn] );

  1325                                 CHECKSLOTILLEGAL();

  1326                                 sh4r.in_delay_slot = 1;

  1327                                 sh4r.pc = sh4r.new_pc;

  1328                                 sh4r.new_pc = sh4r.r[Rn];

  1329                                 return TRUE;

  1330                                 }

  1331                                 break;

  1332                             default:

  1333                                 UNDEF();

  1334                                 break;

  1335                         }

  1336                         break;

  1337                     case 0xC:

  1338                         { /* SHAD Rm, Rn */

  1339                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1340                         tmp = sh4r.r[Rm];

  1341                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);

  1342                         else if( (tmp & 0x1F) == 0 )

  1343                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;

  1344                         else

  1345                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);

  1346                         }

  1347                         break;

  1348                     case 0xD:

  1349                         { /* SHLD Rm, Rn */

  1350                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1351                         tmp = sh4r.r[Rm];

  1352                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);

  1353                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;

  1354                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);

  1355                         }

  1356                         break;

  1357                     case 0xE:

  1358                         switch( (ir&0x80) >> 7 ) {

  1359                             case 0x0:

  1360                                 switch( (ir&0x70) >> 4 ) {

  1361                                     case 0x0:

  1362                                         { /* LDC Rm, SR */

  1363                                         uint32_t Rm = ((ir>>8)&0xF);

  1364                                         CHECKSLOTILLEGAL();

  1365                                         CHECKPRIV();

  1366                                         sh4_write_sr( sh4r.r[Rm] );

  1367                                         }

  1368                                         break;

  1369                                     case 0x1:

  1370                                         { /* LDC Rm, GBR */

  1371                                         uint32_t Rm = ((ir>>8)&0xF);

  1372                                         sh4r.gbr = sh4r.r[Rm];

  1373                                         }

  1374                                         break;

  1375                                     case 0x2:

  1376                                         { /* LDC Rm, VBR */

  1377                                         uint32_t Rm = ((ir>>8)&0xF);

  1378                                         CHECKPRIV();

  1379                                         sh4r.vbr = sh4r.r[Rm];

  1380                                         }

  1381                                         break;

  1382                                     case 0x3:

  1383                                         { /* LDC Rm, SSR */

  1384                                         uint32_t Rm = ((ir>>8)&0xF);

  1385                                         CHECKPRIV();

  1386                                         sh4r.ssr = sh4r.r[Rm];

  1387                                         }

  1388                                         break;

  1389                                     case 0x4:

  1390                                         { /* LDC Rm, SPC */

  1391                                         uint32_t Rm = ((ir>>8)&0xF);

  1392                                         CHECKPRIV();

  1393                                         sh4r.spc = sh4r.r[Rm];

  1394                                         }

  1395                                         break;

  1396                                     default:

  1397                                         UNDEF();

  1398                                         break;

  1399                                 }

  1400                                 break;

  1401                             case 0x1:

  1402                                 { /* LDC Rm, Rn_BANK */

  1403                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);

  1404                                 CHECKPRIV();

  1405                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];

  1406                                 }

  1407                                 break;

  1408                         }

  1409                         break;

  1410                     case 0xF:

  1411                         { /* MAC.W @Rm+, @Rn+ */

  1412                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1413                         CHECKRALIGN16( sh4r.r[Rn] );

  1414                         CHECKRALIGN16( sh4r.r[Rm] );

  1415                         MEM_READ_WORD(sh4r.r[Rn], tmp);

  1416                         int32_t stmp = SIGNEXT16(tmp);

  1417                         sh4r.r[Rn] += 2;

  1418                         MEM_READ_WORD(sh4r.r[Rm], tmp);

  1419                         stmp = stmp * SIGNEXT16(tmp);

  1420                         sh4r.r[Rm] += 2;

  1421                         if( sh4r.s ) {

  1422                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;

  1423                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {

  1424                     	    sh4r.mac = 0x000000017FFFFFFFLL;

  1425                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {

  1426                     	    sh4r.mac = 0x0000000180000000LL;

  1427                     	} else {

  1428                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |

  1429                     		((uint32_t)(sh4r.mac + stmp));

  1430                     	}

  1431                         } else {

  1432                     	sh4r.mac += SIGNEXT32(stmp);

  1433                         }

  1434                         }

  1435                         break;

  1436                 }

  1437                 break;

  1438             case 0x5:

  1439                 { /* MOV.L @(disp, Rm), Rn */

  1440                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;

  1441                 tmp = sh4r.r[Rm] + disp;

  1442                 CHECKRALIGN32( tmp );

  1443                 MEM_READ_LONG( tmp, sh4r.r[Rn] );

  1444                 }

  1445                 break;

  1446             case 0x6:

  1447                 switch( ir&0xF ) {

  1448                     case 0x0:

  1449                         { /* MOV.B @Rm, Rn */

  1450                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1451                         MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] );

  1452                         }

  1453                         break;

  1454                     case 0x1:

  1455                         { /* MOV.W @Rm, Rn */

  1456                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1457                         CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] );

  1458                         }

  1459                         break;

  1460                     case 0x2:

  1461                         { /* MOV.L @Rm, Rn */

  1462                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1463                         CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] );

  1464                         }

  1465                         break;

  1466                     case 0x3:

  1467                         { /* MOV Rm, Rn */

  1468                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1469                         sh4r.r[Rn] = sh4r.r[Rm];

  1470                         }

  1471                         break;

  1472                     case 0x4:

  1473                         { /* MOV.B @Rm+, Rn */

  1474                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1475                         MEM_READ_BYTE( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] ++;

  1476                         }

  1477                         break;

  1478                     case 0x5:

  1479                         { /* MOV.W @Rm+, Rn */

  1480                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1481                         CHECKRALIGN16( sh4r.r[Rm] ); MEM_READ_WORD( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 2;

  1482                         }

  1483                         break;

  1484                     case 0x6:

  1485                         { /* MOV.L @Rm+, Rn */

  1486                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1487                         CHECKRALIGN32( sh4r.r[Rm] ); MEM_READ_LONG( sh4r.r[Rm], sh4r.r[Rn] ); sh4r.r[Rm] += 4;

  1488                         }

  1489                         break;

  1490                     case 0x7:

  1491                         { /* NOT Rm, Rn */

  1492                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1493                         sh4r.r[Rn] = ~sh4r.r[Rm];

  1494                         }

  1495                         break;

  1496                     case 0x8:

  1497                         { /* SWAP.B Rm, Rn */

  1498                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1499                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);

  1500                         }

  1501                         break;

  1502                     case 0x9:

  1503                         { /* SWAP.W Rm, Rn */

  1504                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1505                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);

  1506                         }

  1507                         break;

  1508                     case 0xA:

  1509                         { /* NEGC Rm, Rn */

  1510                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1511                         tmp = 0 - sh4r.r[Rm];

  1512                         sh4r.r[Rn] = tmp - sh4r.t;

  1513                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );

  1514                         }

  1515                         break;

  1516                     case 0xB:

  1517                         { /* NEG Rm, Rn */

  1518                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1519                         sh4r.r[Rn] = 0 - sh4r.r[Rm];

  1520                         }

  1521                         break;

  1522                     case 0xC:

  1523                         { /* EXTU.B Rm, Rn */

  1524                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1525                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;

  1526                         }

  1527                         break;

  1528                     case 0xD:

  1529                         { /* EXTU.W Rm, Rn */

  1530                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1531                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;

  1532                         }

  1533                         break;

  1534                     case 0xE:

  1535                         { /* EXTS.B Rm, Rn */

  1536                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1537                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );

  1538                         }

  1539                         break;

  1540                     case 0xF:

  1541                         { /* EXTS.W Rm, Rn */

  1542                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1543                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );

  1544                         }

  1545                         break;

  1546                 }

  1547                 break;

  1548             case 0x7:

  1549                 { /* ADD #imm, Rn */

  1550                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1551                 sh4r.r[Rn] += imm;

  1552                 }

  1553                 break;

  1554             case 0x8:

  1555                 switch( (ir&0xF00) >> 8 ) {

  1556                     case 0x0:

  1557                         { /* MOV.B R0, @(disp, Rn) */

  1558                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1559                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );

  1560                         }

  1561                         break;

  1562                     case 0x1:

  1563                         { /* MOV.W R0, @(disp, Rn) */

  1564                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1565                         tmp = sh4r.r[Rn] + disp;

  1566                         CHECKWALIGN16( tmp );

  1567                         MEM_WRITE_WORD( tmp, R0 );

  1568                         }

  1569                         break;

  1570                     case 0x4:

  1571                         { /* MOV.B @(disp, Rm), R0 */

  1572                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);

  1573                         MEM_READ_BYTE( sh4r.r[Rm] + disp, R0 );

  1574                         }

  1575                         break;

  1576                     case 0x5:

  1577                         { /* MOV.W @(disp, Rm), R0 */

  1578                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;

  1579                         tmp = sh4r.r[Rm] + disp;

  1580                         CHECKRALIGN16( tmp );

  1581                         MEM_READ_WORD( tmp, R0 );

  1582                         }

  1583                         break;

  1584                     case 0x8:

  1585                         { /* CMP/EQ #imm, R0 */

  1586                         int32_t imm = SIGNEXT8(ir&0xFF);

  1587                         sh4r.t = ( R0 == imm ? 1 : 0 );

  1588                         }

  1589                         break;

  1590                     case 0x9:

  1591                         { /* BT disp */

  1592                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1593                         CHECKSLOTILLEGAL();

  1594                         if( sh4r.t ) {

  1595                             CHECKDEST( sh4r.pc + disp + 4 )

  1596                             sh4r.pc += disp + 4;

  1597                             sh4r.new_pc = sh4r.pc + 2;

  1598                             return TRUE;

  1599                         }

  1600                         }

  1601                         break;

  1602                     case 0xB:

  1603                         { /* BF disp */

  1604                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1605                         CHECKSLOTILLEGAL();

  1606                         if( !sh4r.t ) {

  1607                             CHECKDEST( sh4r.pc + disp + 4 )

  1608                             sh4r.pc += disp + 4;

  1609                             sh4r.new_pc = sh4r.pc + 2;

  1610                             return TRUE;

  1611                         }

  1612                         }

  1613                         break;

  1614                     case 0xD:

  1615                         { /* BT/S disp */

  1616                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1617                         CHECKSLOTILLEGAL();

  1618                         if( sh4r.t ) {

  1619                             CHECKDEST( sh4r.pc + disp + 4 )

  1620                             sh4r.in_delay_slot = 1;

  1621                             sh4r.pc = sh4r.new_pc;

  1622                             sh4r.new_pc = pc + disp + 4;

  1623                             sh4r.in_delay_slot = 1;

  1624                             return TRUE;

  1625                         }

  1626                         }

  1627                         break;

  1628                     case 0xF:

  1629                         { /* BF/S disp */

  1630                         int32_t disp = SIGNEXT8(ir&0xFF)<<1;

  1631                         CHECKSLOTILLEGAL();

  1632                         if( !sh4r.t ) {

  1633                             CHECKDEST( sh4r.pc + disp + 4 )

  1634                             sh4r.in_delay_slot = 1;

  1635                             sh4r.pc = sh4r.new_pc;

  1636                             sh4r.new_pc = pc + disp + 4;

  1637                             return TRUE;

  1638                         }

  1639                         }

  1640                         break;

  1641                     default:

  1642                         UNDEF();

  1643                         break;

  1644                 }

  1645                 break;

  1646             case 0x9:

  1647                 { /* MOV.W @(disp, PC), Rn */

  1648                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;

  1649                 CHECKSLOTILLEGAL();

  1650                 tmp = pc + 4 + disp;

  1651                 MEM_READ_WORD( tmp, sh4r.r[Rn] );

  1652                 }

  1653                 break;

  1654             case 0xA:

  1655                 { /* BRA disp */

  1656                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1657                 CHECKSLOTILLEGAL();

  1658                 CHECKDEST( sh4r.pc + disp + 4 );

  1659                 sh4r.in_delay_slot = 1;

  1660                 sh4r.pc = sh4r.new_pc;

  1661                 sh4r.new_pc = pc + 4 + disp;

  1662                 return TRUE;

  1663                 }

  1664                 break;

  1665             case 0xB:

  1666                 { /* BSR disp */

  1667                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;

  1668                 CHECKDEST( sh4r.pc + disp + 4 );

  1669                 CHECKSLOTILLEGAL();

  1670                 sh4r.in_delay_slot = 1;

  1671                 sh4r.pr = pc + 4;

  1672                 sh4r.pc = sh4r.new_pc;

  1673                 sh4r.new_pc = pc + 4 + disp;

  1674                 TRACE_CALL( pc, sh4r.new_pc );

  1675                 return TRUE;

  1676                 }

  1677                 break;

  1678             case 0xC:

  1679                 switch( (ir&0xF00) >> 8 ) {

  1680                     case 0x0:

  1681                         { /* MOV.B R0, @(disp, GBR) */

  1682                         uint32_t disp = (ir&0xFF);

  1683                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );

  1684                         }

  1685                         break;

  1686                     case 0x1:

  1687                         { /* MOV.W R0, @(disp, GBR) */

  1688                         uint32_t disp = (ir&0xFF)<<1;

  1689                         tmp = sh4r.gbr + disp;

  1690                         CHECKWALIGN16( tmp );

  1691                         MEM_WRITE_WORD( tmp, R0 );

  1692                         }

  1693                         break;

  1694                     case 0x2:

  1695                         { /* MOV.L R0, @(disp, GBR) */

  1696                         uint32_t disp = (ir&0xFF)<<2;

  1697                         tmp = sh4r.gbr + disp;

  1698                         CHECKWALIGN32( tmp );

  1699                         MEM_WRITE_LONG( tmp, R0 );

  1700                         }

  1701                         break;

  1702                     case 0x3:

  1703                         { /* TRAPA #imm */

  1704                         uint32_t imm = (ir&0xFF);

  1705                         CHECKSLOTILLEGAL();

  1706                         MMIO_WRITE( MMU, TRA, imm<<2 );

  1707                         sh4r.pc += 2;

  1708                         sh4_raise_exception( EXC_TRAP );

  1709                         }

  1710                         break;

  1711                     case 0x4:

  1712                         { /* MOV.B @(disp, GBR), R0 */

  1713                         uint32_t disp = (ir&0xFF);

  1714                         MEM_READ_BYTE( sh4r.gbr + disp, R0 );

  1715                         }

  1716                         break;

  1717                     case 0x5:

  1718                         { /* MOV.W @(disp, GBR), R0 */

  1719                         uint32_t disp = (ir&0xFF)<<1;

  1720                         tmp = sh4r.gbr + disp;

  1721                         CHECKRALIGN16( tmp );

  1722                         MEM_READ_WORD( tmp, R0 );

  1723                         }

  1724                         break;

  1725                     case 0x6:

  1726                         { /* MOV.L @(disp, GBR), R0 */

  1727                         uint32_t disp = (ir&0xFF)<<2;

  1728                         tmp = sh4r.gbr + disp;

  1729                         CHECKRALIGN32( tmp );

  1730                         MEM_READ_LONG( tmp, R0 );

  1731                         }

  1732                         break;

  1733                     case 0x7:

  1734                         { /* MOVA @(disp, PC), R0 */

  1735                         uint32_t disp = (ir&0xFF)<<2;

  1736                         CHECKSLOTILLEGAL();

  1737                         R0 = (pc&0xFFFFFFFC) + disp + 4;

  1738                         }

  1739                         break;

  1740                     case 0x8:

  1741                         { /* TST #imm, R0 */

  1742                         uint32_t imm = (ir&0xFF);

  1743                         sh4r.t = (R0 & imm ? 0 : 1);

  1744                         }

  1745                         break;

  1746                     case 0x9:

  1747                         { /* AND #imm, R0 */

  1748                         uint32_t imm = (ir&0xFF);

  1749                         R0 &= imm;

  1750                         }

  1751                         break;

  1752                     case 0xA:

  1753                         { /* XOR #imm, R0 */

  1754                         uint32_t imm = (ir&0xFF);

  1755                         R0 ^= imm;

  1756                         }

  1757                         break;

  1758                     case 0xB:

  1759                         { /* OR #imm, R0 */

  1760                         uint32_t imm = (ir&0xFF);

  1761                         R0 |= imm;

  1762                         }

  1763                         break;

  1764                     case 0xC:

  1765                         { /* TST.B #imm, @(R0, GBR) */

  1766                         uint32_t imm = (ir&0xFF);

  1767                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); sh4r.t = ( tmp & imm ? 0 : 1 );

  1768                         }

  1769                         break;

  1770                     case 0xD:

  1771                         { /* AND.B #imm, @(R0, GBR) */

  1772                         uint32_t imm = (ir&0xFF);

  1773                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & tmp );

  1774                         }

  1775                         break;

  1776                     case 0xE:

  1777                         { /* XOR.B #imm, @(R0, GBR) */

  1778                         uint32_t imm = (ir&0xFF);

  1779                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ tmp );

  1780                         }

  1781                         break;

  1782                     case 0xF:

  1783                         { /* OR.B #imm, @(R0, GBR) */

  1784                         uint32_t imm = (ir&0xFF);

  1785                         MEM_READ_BYTE(R0+sh4r.gbr, tmp); MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | tmp );

  1786                         }

  1787                         break;

  1788                 }

  1789                 break;

  1790             case 0xD:

  1791                 { /* MOV.L @(disp, PC), Rn */

  1792                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;

  1793                 CHECKSLOTILLEGAL();

  1794                 tmp = (pc&0xFFFFFFFC) + disp + 4;

  1795                 MEM_READ_LONG( tmp, sh4r.r[Rn] );

  1796                 }

  1797                 break;

  1798             case 0xE:

  1799                 { /* MOV #imm, Rn */

  1800                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);

  1801                 sh4r.r[Rn] = imm;

  1802                 }

  1803                 break;

  1804             case 0xF:

  1805                 switch( ir&0xF ) {

  1806                     case 0x0:

  1807                         { /* FADD FRm, FRn */

  1808                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1809                         CHECKFPUEN();

  1810                         if( IS_FPU_DOUBLEPREC() ) {

  1811                     	DR(FRn) += DR(FRm);

  1812                         } else {

  1813                     	FR(FRn) += FR(FRm);

  1814                         }

  1815                         }

  1816                         break;

  1817                     case 0x1:

  1818                         { /* FSUB FRm, FRn */

  1819                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1820                         CHECKFPUEN();

  1821                         if( IS_FPU_DOUBLEPREC() ) {

  1822                     	DR(FRn) -= DR(FRm);

  1823                         } else {

  1824                     	FR(FRn) -= FR(FRm);

  1825                         }

  1826                         }

  1827                         break;

  1828                     case 0x2:

  1829                         { /* FMUL FRm, FRn */

  1830                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1831                         CHECKFPUEN();

  1832                         if( IS_FPU_DOUBLEPREC() ) {

  1833                     	DR(FRn) *= DR(FRm);

  1834                         } else {

  1835                     	FR(FRn) *= FR(FRm);

  1836                         }

  1837                         }

  1838                         break;

  1839                     case 0x3:

  1840                         { /* FDIV FRm, FRn */

  1841                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1842                         CHECKFPUEN();

  1843                         if( IS_FPU_DOUBLEPREC() ) {

  1844                     	DR(FRn) /= DR(FRm);

  1845                         } else {

  1846                     	FR(FRn) /= FR(FRm);

  1847                         }

  1848                         }

  1849                         break;

  1850                     case 0x4:

  1851                         { /* FCMP/EQ FRm, FRn */

  1852                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1853                         CHECKFPUEN();

  1854                         if( IS_FPU_DOUBLEPREC() ) {

  1855                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );

  1856                         } else {

  1857                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );

  1858                         }

  1859                         }

  1860                         break;

  1861                     case 0x5:

  1862                         { /* FCMP/GT FRm, FRn */

  1863                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1864                         CHECKFPUEN();

  1865                         if( IS_FPU_DOUBLEPREC() ) {

  1866                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );

  1867                         } else {

  1868                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );

  1869                         }

  1870                         }

  1871                         break;

  1872                     case 0x6:

  1873                         { /* FMOV @(R0, Rm), FRn */

  1874                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1875                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );

  1876                         }

  1877                         break;

  1878                     case 0x7:

  1879                         { /* FMOV FRm, @(R0, Rn) */

  1880                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1881                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );

  1882                         }

  1883                         break;

  1884                     case 0x8:

  1885                         { /* FMOV @Rm, FRn */

  1886                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1887                         MEM_FP_READ( sh4r.r[Rm], FRn );

  1888                         }

  1889                         break;

  1890                     case 0x9:

  1891                         { /* FMOV @Rm+, FRn */

  1892                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);

  1893                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;

  1894                         }

  1895                         break;

  1896                     case 0xA:

  1897                         { /* FMOV FRm, @Rn */

  1898                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1899                         MEM_FP_WRITE( sh4r.r[Rn], FRm );

  1900                         }

  1901                         break;

  1902                     case 0xB:

  1903                         { /* FMOV FRm, @-Rn */

  1904                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1905                         sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );

  1906                         }

  1907                         break;

  1908                     case 0xC:

  1909                         { /* FMOV FRm, FRn */

  1910                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  1911                         if( IS_FPU_DOUBLESIZE() )

  1912                     	DR(FRn) = DR(FRm);

  1913                         else

  1914                     	FR(FRn) = FR(FRm);

  1915                         }

  1916                         break;

  1917                     case 0xD:

  1918                         switch( (ir&0xF0) >> 4 ) {

  1919                             case 0x0:

  1920                                 { /* FSTS FPUL, FRn */

  1921                                 uint32_t FRn = ((ir>>8)&0xF);

  1922                                 CHECKFPUEN(); FR(FRn) = FPULf;

  1923                                 }

  1924                                 break;

  1925                             case 0x1:

  1926                                 { /* FLDS FRm, FPUL */

  1927                                 uint32_t FRm = ((ir>>8)&0xF);

  1928                                 CHECKFPUEN(); FPULf = FR(FRm);

  1929                                 }

  1930                                 break;

  1931                             case 0x2:

  1932                                 { /* FLOAT FPUL, FRn */

  1933                                 uint32_t FRn = ((ir>>8)&0xF);

  1934                                 CHECKFPUEN();

  1935                                 if( IS_FPU_DOUBLEPREC() ) {

  1936                             	if( FRn&1 ) { // No, really...

  1937                             	    dtmp = (double)FPULi;

  1938                             	    FR(FRn) = *(((float *)&dtmp)+1);

  1939                             	} else {

  1940                             	    DRF(FRn>>1) = (double)FPULi;

  1941                             	}

  1942                                 } else {

  1943                             	FR(FRn) = (float)FPULi;

  1944                                 }

  1945                                 }

  1946                                 break;

  1947                             case 0x3:

  1948                                 { /* FTRC FRm, FPUL */

  1949                                 uint32_t FRm = ((ir>>8)&0xF);

  1950                                 CHECKFPUEN();

  1951                                 if( IS_FPU_DOUBLEPREC() ) {

  1952                             	if( FRm&1 ) {

  1953                             	    dtmp = 0;

  1954                             	    *(((float *)&dtmp)+1) = FR(FRm);

  1955                             	} else {

  1956                             	    dtmp = DRF(FRm>>1);

  1957                             	}

  1958                                     if( dtmp >= MAX_INTF )

  1959                                         FPULi = MAX_INT;

  1960                                     else if( dtmp <= MIN_INTF )

  1961                                         FPULi = MIN_INT;

  1962                                     else

  1963                                         FPULi = (int32_t)dtmp;

  1964                                 } else {

  1965                             	ftmp = FR(FRm);

  1966                             	if( ftmp >= MAX_INTF )

  1967                             	    FPULi = MAX_INT;

  1968                             	else if( ftmp <= MIN_INTF )

  1969                             	    FPULi = MIN_INT;

  1970                             	else

  1971                             	    FPULi = (int32_t)ftmp;

  1972                                 }

  1973                                 }

  1974                                 break;

  1975                             case 0x4:

  1976                                 { /* FNEG FRn */

  1977                                 uint32_t FRn = ((ir>>8)&0xF);

  1978                                 CHECKFPUEN();

  1979                                 if( IS_FPU_DOUBLEPREC() ) {

  1980                             	DR(FRn) = -DR(FRn);

  1981                                 } else {

  1982                                     FR(FRn) = -FR(FRn);

  1983                                 }

  1984                                 }

  1985                                 break;

  1986                             case 0x5:

  1987                                 { /* FABS FRn */

  1988                                 uint32_t FRn = ((ir>>8)&0xF);

  1989                                 CHECKFPUEN();

  1990                                 if( IS_FPU_DOUBLEPREC() ) {

  1991                             	DR(FRn) = fabs(DR(FRn));

  1992                                 } else {

  1993                                     FR(FRn) = fabsf(FR(FRn));

  1994                                 }

  1995                                 }

  1996                                 break;

  1997                             case 0x6:

  1998                                 { /* FSQRT FRn */

  1999                                 uint32_t FRn = ((ir>>8)&0xF);

  2000                                 CHECKFPUEN();

  2001                                 if( IS_FPU_DOUBLEPREC() ) {

  2002                             	DR(FRn) = sqrt(DR(FRn));

  2003                                 } else {

  2004                                     FR(FRn) = sqrtf(FR(FRn));

  2005                                 }

  2006                                 }

  2007                                 break;

  2008                             case 0x7:

  2009                                 { /* FSRRA FRn */

  2010                                 uint32_t FRn = ((ir>>8)&0xF);

  2011                                 CHECKFPUEN();

  2012                                 if( !IS_FPU_DOUBLEPREC() ) {

  2013                             	FR(FRn) = 1.0/sqrtf(FR(FRn));

  2014                                 }

  2015                                 }

  2016                                 break;

  2017                             case 0x8:

  2018                                 { /* FLDI0 FRn */

  2019                                 uint32_t FRn = ((ir>>8)&0xF);

  2020                                 CHECKFPUEN();

  2021                                 if( IS_FPU_DOUBLEPREC() ) {

  2022                             	DR(FRn) = 0.0;

  2023                                 } else {

  2024                                     FR(FRn) = 0.0;

  2025                                 }

  2026                                 }

  2027                                 break;

  2028                             case 0x9:

  2029                                 { /* FLDI1 FRn */

  2030                                 uint32_t FRn = ((ir>>8)&0xF);

  2031                                 CHECKFPUEN();

  2032                                 if( IS_FPU_DOUBLEPREC() ) {

  2033                             	DR(FRn) = 1.0;

  2034                                 } else {

  2035                                     FR(FRn) = 1.0;

  2036                                 }

  2037                                 }

  2038                                 break;

  2039                             case 0xA:

  2040                                 { /* FCNVSD FPUL, FRn */

  2041                                 uint32_t FRn = ((ir>>8)&0xF);

  2042                                 CHECKFPUEN();

  2043                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {

  2044                             	DR(FRn) = (double)FPULf;

  2045                                 }

  2046                                 }

  2047                                 break;

  2048                             case 0xB:

  2049                                 { /* FCNVDS FRm, FPUL */

  2050                                 uint32_t FRm = ((ir>>8)&0xF);

  2051                                 CHECKFPUEN();

  2052                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {

  2053                             	FPULf = (float)DR(FRm);

  2054                                 }

  2055                                 }

  2056                                 break;

  2057                             case 0xE:

  2058                                 { /* FIPR FVm, FVn */

  2059                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);

  2060                                 CHECKFPUEN();

  2061                                 if( !IS_FPU_DOUBLEPREC() ) {

  2062                                     int tmp2 = FVn<<2;

  2063                                     tmp = FVm<<2;

  2064                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +

  2065                                         FR(tmp+1)*FR(tmp2+1) +

  2066                                         FR(tmp+2)*FR(tmp2+2) +

  2067                                         FR(tmp+3)*FR(tmp2+3);

  2068                                 }

  2069                                 }

  2070                                 break;

  2071                             case 0xF:

  2072                                 switch( (ir&0x100) >> 8 ) {

  2073                                     case 0x0:

  2074                                         { /* FSCA FPUL, FRn */

  2075                                         uint32_t FRn = ((ir>>9)&0x7)<<1;

  2076                                         CHECKFPUEN();

  2077                                         if( !IS_FPU_DOUBLEPREC() ) {

  2078                                     	sh4_fsca( FPULi, &(DRF(FRn>>1)) );

  2079                                     	/*

  2080                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;

  2081                                             FR(FRn) = sinf(angle);

  2082                                             FR((FRn)+1) = cosf(angle);

  2083                                     	*/

  2084                                         }

  2085                                         }

  2086                                         break;

  2087                                     case 0x1:

  2088                                         switch( (ir&0x200) >> 9 ) {

  2089                                             case 0x0:

  2090                                                 { /* FTRV XMTRX, FVn */

  2091                                                 uint32_t FVn = ((ir>>10)&0x3);

  2092                                                 CHECKFPUEN();

  2093                                                 if( !IS_FPU_DOUBLEPREC() ) {

  2094                                             	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);

  2095                                             	/*

  2096                                                     tmp = FVn<<2;

  2097                                             	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];

  2098                                                     float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };

  2099                                                     FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +

  2100                                             	    xf[9]*fv[2] + xf[13]*fv[3];

  2101                                                     FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +

  2102                                             	    xf[8]*fv[2] + xf[12]*fv[3];

  2103                                                     FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +

  2104                                             	    xf[11]*fv[2] + xf[15]*fv[3];

  2105                                                     FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +

  2106                                             	    xf[10]*fv[2] + xf[14]*fv[3];

  2107                                             	*/

  2108                                                 }

  2109                                                 }

  2110                                                 break;

  2111                                             case 0x1:

  2112                                                 switch( (ir&0xC00) >> 10 ) {

  2113                                                     case 0x0:

  2114                                                         { /* FSCHG */

  2115                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;

  2116                                                         }

  2117                                                         break;

  2118                                                     case 0x2:

  2119                                                         { /* FRCHG */

  2120                                                         CHECKFPUEN();

  2121                                                         sh4r.fpscr ^= FPSCR_FR;

  2122                                                         sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];

  2123                                                         }

  2124                                                         break;

  2125                                                     case 0x3:

  2126                                                         { /* UNDEF */

  2127                                                         UNDEF(ir);

  2128                                                         }

  2129                                                         break;

  2130                                                     default:

  2131                                                         UNDEF();

  2132                                                         break;

  2133                                                 }

  2134                                                 break;

  2135                                         }

  2136                                         break;

  2137                                 }

  2138                                 break;

  2139                             default:

  2140                                 UNDEF();

  2141                                 break;

  2142                         }

  2143                         break;

  2144                     case 0xE:

  2145                         { /* FMAC FR0, FRm, FRn */

  2146                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);

  2147                         CHECKFPUEN();

  2148                         if( IS_FPU_DOUBLEPREC() ) {

  2149                             DR(FRn) += DR(FRm)*DR(0);

  2150                         } else {

  2151                     	FR(FRn) += FR(FRm)*FR(0);

  2152                         }

  2153                         }

  2154                         break;

  2155                     default:

  2156                         UNDEF();

  2157                         break;

  2158                 }

  2159                 break;

  2160         }

  2162     sh4r.pc = sh4r.new_pc;

  2163     sh4r.new_pc += 2;

  2164     sh4r.in_delay_slot = 0;

  2165     return TRUE;

  2166 }