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lxdream.org :: lxdream/src/asic.c
lxdream 0.9.1
released Jun 29
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filename src/asic.c
changeset 1:eea311cfd33e
next2:42349f6ea216
author nkeynes
date Sat Mar 13 00:03:32 2004 +0000 (15 years ago)
permissions -rw-r--r--
last change This commit was generated by cvs2svn to compensate for changes in r2,
which included commits to RCS files with non-trunk default branches.
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     1 #include <assert.h>
     2 #include "dream.h"
     3 #include "mem.h"
     4 #include "sh4/intc.h"
     5 #include "asic.h"
     6 #include "maple.h"
     7 #define MMIO_IMPL
     8 #include "asic.h"
     9 /*
    10  * Open questions:
    11  *   1) Does changing the mask after event occurance result in the
    12  *      interrupt being delivered immediately?
    13  *   2) If the pending register is not cleared after an interrupt, does
    14  *      the interrupt line remain high? (ie does the IRQ reoccur?)
    15  * TODO: Logic diagram of ASIC event/interrupt logic.
    16  *
    17  * ... don't even get me started on the "EXTDMA" page, about which, apparently,
    18  * practically nothing is publicly known...
    19  */
    21 void asic_init( void )
    22 {
    23     register_io_region( &mmio_region_ASIC );
    24     register_io_region( &mmio_region_EXTDMA );
    25     mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
    26     asic_event( EVENT_GDROM_CMD );
    27 }
    29 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
    30 {
    31     switch( reg ) {
    32         case PIRQ0:
    33         case PIRQ1:
    34         case PIRQ2:
    35             /* Clear any interrupts */
    36             MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
    37             break;
    38         case MAPLE_STATE:
    39             MMIO_WRITE( ASIC, reg, val );
    40             if( val & 1 ) {
    41                 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
    42 //                maple_handle_buffer( maple_addr );
    43 		WARN( "Maple request initiated, halting" );
    44                 MMIO_WRITE( ASIC, reg, 0 );
    45                 sh4_stop();
    46             }
    47             break;
    48         default:
    49             MMIO_WRITE( ASIC, reg, val );
    50             WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
    51                   reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
    52     }
    53 }
    55 int32_t mmio_region_ASIC_read( uint32_t reg )
    56 {
    57     int32_t val;
    58     switch( reg ) {
    59         case PIRQ0:
    60         case PIRQ1:
    61         case PIRQ2:
    62             val = MMIO_READ(ASIC, reg);
    63 //            WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
    64 //                  reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
    65             return val;            
    66         case G2STATUS:
    67             return 0; /* find out later if there's any cases we actually need to care about */
    68         default:
    69             val = MMIO_READ(ASIC, reg);
    70             WARN( "Read from ASIC (%03X => %08X) [%s: %s]",
    71                   reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
    72             return val;
    73     }
    75 }
    77 void asic_event( int event )
    78 {
    79     int offset = ((event&0x60)>>3);
    80     int result = (MMIO_READ(ASIC, PIRQ0 + offset))  |=  (1<<(event&0x1F));
    82     if( result & MMIO_READ(ASIC, IRQA0 + offset) )
    83         intc_raise_interrupt( INT_IRQ13 );
    84     if( result & MMIO_READ(ASIC, IRQB0 + offset) )
    85         intc_raise_interrupt( INT_IRQ11 );
    86     if( result & MMIO_READ(ASIC, IRQC0 + offset) )
    87         intc_raise_interrupt( INT_IRQ9 );
    88 }
    92 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
    93 {
    94     MMIO_WRITE( EXTDMA, reg, val );
    95 }
    97 MMIO_REGION_READ_FN( EXTDMA, reg )
    98 {
    99     switch( reg ) {
   100         case GDBUSY: return 0;
   101         default:
   102             return MMIO_READ( EXTDMA, reg );
   103     }
   104 }
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