lxdream 0.9.1| filename | src/sh4/sh4core.h |
| changeset | 1:eea311cfd33e |
| next | 2:42349f6ea216 |
| author | nkeynes |
| date | Sat Mar 13 00:03:32 2004 +0000 (16 years ago) |
| permissions | -rw-r--r-- |
| last change | This commit was generated by cvs2svn to compensate for changes in r2, which included commits to RCS files with non-trunk default branches. |
| view | annotate | diff | log | raw |
1 /*
2 * Header for the basic sh4 emulator core
3 */
4 #ifndef sh4core_H
5 #define sh4core_H 1
7 #include <stdint.h>
9 #ifdef __cplusplus
10 extern "C" {
11 #if 0
12 }
13 #endif
14 #endif
16 struct sh4_registers {
17 uint32_t r[16];
18 uint32_t r_bank[8]; /* hidden banked registers */
19 uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
20 uint32_t pr, pc, fpul, fpscr;
21 uint64_t mac;
22 uint32_t m, q, s, t; /* really boolean - 0 or 1 */
23 float fr[2][16];
25 uint32_t new_pc; /* Not a real register, but used to handle delay slots */
26 uint32_t icount; /* Also not a real register, instruction counter */
27 uint32_t int_pending; /* flag set by the INTC = pending priority level */
28 };
30 extern struct sh4_registers sh4r;
32 /* Public functions */
34 void sh4_init( void );
35 void sh4_reset( void );
36 void sh4_run( void );
37 void sh4_runto( uint32_t pc, uint32_t count );
38 void sh4_runfor( uint32_t count );
39 int sh4_isrunning( void );
40 void sh4_stop( void );
41 void sh4_set_pc( int );
42 void sh4_execute_instruction( void );
43 void sh4_raise_exception( int, int );
45 void run_timers( int );
47 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
48 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
49 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
50 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
51 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
52 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
54 /* Status Register (SR) bits */
55 #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
56 #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
57 #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */
58 #define SR_FD 0x00008000 /* FPU disable */
59 #define SR_M 0x00000200
60 #define SR_Q 0x00000100
61 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
62 #define SR_S 0x00000002 /* Saturation operation for MAC instructions */
63 #define SR_T 0x00000001 /* True/false or carry/borrow */
64 #define SR_MASK 0x700083F3
65 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
67 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
68 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
69 #define SH4_INT_PENDING() (sh4r.int_pending)
71 #define FPSCR_FR 0x00200000 /* FPU register bank */
72 #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
73 #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */
74 #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */
75 #define FPSCR_CAUSE 0x0003F000
76 #define FPSCR_ENABLE 0x00000F80
77 #define FPSCR_FLAG 0x0000007C
78 #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
80 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
81 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
82 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
84 #define FR sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]
86 /* Exceptions (for use with sh4_raise_exception) */
88 #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
89 #define EX_SLOT_ILLEGAL 0x1A0, 0x100
90 #define EX_TLB_MISS_READ 0x040, 0x400
91 #define EX_TLB_MISS_WRITE 0x060, 0x400
92 #define EX_INIT_PAGE_WRITE 0x080, 0x100
93 #define EX_TLB_PROT_READ 0x0A0, 0x100
94 #define EX_TLB_PROT_WRITE 0x0C0, 0x100
95 #define EX_DATA_ADDR_READ 0x0E0, 0x100
96 #define EX_DATA_ADDR_WRITE 0x100, 0x100
97 #define EX_FPU_EXCEPTION 0x120, 0x100
98 #define EX_TRAPA 0x160, 0x100
99 #define EX_BREAKPOINT 0x1E0, 0x100
100 #define EX_FPU_DISABLED 0x800, 0x100
101 #define EX_SLOT_FPU_DISABLED 0x820, 0x100
105 #ifdef __cplusplus
106 }
107 #endif
108 #endif
.