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lxdream.org :: lxdream/src/tst1.c
lxdream 0.9.1
released Jun 29
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filename src/tst1.c
changeset 1:eea311cfd33e
author nkeynes
date Sat Mar 13 00:03:32 2004 +0000 (15 years ago)
permissions -rw-r--r--
last change This commit was generated by cvs2svn to compensate for changes in r2,
which included commits to RCS files with non-trunk default branches.
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     1 #include <stdint.h>
     3 #define PORT_R 1
     4 #define PORT_W 2
     5 #define PORT_MEM 4 /* store written value */
     6 #define PORT_RW 3
     7 #define PORT_MRW 7
     8 #define UNDEFINED 0
    10 struct mmio_region {
    11     char *id, *desc;
    12     uint32_t base;
    13     char *mem;
    14     struct mmio_port {
    15         char *id, *desc;
    16         int width;
    17         uint32_t offset;
    18         uint32_t default;
    19         int flags;
    20     } *ports;
    21 };
    23 #define _MACROIZE #define
    25 #define MMIO_REGION_BEGIN(b,id,d) struct mmio_region mmio_region_##id = { #id, d, b, NULL, 
    26 #define LONG_PORT( o,id,f,def,d ) { #id, desc, 32, o, def, f }, \
    27 _MACROIZE port_##id o \
    28 _MACROIZE reg_##id  (*(uint32_t *)(mmio_region_##id.mem + o))
    29 #define WORD_PORT( o,id,f,def,d ) { #id, desc, 16, o, def, f },
    30 #define BYTE_PORT( o,id,f,def,d ) { #id, desc, 8, o, def, f },
    31 #define MMIO_REGION_END {NULL, NULL, 0, 0, 0} };
    33 MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" )
    34     LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" ),
    35     LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" ),
    36 MMIO_REGION_END
    38 MMIO_REGION_BEGIN( BSC, 0xFF800000, "I/O Port Registers" )
    39     LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "" ),
    40     WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "" ),
    41     LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "" ),
    42     LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "" ),
    43     LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "" ),
    44     LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" ),
    45     WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" ),
    46     LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" ),
    47     WORD_PORT( 0x044, PCTRB, PORT_RW, UNDEFINED, "Port data register B" ),
    48     WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" )
    49 MMIO_REGION_END
    51 MMIO_REGION_BEGIN( SCI, 0xFFE00000, "Serial Controller Registers" )
    53 MMIO_REGION_END
    55 MMIO_REGIN_BEGIN( SCIF, 0xFFE80000, "Serial Controller (FIFO) Registers" )
    56 MMIO_REGION_END
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