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lxdream.org :: lxdream/src/sh4/sh4mmio.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4mmio.h
changeset 819:ef4fec10a63a
prev818:2e08d8237d33
next826:69f2c9f1e608
author nkeynes
date Tue Aug 19 22:58:05 2008 +0000 (12 years ago)
permissions -rw-r--r--
last change Add stubs for the (undocumented) SH4 performance counter registers
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     1 /**
     2  * $Id$
     3  * 
     4  * MMIO region and supporting function declarations. Private to the sh4
     5  * module.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #include "lxdream.h"
    21 #include "mmio.h"
    23 #if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \
    24     (!defined(MMIO_IMPL) && !defined(SH4MMIO_IFACE))
    26 #ifdef __cplusplus
    27 extern "C" {
    28 #endif
    30 #ifdef MMIO_IMPL
    31 #define SH4MMIO_IMPL
    32 #else
    33 #define SH4MMIO_IFACE
    34 #endif
    35 /* SH7750 onchip mmio devices */
    37 MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" )
    38     LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" )
    39     LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" )
    40     LONG_PORT( 0x008, TTB,  PORT_MRW, UNDEFINED, "Translation table base" )
    41     LONG_PORT( 0x00C, TEA,  PORT_MRW, UNDEFINED, "TLB exception address" )
    42     LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" )
    43     BYTE_PORT( 0x014, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */
    44     BYTE_PORT( 0x018, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */
    45     LONG_PORT( 0x01C, CCR,  PORT_MRW, 0, "Cache control register" )
    46     LONG_PORT( 0x020, TRA,  PORT_MRW, UNDEFINED, "TRAPA exception register" )
    47     LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" )
    48     LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" )
    49     LONG_PORT( 0x030, SH4VER, PORT_MRW, 0x040205C1, "SH4 version register (PVR)" ) /* Renamed to avoid naming conflict */
    50     LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" )
    51     LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" )
    52     LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" )
    53     WORD_PORT( 0x084, PMCR1, PORT_MRW, 0, "Performance counter control 1" )
    54     WORD_PORT( 0x088, PMCR2, PORT_MRW, 0, "Performance counter control 2" )
    55 MMIO_REGION_END
    57 /* Performance counter values (undocumented) */
    58 MMIO_REGION_BEGIN( 0xFF100000, PMM, "Performance monitoring" )
    59     LONG_PORT (0x004, PMCTR1H, PORT_MR, 0, "Performance counter 1 High" )  
    60     LONG_PORT (0x008, PMCTR1L, PORT_MR, 0, "Performance counter 1 Low" )  
    61     LONG_PORT (0x00C, PMCTR2H, PORT_MR, 0, "Performance counter 2 High" )  
    62     LONG_PORT (0x010, PMCTR2L, PORT_MR, 0, "Performance counter 2 Low" ) 
    63 MMIO_REGION_END
    65 /* User Break Controller (Page 717 [757] of sh7750h manual) */
    66 MMIO_REGION_BEGIN( 0xFF200000, UBC, "User Break Controller" )
    67     LONG_PORT( 0x000, BARA, PORT_MRW, UNDEFINED, "Break address A" )
    68     BYTE_PORT( 0x004, BAMRA, PORT_MRW, UNDEFINED, "Break address mask A" )
    69     WORD_PORT( 0x008, BBRA, PORT_MRW, 0, "Break bus cycle A" )
    70     LONG_PORT( 0x00C, BARB, PORT_MRW, UNDEFINED, "Break address B" )
    71     BYTE_PORT( 0x010, BAMRB, PORT_MRW, UNDEFINED, "Break address mask B" )
    72     WORD_PORT( 0x014, BBRB, PORT_MRW, 0, "Break bus cycle B" )
    73     LONG_PORT( 0x018, BDRB, PORT_MRW, UNDEFINED, "Break data B" )
    74     LONG_PORT( 0x01C, BDMRB, PORT_MRW, UNDEFINED, "Break data mask B" )
    75     WORD_PORT( 0x020, BRCR, PORT_MRW, 0, "Break control" )
    76 MMIO_REGION_END
    77 /* Bus State Controller (Page 293 [333] of sh7750h manual)
    78  * I/O Ports */
    79 MMIO_REGION_BEGIN( 0xFF800000, BSC, "Bus State Controller" )
    80     LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "Bus control 1" )
    81     WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "Bus control 2" )
    82     LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "Wait state control 1" )
    83     LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "Wait state control 2" )
    84     LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "Wait state control 3" )
    85     LONG_PORT( 0x014, MCR, PORT_MRW, 0, "Memory control register" )
    86     WORD_PORT( 0x018, PCR, PORT_MRW, 0, "PCMCIA control register" )
    87     WORD_PORT( 0x01C, RTCSR, PORT_MRW, 0, "Refresh timer control/status" )
    88     WORD_PORT( 0x020, RTCNT, PORT_MRW, 0, "Refresh timer counter" )
    89     WORD_PORT( 0x024, RTCOR, PORT_MRW, 0, "Refresh timer constant" )
    90     WORD_PORT( 0x028, RFCR, PORT_MRW, 0, "Refresh count" )
    91     LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" )
    92     WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" )
    93     LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" )
    94     WORD_PORT( 0x044, PDTRB, PORT_RW, UNDEFINED, "Port data register B" )
    95     WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" )
    96 MMIO_REGION_END
    98 /* DMA Controller (Page 457 [497] of sh7750h manual) */
    99 MMIO_REGION_BEGIN( 0xFFA00000, DMAC, "DMA Controller" )
   100     LONG_PORT( 0x000, SAR0, PORT_MRW, UNDEFINED, "DMA source address 0" )
   101     LONG_PORT( 0x004, DAR0, PORT_MRW, UNDEFINED, "DMA destination address 0" )
   102     LONG_PORT( 0x008, DMATCR0, PORT_MRW, UNDEFINED, "DMA transfer count 0" )
   103     LONG_PORT( 0x00C, CHCR0, PORT_MRW, 0, "DMA channel control 0" )
   104     LONG_PORT( 0x010, SAR1, PORT_MRW, UNDEFINED, "DMA source address 1" )
   105     LONG_PORT( 0x014, DAR1, PORT_MRW, UNDEFINED, "DMA destination address 1" )
   106     LONG_PORT( 0x018, DMATCR1, PORT_MRW, UNDEFINED, "DMA transfer count 1" )
   107     LONG_PORT( 0x01C, CHCR1, PORT_MRW, 0, "DMA channel control 1" )
   108     LONG_PORT( 0x020, SAR2, PORT_MRW, UNDEFINED, "DMA source address 2" )
   109     LONG_PORT( 0x024, DAR2, PORT_MRW, UNDEFINED, "DMA destination address 2" )
   110     LONG_PORT( 0x028, DMATCR2, PORT_MRW, UNDEFINED, "DMA transfer count 2" )
   111     LONG_PORT( 0x02C, CHCR2, PORT_MRW, 0, "DMA channel control 2" )
   112     LONG_PORT( 0x030, SAR3, PORT_MRW, UNDEFINED, "DMA source address 3" )
   113     LONG_PORT( 0x034, DAR3, PORT_MRW, UNDEFINED, "DMA destination address 3" )
   114     LONG_PORT( 0x038, DMATCR3, PORT_MRW, UNDEFINED, "DMA transfer count 3" )
   115     LONG_PORT( 0x03C, CHCR3, PORT_MRW, 0, "DMA channel control 3" )
   116     LONG_PORT( 0x040, DMAOR, PORT_MRW, 0, "DMA operation register" )
   117 MMIO_REGION_END
   119 /* Clock Pulse Generator (page 233 [273] of sh7750h manual) */
   120 MMIO_REGION_BEGIN( 0xFFC00000, CPG, "Clock Pulse Generator" )
   121     WORD_PORT( 0x000, FRQCR, PORT_MRW, UNDEFINED, "Frequency control" )
   122     BYTE_PORT( 0x004, STBCR, PORT_MRW, 0, "Standby control" )
   123     BYTE_PORT( 0x008, WTCNT, PORT_MRW, 0, "Watchdog timer counter" )
   124     BYTE_PORT( 0x00C, WTCSR, PORT_MRW, 0, "Watchdog timer control/status" )
   125     BYTE_PORT( 0x010, STBCR2, PORT_MRW, 0, "Standby control 2" )
   126 MMIO_REGION_END
   128 /* Real time clock (Page 253 [293] of sh7750h manual) */
   129 MMIO_REGION_BEGIN( 0xFFC80000, RTC, "Realtime Clock" )
   130     BYTE_PORT( 0x000, R64CNT, PORT_R, UNDEFINED, "64 Hz counter" )
   131     BYTE_PORT( 0x004, RSECCNT, PORT_MRW, UNDEFINED, "Second counter" )
   132     /* ... */
   133 MMIO_REGION_END
   135 /* Interrupt controller (Page 699 [739] of sh7750h manual) */
   136 MMIO_REGION_BEGIN( 0xFFD00000, INTC, "Interrupt Controller" )
   137     WORD_PORT( 0x000, ICR, PORT_MRW, 0x0000, "Interrupt control register" )
   138     WORD_PORT( 0x004, IPRA, PORT_MRW, 0x0000, "Interrupt priority register A" )
   139     WORD_PORT( 0x008, IPRB, PORT_MRW, 0x0000, "Interrupt priority register B" )
   140     WORD_PORT( 0x00C, IPRC, PORT_MRW, 0x0000, "Interrupt priority register C" )
   141     WORD_PORT( 0x010, IPRD, PORT_MRW, 0xDA74, "Interrupt priority register D" )
   142 MMIO_REGION_END
   144 /* Timer unit (Page 277 [317] of sh7750h manual) */
   145 MMIO_REGION_BEGIN( 0xFFD80000, TMU, "Timer Unit" )
   146     BYTE_PORT( 0x000, TOCR, PORT_MRW, 0x00, "Timer output control register" )
   147     BYTE_PORT( 0x004, TSTR, PORT_MRW, 0x00, "Timer start register" )
   148     LONG_PORT( 0x008, TCOR0, PORT_MRW, 0xFFFFFFFF, "Timer constant 0" )
   149     LONG_PORT( 0x00C, TCNT0, PORT_MRW, 0xFFFFFFFF, "Timer counter 0" )
   150     WORD_PORT( 0x010, TCR0, PORT_MRW, 0x0000, "Timer control 0" )
   151     LONG_PORT( 0x014, TCOR1, PORT_MRW, 0xFFFFFFFF, "Timer constant 1" )
   152     LONG_PORT( 0x018, TCNT1, PORT_MRW, 0xFFFFFFFF, "Timer counter 1" )
   153     WORD_PORT( 0x01C, TCR1, PORT_MRW, 0x0000, "Timer control 1" )
   154     LONG_PORT( 0x020, TCOR2, PORT_MRW, 0xFFFFFFFF, "Timer constant 2" )
   155     LONG_PORT( 0x024, TCNT2, PORT_MRW, 0xFFFFFFFF, "Timer counter 2" )
   156     WORD_PORT( 0x028, TCR2, PORT_MRW, 0x0000, "Timer control 2" )
   157     LONG_PORT( 0x02C, TCPR2, PORT_R, UNDEFINED, "Input capture register" )
   158 MMIO_REGION_END
   160 /* Serial channel (page 541 [581] of sh7750h manual) */
   161 MMIO_REGION_BEGIN( 0xFFE00000, SCI, "Serial Communication Interface" )
   162     BYTE_PORT( 0x000, SCSMR1, PORT_MRW, 0x00, "Serial mode register" )
   163     BYTE_PORT( 0x004, SCBRR1, PORT_MRW, 0xFF, "Bit rate register" )
   164     BYTE_PORT( 0x008, SCSCR1, PORT_MRW, 0x00, "Serial control register" )
   165     BYTE_PORT( 0x00C, SCTDR1, PORT_MRW, 0xFF, "Transmit data register" )
   166     BYTE_PORT( 0x010, SCSSR1, PORT_MRW, 0x84, "Serial status register" )
   167     BYTE_PORT( 0x014, SCRDR1, PORT_R, 0x00, "Receive data register" )
   168     BYTE_PORT( 0x01C, SCSPTR1, PORT_MRW, 0x00, "Serial port register" )
   169 MMIO_REGION_END
   171 MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" )
   172     WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" )
   173     BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" )
   174     WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" )
   175     BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" )
   176     WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)") 
   177     BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" )
   178     WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" )
   179     WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" )
   180     WORD_PORT( 0x020, SCSPTR2, PORT_MRW, 0x0000, "Serial port register (FIFO)" )
   181     WORD_PORT( 0x024, SCLSR2, PORT_MRW, 0x0000, "Line status register (FIFO)" )
   182 MMIO_REGION_END
   184 MMIO_REGION_LIST_BEGIN( sh4mmio )
   185     MMIO_REGION( MMU )
   186     MMIO_REGION( UBC )
   187     MMIO_REGION( BSC )
   188     MMIO_REGION( DMAC )
   189     MMIO_REGION( CPG )
   190     MMIO_REGION( RTC )
   191     MMIO_REGION( INTC )
   192     MMIO_REGION( TMU )
   193     MMIO_REGION( SCI )
   194     MMIO_REGION( SCIF )
   195     MMIO_REGION( PMM )
   196 MMIO_REGION_LIST_END
   198 /* mmucr register bits */
   199 #define MMUCR_AT   0x00000001 /* Address Translation enabled */
   200 #define MMUCR_TI   0x00000004 /* TLB invalidate (always read as 0) */
   201 #define MMUCR_SV   0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
   202 #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
   203 #define MMUCR_URC  0x0000FC00 /* UTLB access counter */
   204 #define MMUCR_URB  0x00FC0000 /* UTLB entry boundary */
   205 #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
   206 #define MMUCR_MASK 0xFCFCFF05
   207 #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
   209 #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
   211 /* ccr register bits */
   212 #define CCR_IIX    0x00008000 /* IC index enable */
   213 #define CCR_ICI    0x00000800 /* IC invalidation (always read as 0) */
   214 #define CCR_ICE    0x00000100 /* IC enable */
   215 #define CCR_OIX    0x00000080 /* OC index enable */
   216 #define CCR_ORA    0x00000020 /* OC RAM enable */
   217 #define CCR_OCI    0x00000008 /* OC invalidation (always read as 0) */
   218 #define CCR_CB     0x00000004 /* Copy-back (P1 area cache write mode) */
   219 #define CCR_WT     0x00000002 /* Write-through (P0,U0,P3 write mode) */
   220 #define CCR_OCE    0x00000001 /* OC enable */
   221 #define CCR_MASK   0x000089AF
   222 #define CCR_RMASK  0x000081A7 /* Read mask */
   224 #define MEM_OC_INDEX0   (CCR_ORA|CCR_OCE)
   225 #define MEM_OC_INDEX1   (CCR_ORA|CCR_OIX|CCR_OCE)
   227 #define PMCR_CLKF  0x0100
   228 #define PMCR_PMCLR 0x2000
   229 #define PMCR_PMST  0x4000
   230 #define PMCR_PMEN  0x8000
   232 /* MMU functions */
   233 void mmu_init(void);
   234 void mmu_set_cache_mode( int );
   235 void mmu_ldtlb(void);
   237 int32_t mmu_icache_addr_read( sh4addr_t addr );
   238 int32_t mmu_icache_data_read( sh4addr_t addr );
   239 int32_t mmu_itlb_addr_read( sh4addr_t addr );
   240 int32_t mmu_itlb_data_read( sh4addr_t addr );
   241 int32_t mmu_ocache_addr_read( sh4addr_t addr );
   242 int32_t mmu_ocache_data_read( sh4addr_t addr );
   243 int32_t mmu_utlb_addr_read( sh4addr_t addr );
   244 int32_t mmu_utlb_data_read( sh4addr_t addr );
   245 void mmu_icache_addr_write( sh4addr_t addr, uint32_t val );
   246 void mmu_icache_data_write( sh4addr_t addr, uint32_t val );
   247 void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val );
   248 void mmu_itlb_data_write( sh4addr_t addr, uint32_t val );
   249 void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val );
   250 void mmu_ocache_data_write( sh4addr_t addr, uint32_t val );
   251 void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val );
   252 void mmu_utlb_data_write( sh4addr_t addr, uint32_t val );
   255 #ifdef __cplusplus
   256 }
   257 #endif
   259 #endif
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