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lxdream.org :: lxdream/src/sh4/scif.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/scif.c
changeset 22:f0703013049f
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next23:1ec3acd0594d
author nkeynes
date Thu Dec 22 13:57:26 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Add basic save/load state methods
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     1 /**
     2  * $Id: scif.c,v 1.3 2005-12-22 13:57:26 nkeynes Exp $
     3  * SCIF (Serial Communication Interface with FIFO) implementation - part of the 
     4  * SH4 standard on-chip peripheral set. The SCIF is hooked up to the DCs
     5  * external serial port
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #include <glib.h>
    21 #include "dream.h"
    22 #include "mem.h"
    23 #include "sh4core.h"
    24 #include "sh4mmio.h"
    25 #include "intc.h"
    26 #include "clock.h"
    27 #include "serial.h"
    28 #include "modules.h"
    30 void SCIF_set_break(void);
    32 /************************* External serial interface ************************/
    34 /**
    35  * Note: serial_* operations are called from outside the SH4, and as such are
    36  * named relative to the external serial device. SCIF_* operations are only
    37  * called internally to the SH4 and so are named relative to the CPU.
    38  */
    40 /**
    41  * Storage space for inbound/outbound data blocks. It's a little more
    42  * convenient for serial consumers to be able to deal with block-sized pieces
    43  * rather than a byte at a time, even if it makes all this look rather
    44  * complicated.
    45  *
    46  * Currently there's no limit on the number of blocks that can be queued up.
    47  */
    48 typedef struct serial_data_block {
    49     uint32_t length;
    50     uint32_t offset;
    51     struct serial_data_block *next;
    52     char data[];
    53 } *serial_data_block_t;
    55 serial_data_block_t serial_recvq_head = NULL, serial_recvq_tail = NULL;
    56 serial_device_t serial_device = NULL;
    58 void serial_attach_device( serial_device_t dev ) 
    59 {
    60     if( serial_device != NULL )
    61 	serial_detach_device();
    62     serial_device = dev;
    63 }
    66 void serial_detach_device( void )
    67 {
    68     serial_device = NULL;
    69 }
    71 /**
    72  * Add a block of data to the serial receive queue. The data will be received
    73  * by the CPU at the appropriate baud rate.
    74  */
    75 void serial_transmit_data( char *data, int length ) {
    76     if( length == 0 )
    77 	return;
    78     serial_data_block_t block = 
    79 	g_malloc( sizeof( struct serial_data_block ) + length );
    80     block->length = length;
    81     block->offset = 0;
    82     block->next = NULL;
    83     memcpy( block->data, data, length );
    85     if( serial_recvq_head == NULL ) {
    86 	serial_recvq_head = serial_recvq_tail = block;
    87     } else {
    88 	serial_recvq_tail->next = block;
    89 	serial_recvq_tail = block;
    90     }
    91 }
    93 /**
    94  * Dequeue a byte from the serial input queue
    95  */
    96 static int serial_transmit_dequeue( ) {
    97     if( serial_recvq_head != NULL ) {
    98 	uint8_t val = serial_recvq_head->data[serial_recvq_head->offset++];
    99 	if( serial_recvq_head->offset >= serial_recvq_head->length ) {
   100 	    serial_data_block_t next = serial_recvq_head->next;
   101 	    g_free( serial_recvq_head );
   102 	    serial_recvq_head = next;
   103 	    if( next == NULL )
   104 		serial_recvq_tail = NULL;
   105 	}
   106 	return (int)(unsigned int)val;
   107     }
   108     return -1;
   110 }
   112 void serial_transmit_break() {
   113     SCIF_set_break();
   114 }
   116 /********************************* SCIF *************************************/
   118 #define FIFO_LENGTH 16
   119 #define FIFO_ARR_LENGTH (FIFO_LENGTH+1)
   121 /* Serial control register flags */
   122 #define SCSCR2_TIE  0x80
   123 #define SCSCR2_RIE  0x40
   124 #define SCSCR2_TE   0x20
   125 #define SCSCR2_RE   0x10
   126 #define SCSCR2_REIE 0x08
   127 #define SCSCR2_CKE 0x02
   129 #define IS_TRANSMIT_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_TIE)
   130 #define IS_RECEIVE_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RIE)
   131 #define IS_RECEIVE_ERROR_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & (SCSCR2_RIE|SCSCR2_REIE))
   132 /* Receive is enabled if the RE bit is set in SCSCR2, and the ORER bit is cleared in SCLSR2 */
   133 #define IS_RECEIVE_ENABLED() ( (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RE) && (MMIO_READ(SCIF,SCLSR2) & SCLSR2_ORER == 0) )
   134 /* Transmit is enabled if the TE bit is set in SCSCR2 */
   135 #define IS_TRANSMIT_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_TE)
   136 #define IS_LOOPBACK_ENABLED() (MMIO_READ(SCIF,SCFCR2) & SCFCR2_LOOP)
   138 /* Serial status register flags */
   139 #define SCFSR2_ER   0x80
   140 #define SCFSR2_TEND 0x40
   141 #define SCFSR2_TDFE 0x20
   142 #define SCFSR2_BRK  0x10
   143 #define SCFSR2_RDF  0x02
   144 #define SCFSR2_DR   0x01
   146 /* FIFO control register flags */
   147 #define SCFCR2_MCE   0x08
   148 #define SCFCR2_TFRST 0x04
   149 #define SCFCR2_RFRST 0x02
   150 #define SCFCR2_LOOP  0x01
   152 /* Line Status Register */
   153 #define SCLSR2_ORER 0x01
   155 struct SCIF_fifo {
   156     int head;
   157     int tail;
   158     int trigger;
   159     uint8_t data[FIFO_ARR_LENGTH];
   160 };
   162 int SCIF_recvq_triggers[4] = {1, 4, 8, 14};
   163 struct SCIF_fifo SCIF_recvq = {0,0,1};
   165 int SCIF_sendq_triggers[4] = {8, 4, 2, 1};
   166 struct SCIF_fifo SCIF_sendq = {0,0,8};
   168 /**
   169  * Flag to indicate if data was received (ie added to the receive queue)
   170  * during the last SCIF clock tick. Used to determine when to set the DR
   171  * flag.
   172  */
   173 gboolean SCIF_rcvd_last_tick = FALSE;
   175 void SCIF_save_state( FILE *f ) 
   176 {
   177     fwrite( &SCIF_recvq, sizeof(SCIF_recvq), 1, f );
   178     fwrite( &SCIF_sendq, sizeof(SCIF_sendq), 1, f );
   179     fwrite( &SCIF_rcvd_last_tick, sizeof(gboolean), 1, f );
   181 }
   183 int SCIF_load_state( FILE *f ) 
   184 {
   185     fread( &SCIF_recvq, sizeof(SCIF_recvq), 1, f );
   186     fread( &SCIF_sendq, sizeof(SCIF_sendq), 1, f );
   187     fread( &SCIF_rcvd_last_tick, sizeof(gboolean), 1, f );
   188     return 0;
   189 }
   191 static inline uint8_t SCIF_recvq_size( ) 
   192 {
   193     int val = SCIF_recvq.tail - SCIF_recvq.head;
   194     if( val < 0 ) {
   195 	val = FIFO_ARR_LENGTH - SCIF_recvq.head + SCIF_recvq.tail;
   196     }
   197     return val;
   198 }
   200 int SCIF_recvq_dequeue( gboolean clearFlags )
   201 {
   202     uint8_t result;
   203     uint32_t tmp, length;
   204     if( SCIF_recvq.head == SCIF_recvq.tail )
   205 	return -1; /* No data */
   206     result = SCIF_recvq.data[SCIF_recvq.head++];
   207     if( SCIF_recvq.head > FIFO_LENGTH )
   208 	SCIF_recvq.head = 0;
   210     /* Update data count register */
   211     tmp = MMIO_READ( SCIF, SCFDR2 ) & 0xF0;
   212     length = SCIF_recvq_size();
   213     MMIO_WRITE( SCIF, SCFDR2, tmp | length );
   215     /* Clear flags (if requested ) */
   216     if( clearFlags && length < SCIF_recvq.trigger ) {
   217 	tmp = SCFSR2_RDF;
   218 	if( length == 0 )
   219 	    tmp |= SCFSR2_DR;
   220 	tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp);
   221 	MMIO_WRITE( SCIF, SCFSR2, tmp );
   222 	/* If both flags are cleared, clear the interrupt as well */
   223 	if( (tmp & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() )
   224 	    intc_clear_interrupt( INT_SCIF_RXI );
   225     }
   227     return (int)(unsigned int)result;
   228 }
   230 gboolean SCIF_recvq_enqueue( uint8_t value )
   231 {
   232     uint32_t tmp, length;
   233     int newpos = SCIF_recvq.tail + 1;
   234     if( newpos > FIFO_LENGTH )
   235 	newpos = 0;
   236     if( newpos == SCIF_recvq.head ) {
   237 	/* FIFO full - set ORER and discard the value */
   238 	MMIO_WRITE( SCIF, SCLSR2, SCLSR2_ORER );
   239 	if( IS_RECEIVE_ERROR_IRQ_ENABLED() )
   240 	    intc_raise_interrupt( INT_SCIF_ERI );
   241 	return FALSE;
   242     }
   243     SCIF_recvq.data[SCIF_recvq.tail] = value;
   245     /* Update data count register */
   246     tmp = MMIO_READ( SCIF, SCFDR2 ) & 0xF0;
   247     length = SCIF_recvq_size();
   248     MMIO_WRITE( SCIF, SCFDR2, tmp | length );
   250     /* Update status register */
   251     tmp = MMIO_READ( SCIF, SCFSR2 );
   252     if( length >= SCIF_recvq.trigger ) {
   253 	tmp |= SCFSR2_RDF;
   254 	if( IS_RECEIVE_IRQ_ENABLED() ) 
   255 	    intc_raise_interrupt( INT_SCIF_RXI );
   256     }
   257     MMIO_WRITE( SCIF, SCFSR2, tmp );
   258     return TRUE;
   259 }
   262 /**
   263  * Reset the receive FIFO to its initial state. Manual is unclear as to
   264  * whether this also clears flags/interrupts, but we're assuming here that
   265  * it does until proven otherwise.
   266  */
   267 void SCIF_recvq_clear( void ) 
   268 {
   269     SCIF_recvq.head = SCIF_recvq.tail = 0;
   270     MMIO_WRITE( SCIF, SCFDR2, MMIO_READ( SCIF, SCFDR2 ) & 0xF0 );
   271     MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) & ~(SCFSR2_DR|SCFSR2_RDF) );
   272     if( IS_RECEIVE_IRQ_ENABLED() )
   273 	intc_clear_interrupt( INT_SCIF_RXI );
   274 }
   276 static inline uint8_t SCIF_sendq_size( ) 
   277 {
   278     int val = SCIF_sendq.tail - SCIF_sendq.head;
   279     if( val < 0 ) {
   280 	val = FIFO_ARR_LENGTH - SCIF_sendq.head + SCIF_sendq.tail;
   281     }
   282     return val;
   283 }
   285 /**
   286  * Dequeue one byte from the SCIF transmit queue (ie transmit the byte),
   287  * updating all status flags as required.
   288  * @return The byte dequeued, or -1 if the queue is empty.
   289  */
   290 int SCIF_sendq_dequeue( )
   291 {
   292     uint8_t result;
   293     uint32_t tmp, length;
   294     if( SCIF_sendq.head == SCIF_sendq.tail )
   295 	return -1; /* No data */
   297     /* Update queue head pointer */
   298     result = SCIF_sendq.data[SCIF_sendq.head++];
   299     if( SCIF_sendq.head > FIFO_LENGTH )
   300 	SCIF_sendq.head = 0;
   302     /* Update data count register */
   303     tmp = MMIO_READ( SCIF, SCFDR2 ) & 0x0F;
   304     length = SCIF_sendq_size();
   305     MMIO_WRITE( SCIF, SCFDR2, tmp | (length << 8) );
   307     /* Update status register */
   308     if( length <= SCIF_sendq.trigger ) {
   309 	tmp = MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TDFE;
   310 	if( length == 0 )
   311 	    tmp |= SCFSR2_TEND; /* Transmission ended - no data waiting */
   312 	if( IS_TRANSMIT_IRQ_ENABLED() ) 
   313 	    intc_raise_interrupt( INT_SCIF_TXI );
   314 	MMIO_WRITE( SCIF, SCFSR2, tmp );
   315     }
   316     return (int)(unsigned int)result;
   317 }
   319 /**
   320  * Enqueue a single byte in the SCIF transmit queue. If the queue is full,
   321  * the value will be discarded.
   322  * @param value to be queued.
   323  * @param clearFlags TRUE if the TEND/TDFE flags should be cleared
   324  *   if the queue exceeds the trigger level. (According to the manual,
   325  *   DMAC writes will clear the flag, whereas regular SH4 writes do NOT
   326  *   automatically clear it. Go figure).
   327  * @return gboolean TRUE if the value was queued, FALSE if the queue was
   328  *   full.
   329  */
   330 gboolean SCIF_sendq_enqueue( uint8_t value, gboolean clearFlags )
   331 {
   332     uint32_t tmp, length;
   333     int newpos = SCIF_sendq.tail + 1;
   334     if( newpos > FIFO_LENGTH )
   335 	newpos = 0;
   336     if( newpos == SCIF_sendq.head ) {
   337 	/* FIFO full - discard */
   338 	return FALSE;
   339     }
   340     SCIF_sendq.data[SCIF_sendq.tail] = value;
   341     SCIF_sendq.tail = newpos;
   343     /* Update data count register */
   344     tmp = MMIO_READ( SCIF, SCFDR2 ) & 0x0F;
   345     length = SCIF_sendq_size();
   346     MMIO_WRITE( SCIF, SCFDR2, tmp | (length << 8) );
   348     /* Update flags if requested */
   349     if( clearFlags ) {
   350 	tmp = SCFSR2_TEND;
   351 	if( length > SCIF_sendq.trigger ) {
   352 	    tmp |= SCFSR2_TDFE;
   353 	    if( IS_TRANSMIT_IRQ_ENABLED() )
   354 		intc_clear_interrupt( INT_SCIF_TXI );
   355 	}
   356 	tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp);
   357 	MMIO_WRITE( SCIF, SCFSR2, tmp );
   358     }
   359     return TRUE;
   360 }
   362 void SCIF_sendq_clear( void ) 
   363 {
   364     SCIF_sendq.head = SCIF_sendq.tail = 0;
   365     MMIO_WRITE( SCIF, SCFDR2, MMIO_READ( SCIF, SCFDR2 ) & 0x0F );
   366     MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TEND | SCFSR2_TDFE );
   367     if( IS_TRANSMIT_IRQ_ENABLED() ) {
   368 	intc_raise_interrupt( INT_SCIF_TXI );
   369     }
   370 }
   372 /**
   373  * Update the SCFSR2 status register with the given mask (ie clear any values
   374  * that are set to 0 in the mask. According to a strict reading of the doco
   375  * though, the bits will only actually clear if the flag state is no longer
   376  * true, so we need to recheck everything...
   377  */
   378 void SCIF_update_status( uint32_t mask )
   379 {
   380     uint32_t value = MMIO_READ( SCIF, SCFSR2 );
   381     uint32_t result = value & mask;
   382     uint32_t sendq_size = SCIF_sendq_size();
   383     uint32_t recvq_size = SCIF_recvq_size();
   385     if( sendq_size != 0 )
   386 	result |= SCFSR2_TEND;
   388     if( sendq_size <= SCIF_sendq.trigger )
   389 	result |= SCFSR2_TDFE;
   390     else if( result & SCFSR2_TDFE == 0 && IS_TRANSMIT_IRQ_ENABLED() )
   391 	intc_clear_interrupt( INT_SCIF_TXI );
   393     if( recvq_size >= SCIF_recvq.trigger )
   394 	result |= SCFSR2_RDF;
   395     if( (value & SCFSR2_DR) != 0 && (result & SCFSR2_DR) == 0 &&
   396 	recvq_size != 0 )
   397 	result |= SCFSR2_DR;
   398     if( (result & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() )
   399 	intc_clear_interrupt( INT_SCIF_RXI );
   401     if( IS_RECEIVE_ERROR_IRQ_ENABLED() ) {
   402 	if( (result & SCFSR2_BRK) == 0 )
   403 	    intc_clear_interrupt( INT_SCIF_BRI );
   404 	if( (result & SCFSR2_ER) == 0 && 
   405 	    (MMIO_READ( SCIF, SCLSR2 ) & SCLSR2_ORER) == 0 )
   406 	    intc_clear_interrupt( INT_SCIF_ERI );
   407     }
   408 }
   410 /**
   411  * Set the break detected flag
   412  */
   413 void SCIF_set_break( void ) 
   414 {
   415     MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_BRK );
   416     if( IS_RECEIVE_ERROR_IRQ_ENABLED() )
   417 	intc_raise_interrupt( INT_SCIF_BRI );
   418 }
   420 const static int SCIF_CLOCK_MULTIPLIER[4] = {1, 4, 16, 64};
   422 /**
   423  * Calculate the current line speed.
   424  */
   425 void SCIF_update_line_speed( void )
   426 {
   427     /* If CKE1 is set, use the external clock as a base */
   428     if( MMIO_READ( SCIF, SCSCR2 ) & SCSCR2_CKE ) {
   431     } else {
   433 	/* Otherwise, SH4 peripheral clock divided by n */
   434 	int mult = SCIF_CLOCK_MULTIPLIER[MMIO_READ( SCIF, SCSMR2 ) & 0x03];
   436 	/* Then process the bitrate register */
   437 	int bbr = MMIO_READ( SCIF, SCBRR2 ) & 0xFF;
   439 	int baudrate = sh4_peripheral_freq / (32 * mult * (bbr+1) );
   441 	if( serial_device != NULL && serial_device->set_line_speed != NULL )
   442 	    serial_device->set_line_speed( baudrate );
   443 	INFO( "SCIF baud rate set to %d", baudrate );
   444 	/*
   445 	  clock_set_tick_rate( CLOCK_SCIF, baudrate / 10 );
   446 	*/
   447     }
   448 }
   450 int32_t mmio_region_SCIF_read( uint32_t reg )
   451 {
   452     switch( reg ) {
   453     case SCFRDR2: /* Receive data */
   454 	return SCIF_recvq_dequeue(FALSE);
   455     default:
   456 	return MMIO_READ( SCIF, reg );
   457     }
   458 }
   460 void mmio_region_SCIF_write( uint32_t reg, uint32_t val ) 
   461 {
   462     uint32_t tmp;
   463     switch( reg ) {
   464     case SCSMR2: /* Serial mode register */
   465 	/* Bit 6 => 0 = 8-bit, 1 = 7-bit
   466 	 * Bit 5 => 0 = Parity disabled, 1 = parity enabled
   467 	 * Bit 4 => 0 = Even parity, 1 = Odd parity
   468 	 * Bit 3 => 0 = 1 stop bit, 1 = 2 stop bits
   469 	 * Bits 0-1 => Clock select 00 = P, 01 = P/4, 10 = P/16, 11 = P/64
   470 	 */
   471 	val &= 0x007B;
   472 	if( serial_device != NULL ) {
   473 	    serial_device->set_line_params( val );
   474 	}
   475 	tmp = MMIO_READ( SCIF, SCSMR2 );
   476 	if( tmp & 0x03 != val & 0x03 ) {
   477 	    /* Clock change */
   478 	    SCIF_update_line_speed( );
   479 	}
   480 	/* Save for later read-back */
   481 	MMIO_WRITE( SCIF, SCSMR2, val );
   482 	break;
   483     case SCBRR2: /* Bit rate register */
   484 	MMIO_WRITE( SCIF, SCBRR2, val );
   485 	SCIF_update_line_speed( );
   486 	break;
   487     case SCSCR2: /* Serial control register */
   488 	/* Bit 7 => Transmit-FIFO-data-empty interrupt enabled 
   489 	 * Bit 6 => Receive-data-full interrupt enabled 
   490 	 * Bit 5 => Transmit enable 
   491 	 * Bit 4 => Receive enable 
   492 	 * Bit 3 => Receive-error/break interrupt enabled
   493 	 * Bit 1 => Clock enable
   494 	 */
   495 	val &= 0x00FA;
   496 	/* Clear any interrupts that just became disabled */
   497 	if( val & SCSCR2_TIE == 0 )
   498 	    intc_clear_interrupt( INT_SCIF_TXI );
   499 	if( val & SCSCR2_RIE == 0 )
   500 	    intc_clear_interrupt( INT_SCIF_RXI );
   501 	if( val & (SCSCR2_RIE|SCSCR2_REIE) == 0 ) {
   502 	    intc_clear_interrupt( INT_SCIF_ERI );
   503 	    intc_clear_interrupt( INT_SCIF_BRI );
   504 	}
   506 	MMIO_WRITE( SCIF, reg, val );
   507 	break;
   508     case SCFTDR2: /* Transmit FIFO data register */
   509 	SCIF_sendq_enqueue( val, FALSE );
   510 	break;
   511     case SCFSR2: /* Serial status register */
   512 	/* Bits 12-15 Parity error count
   513 	 * Bits 8-11 Framing erro count 
   514 	 * Bit 7 - Receive error
   515 	 * Bit 6 - Transmit end
   516 	 * Bit 5 - Transmit FIFO data empty
   517 	 * Bit 4 - Break detect
   518 	 * Bit 3 - Framing error
   519 	 * Bit 2 - Parity error
   520 	 * Bit 1 - Receive FIFO data full
   521 	 * Bit 0 - Receive data ready
   522 	 */
   523 	/* Clear off any flags/interrupts that are being set to 0 */
   524 	SCIF_update_status( val );
   525 	break;
   526     case SCFCR2: /* FIFO control register */
   527 	val &= 0x0F;
   528 	SCIF_recvq.trigger = SCIF_recvq_triggers[val >> 6];
   529 	SCIF_sendq.trigger = SCIF_sendq_triggers[(val >> 4) & 0x03];
   530 	if( val & SCFCR2_TFRST ) {
   531 	    SCIF_sendq_clear();
   532 	}
   533 	if( val & SCFCR2_RFRST ) {
   534 	    SCIF_recvq_clear();
   535 	}
   537 	MMIO_WRITE( SCIF, reg, val );
   538 	break;
   539     case SCSPTR2: /* Serial Port Register */
   540 	MMIO_WRITE( SCIF, reg, val );
   541 	/* NOT IMPLEMENTED */
   542 	WARN( "SCSPTR2 not implemented: Write %08X", val );
   543 	break;
   544     case SCLSR2:
   545 	val = val & SCLSR2_ORER;
   546 	if( val == 0 ) {
   547 	    MMIO_WRITE( SCIF, SCLSR2, val );
   548 	    if( (MMIO_READ( SCIF, SCFSR2 ) & SCFSR2_ER) == 0 &&
   549 		IS_RECEIVE_ERROR_IRQ_ENABLED() ) 
   550 		intc_clear_interrupt( INT_SCIF_ERI );
   551 	}
   553 	break;
   554     }
   555 }
   557 /**
   558  * Actions for a single tick of the serial clock, defined as the transmission
   559  * time of a single frame.
   560  *
   561  * If transmit queue is non-empty:
   562  *    Transmit one byte and remove from queue
   563  * If input receive source is non-empty:
   564  *    Transfer one byte to the receive queue (if queue is full, byte is lost)
   565  * If recvq is non-empty, less than the trigger level, and no data has been
   566  *    received in the last 2 ticks (including this one), set the DR flag and
   567  *    IRQ if appropriate.
   568  */
   569 void SCIF_clock_tick( void ) 
   570 {
   571     gboolean rcvd = FALSE;
   573     if( IS_LOOPBACK_ENABLED() ) {
   574 	if( IS_TRANSMIT_ENABLED() ) {
   575 	    int val = SCIF_sendq_dequeue();
   576 	    if( val != -1 && IS_RECEIVE_ENABLED() ) {
   577 		SCIF_recvq_enqueue( val );
   578 		rcvd = TRUE;
   579 	    }
   580 	}
   581     } else {
   582 	if( IS_TRANSMIT_ENABLED() ) {
   583 	    int val = SCIF_sendq_dequeue();
   584 	    if( val != -1 && serial_device != NULL && 
   585 		serial_device->receive_data != NULL ) {
   586 		serial_device->receive_data( val );
   587 	    }
   588 	}
   590 	if( IS_RECEIVE_ENABLED() ) {
   591 	    int val = serial_transmit_dequeue();
   592 	    if( val != -1 ) {
   593 		SCIF_recvq_enqueue( val );
   594 		rcvd = TRUE;
   595 	    }
   596 	}
   597     }
   599     /* Check if we need to set the DR flag */
   600     if( !rcvd && !SCIF_rcvd_last_tick &&
   601 	SCIF_recvq.head != SCIF_recvq.tail &&
   602 	SCIF_recvq_size() < SCIF_recvq.trigger ) {
   603 	uint32_t tmp = MMIO_READ( SCIF, SCFSR2 );
   604 	if( tmp & SCFSR2_DR == 0 ) {
   605 	    MMIO_WRITE( SCIF, SCFSR2, tmp | SCFSR2_DR );
   606 	    if( IS_RECEIVE_IRQ_ENABLED() )
   607 		intc_raise_interrupt( INT_SCIF_RXI );
   608 	}
   609     }
   610     SCIF_rcvd_last_tick = rcvd;
   611 }
.