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filename src/sh4/sh4mmio.c
changeset 19:9da7a8e38f9d
prev10:c898b37506e0
next23:1ec3acd0594d
author nkeynes
date Thu Dec 22 13:57:26 2005 +0000 (18 years ago)
permissions -rw-r--r--
last change Add basic save/load state methods
view annotate diff log raw 
     1 #include "dream.h"

     2 #include "mem.h"

     3 #include "clock.h"

     4 #include "sh4core.h"

     5 #include "sh4mmio.h"

     6 #define MMIO_IMPL

     7 #include "sh4mmio.h"

     8 

     9 /********************************* MMU *************************************/

    10 

    11 MMIO_REGION_READ_STUBFN( MMU )

    12 

    13 #define OCRAM_START (0x1C000000>>PAGE_BITS)

    14 #define OCRAM_END   (0x20000000>>PAGE_BITS)

    15 

    16 static char *cache = NULL;

    17 

    18 void mmio_region_MMU_write( uint32_t reg, uint32_t val )

    19 {

    20     switch(reg) {

    21         case CCR:

    22             mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );

    23             INFO( "Cache mode set to %08X", val );

    24             break;

    25         default:

    26             break;

    27     }

    28     MMIO_WRITE( MMU, reg, val );

    29 }

    30 

    31 

    32 void mmu_init() 

    33 {

    34     cache = mem_alloc_pages(2);

    35 }

    36 

    37 void mmu_set_cache_mode( int mode )

    38 {

    39     uint32_t i;

    40     switch( mode ) {

    41         case MEM_OC_INDEX0: /* OIX=0 */

    42             for( i=OCRAM_START; i<OCRAM_END; i++ )

    43                 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));

    44             break;

    45         case MEM_OC_INDEX1: /* OIX=1 */

    46             for( i=OCRAM_START; i<OCRAM_END; i++ )

    47                 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));

    48             break;

    49         default: /* disabled */

    50             for( i=OCRAM_START; i<OCRAM_END; i++ )

    51                 page_map[i] = NULL;

    52             break;

    53     }

    54 }

    55 

    56 

    57 /********************************* BSC *************************************/

    58 

    59 uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;

    60 uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;

    61 uint32_t bsc_output = 0, bsc_input = 0x0300;

    62 

    63 void bsc_out( int output, int mask )

    64 {

    65     /* Go figure... The BIOS won't start without this mess though */

    66     if( ((output | (~mask)) & 0x03) == 3 ) {

    67         bsc_output |= 0x03;

    68     } else {

    69         bsc_output &= ~0x03;

    70     }

    71 }

    72 

    73 void mmio_region_BSC_write( uint32_t reg, uint32_t val )

    74 {

    75     int i;

    76     switch( reg ) {

    77         case PCTRA:

    78             bsc_input_mask_lo = bsc_output_mask_lo = 0;

    79             for( i=0; i<16; i++ ) {

    80                 int bits = (val >> (i<<1)) & 0x03;

    81                 if( bits == 2 ) bsc_input_mask_lo |= (1<<i);

    82                 else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);

    83             }

    84             bsc_output = (bsc_output&0x000F0000) |

    85                 (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);

    86             bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),

    87                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );

    88             break;

    89         case PCTRB:

    90             bsc_input_mask_hi = bsc_output_mask_hi = 0;

    91             for( i=0; i<4; i++ ) {

    92                 int bits = (val >> (i>>1)) & 0x03;

    93                 if( bits == 2 ) bsc_input_mask_hi |= (1<<i);

    94                 else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);

    95             }

    96             bsc_output = (bsc_output&0xFFFF) |

    97                 ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);

    98             break;

    99         case PDTRA:

   100             bsc_output = (bsc_output&0x000F0000) |

   101                 (val & bsc_output_mask_lo );

   102             bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),

   103                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );

   104             break;

   105         case PDTRB:

   106             bsc_output = (bsc_output&0xFFFF) |

   107                 ( (val & bsc_output_mask_hi)<<16 );

   108             break;

   109     }

   110     WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",

   111           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );

   112     MMIO_WRITE( BSC, reg, val );

   113 }

   114 

   115 int32_t mmio_region_BSC_read( uint32_t reg )

   116 {

   117     int32_t val;

   118     switch( reg ) {

   119         case PDTRA:

   120             val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);

   121             break;

   122         case PDTRB:

   123             val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);

   124             break;

   125         default:

   126             val = MMIO_READ( BSC, reg );

   127     }

   128     WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",

   129           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );

   130     return val;

   131 }

   132 

   133 /********************************* UBC *************************************/

   134 

   135 MMIO_REGION_STUBFNS( UBC )

   136 

   137 /********************************* CPG *************************************/

   138 

   139 uint32_t sh4_freq = SH4_BASE_RATE;

   140 uint32_t sh4_bus_freq = SH4_BASE_RATE;

   141 uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;

   142 

   143 

   144 MMIO_REGION_STUBFNS( CPG )

   145 

   146 /********************************* DMAC *************************************/

   147 

   148 MMIO_REGION_STUBFNS( DMAC )

   149 

   150 /********************************** RTC *************************************/

   151 

   152 MMIO_REGION_STUBFNS( RTC )

   153 

   154 /********************************** TMU *************************************/

   155 

   156 int timer_divider[3] = {16,16,16};

   157 MMIO_REGION_READ_DEFFN( TMU )

   158 

   159 int get_timer_div( int val )

   160 {

   161     switch( val & 0x07 ) {

   162         case 0: return 16; /* assume peripheral clock is IC/4 */

   163         case 1: return 64;

   164         case 2: return 256;

   165         case 3: return 1024;

   166         case 4: return 4096;

   167     }

   168     return 1;

   169 }

   170 

   171 void mmio_region_TMU_write( uint32_t reg, uint32_t val )

   172 {

   173     switch( reg ) {

   174         case TCR0:

   175             timer_divider[0] = get_timer_div(val);

   176             break;

   177         case TCR1:

   178             timer_divider[1] = get_timer_div(val);

   179             break;

   180         case TCR2:

   181             timer_divider[2] = get_timer_div(val);

   182             break;

   183     }

   184     MMIO_WRITE( TMU, reg, val );

   185 }

   186 

   187 void run_timers( int cycles )

   188 {

   189     int tcr = MMIO_READ( TMU, TSTR );

   190     cycles *= 16;

   191     if( tcr & 0x01 ) {

   192         int count = cycles / timer_divider[0];

   193         int *val = MMIO_REG( TMU, TCNT0 );

   194         if( *val < count ) {

   195             MMIO_READ( TMU, TCR0 ) |= 0x100;

   196             /* interrupt goes here */

   197             count -= *val;

   198             *val = MMIO_READ( TMU, TCOR0 ) - count;

   199         } else {

   200             *val -= count;

   201         }

   202     }

   203     if( tcr & 0x02 ) {

   204         int count = cycles / timer_divider[1];

   205         int *val = MMIO_REG( TMU, TCNT1 );

   206         if( *val < count ) {

   207             MMIO_READ( TMU, TCR1 ) |= 0x100;

   208             /* interrupt goes here */

   209             count -= *val;

   210             *val = MMIO_READ( TMU, TCOR1 ) - count;

   211         } else {

   212             *val -= count;

   213         }

   214     }

   215     if( tcr & 0x04 ) {

   216         int count = cycles / timer_divider[2];

   217         int *val = MMIO_REG( TMU, TCNT2 );

   218         if( *val < count ) {

   219             MMIO_READ( TMU, TCR2 ) |= 0x100;

   220             /* interrupt goes here */

   221             count -= *val;

   222             *val = MMIO_READ( TMU, TCOR2 ) - count;

   223         } else {

   224             *val -= count;

   225         }

   226     }

   227 }

   228 

   229 /********************************** SCI *************************************/

   230 

   231 MMIO_REGION_STUBFNS( SCI )

   232
.