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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 352:f0df7a6d4703
prev337:cdd757aa8e8c
next373:0ac2ac96a4c5
author nkeynes
date Sun Feb 11 10:09:32 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Bug 27: Implement opengl framebuffer objects
Rewrite much of the final video output stage. Now uses generic "render
buffers", implemented on GL using framebuffer objects + textures.
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     1 /**
     2  * $Id: pvr2.c,v 1.44 2007-02-11 10:09:32 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "eventq.h"
    22 #include "display.h"
    23 #include "mem.h"
    24 #include "asic.h"
    25 #include "clock.h"
    26 #include "pvr2/pvr2.h"
    27 #include "sh4/sh4core.h"
    28 #define MMIO_IMPL
    29 #include "pvr2/pvr2mmio.h"
    31 char *video_base;
    33 #define MAX_RENDER_BUFFERS 4
    35 #define HPOS_PER_FRAME 0
    36 #define HPOS_PER_LINECOUNT 1
    38 static void pvr2_init( void );
    39 static void pvr2_reset( void );
    40 static uint32_t pvr2_run_slice( uint32_t );
    41 static void pvr2_save_state( FILE *f );
    42 static int pvr2_load_state( FILE *f );
    43 static void pvr2_update_raster_posn( uint32_t nanosecs );
    44 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
    45 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
    46 static render_buffer_t pvr2_next_render_buffer( );
    47 uint32_t pvr2_get_sync_status();
    49 void pvr2_display_frame( void );
    51 static int output_colour_formats[] = { COLFMT_ARGB1555, COLFMT_RGB565, COLFMT_RGB888, COLFMT_ARGB8888 };
    53 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    54 					pvr2_run_slice, NULL,
    55 					pvr2_save_state, pvr2_load_state };
    58 display_driver_t display_driver = NULL;
    60 struct pvr2_state {
    61     uint32_t frame_count;
    62     uint32_t line_count;
    63     uint32_t line_remainder;
    64     uint32_t cycles_run; /* Cycles already executed prior to main time slice */
    65     uint32_t irq_hpos_line;
    66     uint32_t irq_hpos_line_count;
    67     uint32_t irq_hpos_mode;
    68     uint32_t irq_hpos_time_ns; /* Time within the line */
    69     uint32_t irq_vpos1;
    70     uint32_t irq_vpos2;
    71     uint32_t odd_even_field; /* 1 = odd, 0 = even */
    72     gboolean palette_changed; /* TRUE if palette has changed since last render */
    73     gchar *save_next_render_filename;
    74     /* timing */
    75     uint32_t dot_clock;
    76     uint32_t total_lines;
    77     uint32_t line_size;
    78     uint32_t line_time_ns;
    79     uint32_t vsync_lines;
    80     uint32_t hsync_width_ns;
    81     uint32_t front_porch_ns;
    82     uint32_t back_porch_ns;
    83     uint32_t retrace_start_line;
    84     uint32_t retrace_end_line;
    85     gboolean interlaced;
    86 } pvr2_state;
    88 render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
    89 int render_buffer_count = 0;
    91 /**
    92  * Event handler for the hpos callback
    93  */
    94 static void pvr2_hpos_callback( int eventid ) {
    95     asic_event( eventid );
    96     pvr2_update_raster_posn(sh4r.slice_cycle);
    97     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
    98 	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
    99 	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   100 	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   101 	}
   102     }
   103     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1, 
   104 				  pvr2_state.irq_hpos_time_ns );
   105 }
   107 /**
   108  * Event handler for the scanline callbacks. Fires the corresponding
   109  * ASIC event, and resets the timer for the next field.
   110  */
   111 static void pvr2_scanline_callback( int eventid ) {
   112     asic_event( eventid );
   113     pvr2_update_raster_posn(sh4r.slice_cycle);
   114     if( eventid == EVENT_SCANLINE1 ) {
   115 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
   116     } else {
   117 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
   118     }
   119 }
   121 static void pvr2_init( void )
   122 {
   123     int i;
   124     register_io_region( &mmio_region_PVR2 );
   125     register_io_region( &mmio_region_PVR2PAL );
   126     register_io_region( &mmio_region_PVR2TA );
   127     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
   128     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
   129     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
   130     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
   131     texcache_init();
   132     pvr2_reset();
   133     pvr2_ta_reset();
   134     pvr2_state.save_next_render_filename = NULL;
   135     for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
   136 	render_buffers[i] = NULL;
   137     }
   138     render_buffer_count = 0;
   139 }
   141 static void pvr2_reset( void )
   142 {
   143     pvr2_state.line_count = 0;
   144     pvr2_state.line_remainder = 0;
   145     pvr2_state.cycles_run = 0;
   146     pvr2_state.irq_vpos1 = 0;
   147     pvr2_state.irq_vpos2 = 0;
   148     pvr2_state.dot_clock = PVR2_DOT_CLOCK;
   149     pvr2_state.back_porch_ns = 4000;
   150     pvr2_state.palette_changed = FALSE;
   151     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
   152     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
   153     mmio_region_PVR2_write( YUV_ADDR, 0 );
   154     mmio_region_PVR2_write( YUV_CFG, 0 );
   156     pvr2_ta_init();
   157     texcache_flush();
   158 }
   160 static void pvr2_save_state( FILE *f )
   161 {
   162     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
   163     pvr2_ta_save_state( f );
   164     pvr2_yuv_save_state( f );
   165 }
   167 static int pvr2_load_state( FILE *f )
   168 {
   169     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   170 	return 1;
   171     if( pvr2_ta_load_state(f) ) {
   172 	return 1;
   173     }
   174     return pvr2_yuv_load_state(f);
   175 }
   177 /**
   178  * Update the current raster position to the given number of nanoseconds,
   179  * relative to the last time slice. (ie the raster will be adjusted forward
   180  * by nanosecs - nanosecs_already_run_this_timeslice)
   181  */
   182 static void pvr2_update_raster_posn( uint32_t nanosecs )
   183 {
   184     uint32_t old_line_count = pvr2_state.line_count;
   185     if( pvr2_state.line_time_ns == 0 ) {
   186 	return; /* do nothing */
   187     }
   188     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
   189     pvr2_state.cycles_run = nanosecs;
   190     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
   191 	pvr2_state.line_count ++;
   192 	pvr2_state.line_remainder -= pvr2_state.line_time_ns;
   193     }
   195     if( pvr2_state.line_count >= pvr2_state.total_lines ) {
   196 	pvr2_state.line_count -= pvr2_state.total_lines;
   197 	if( pvr2_state.interlaced ) {
   198 	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
   199 	}
   200     }
   201     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
   202 	(old_line_count < pvr2_state.retrace_end_line ||
   203 	 old_line_count > pvr2_state.line_count) ) {
   204 	pvr2_state.frame_count++;
   205 	pvr2_display_frame();
   206     }
   207 }
   209 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   210 {
   211     pvr2_update_raster_posn( nanosecs );
   212     pvr2_state.cycles_run = 0;
   213     return nanosecs;
   214 }
   216 int pvr2_get_frame_count() 
   217 {
   218     return pvr2_state.frame_count;
   219 }
   221 gboolean pvr2_save_next_scene( const gchar *filename )
   222 {
   223     if( pvr2_state.save_next_render_filename != NULL ) {
   224 	g_free( pvr2_state.save_next_render_filename );
   225     } 
   226     pvr2_state.save_next_render_filename = g_strdup(filename);
   227     return TRUE;
   228 }
   232 /**
   233  * Display the next frame, copying the current contents of video ram to
   234  * the window. If the video configuration has changed, first recompute the
   235  * new frame size/depth.
   236  */
   237 void pvr2_display_frame( void )
   238 {
   239     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   240     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
   241     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   243     if( display_driver == NULL ) {
   244 	return; /* can't really do anything much */
   245     } else if( !bEnabled ) {
   246 	/* Output disabled == black */
   247 	display_driver->display_blank( 0 ); 
   248     } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { 
   249 	/* Enabled but blanked - border colour */
   250 	uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
   251 	display_driver->display_blank( colour );
   252     } else {
   253 	/* Real output - determine dimensions etc */
   254 	struct frame_buffer fbuf;
   255 	uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
   256 	int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
   257 	int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   259 	fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
   260 	fbuf.width = vid_ppl << 2 / colour_formats[fbuf.colour_format].bpp;
   261 	fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   262 	fbuf.size = vid_ppl << 2 * fbuf.height;
   263 	fbuf.rowstride = (vid_ppl + vid_stride) << 2;
   265 	/* Determine the field to display, and deinterlace if possible */
   266 	if( pvr2_state.interlaced ) {
   267 	    if( vid_ppl == vid_stride ) { /* Magic deinterlace */
   268 		fbuf.height = fbuf.height << 1;
   269 		fbuf.rowstride = vid_ppl << 2;
   270 		fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   271 	    } else { 
   272 		/* Just display the field as is, folks. This is slightly tricky -
   273 		 * we pick the field based on which frame is about to come through,
   274 		 * which may not be the same as the odd_even_field.
   275 		 */
   276 		gboolean oddfield = pvr2_state.odd_even_field;
   277 		if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
   278 		    oddfield = !oddfield;
   279 		}
   280 		if( oddfield ) {
   281 		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   282 		} else {
   283 		    fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
   284 		}
   285 	    }
   286 	} else {
   287 	    fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
   288 	}
   289 	fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
   291 	render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
   292 	if( rbuf != NULL ) {
   293 	    display_driver->display_render_buffer( rbuf );
   294 	} else {
   295 	    fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
   296 	    display_driver->display_frame_buffer( &fbuf );
   297 	}
   298     }
   299 }
   301 /**
   302  * This has to handle every single register individually as they all get masked 
   303  * off differently (and its easier to do it at write time)
   304  */
   305 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   306 {
   307     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   308         MMIO_WRITE( PVR2, reg, val );
   309         return;
   310     }
   312     switch(reg) {
   313     case PVRID:
   314     case PVRVER:
   315     case GUNPOS: /* Read only registers */
   316 	break;
   317     case PVRRESET:
   318 	val &= 0x00000007; /* Do stuff? */
   319 	MMIO_WRITE( PVR2, reg, val );
   320 	break;
   321     case RENDER_START: /* Don't really care what value */
   322 	if( pvr2_state.save_next_render_filename != NULL ) {
   323 	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {
   324 		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);
   325 	    }
   326 	    g_free( pvr2_state.save_next_render_filename );
   327 	    pvr2_state.save_next_render_filename = NULL;
   328 	}
   329 	render_buffer_t buffer = pvr2_next_render_buffer();
   330 	pvr2_render_scene( buffer );
   331 	asic_event( EVENT_PVR_RENDER_DONE );
   332 	break;
   333     case RENDER_POLYBASE:
   334     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   335     	break;
   336     case RENDER_TSPCFG:
   337     	MMIO_WRITE( PVR2, reg, val&0x00010101 );
   338     	break;
   339     case DISP_BORDER:
   340     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   341     	break;
   342     case DISP_MODE:
   343     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   344     	break;
   345     case RENDER_MODE:
   346     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   347     	break;
   348     case RENDER_SIZE:
   349     	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   350     	break;
   351     case DISP_ADDR1:
   352 	val &= 0x00FFFFFC;
   353 	MMIO_WRITE( PVR2, reg, val );
   354 	pvr2_update_raster_posn(sh4r.slice_cycle);
   355 	break;
   356     case DISP_ADDR2:
   357     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   358 	pvr2_update_raster_posn(sh4r.slice_cycle);
   359     	break;
   360     case DISP_SIZE:
   361     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   362     	break;
   363     case RENDER_ADDR1:
   364     case RENDER_ADDR2:
   365     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   366     	break;
   367     case RENDER_HCLIP:
   368 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   369 	break;
   370     case RENDER_VCLIP:
   371 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   372 	break;
   373     case DISP_HPOSIRQ:
   374 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   375 	pvr2_state.irq_hpos_line = val & 0x03FF;
   376 	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
   377 	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
   378 	switch( pvr2_state.irq_hpos_mode ) {
   379 	case 3: /* Reserved - treat as 0 */
   380 	case 0: /* Once per frame at specified line */
   381 	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
   382 	    break;
   383 	case 2: /* Once per line - as per-line-count */
   384 	    pvr2_state.irq_hpos_line = 1;
   385 	    pvr2_state.irq_hpos_mode = 1;
   386 	case 1: /* Once per N lines */
   387 	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
   388 	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) + 
   389 		pvr2_state.irq_hpos_line_count;
   390 	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
   391 		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
   392 	    }
   393 	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
   394 	}
   395 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
   396 					  pvr2_state.irq_hpos_time_ns );
   397 	break;
   398     case DISP_VPOSIRQ:
   399 	val = val & 0x03FF03FF;
   400 	pvr2_state.irq_vpos1 = (val >> 16);
   401 	pvr2_state.irq_vpos2 = val & 0x03FF;
   402 	pvr2_update_raster_posn(sh4r.slice_cycle);
   403 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   404 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   405 	MMIO_WRITE( PVR2, reg, val );
   406 	break;
   407     case RENDER_NEARCLIP:
   408 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   409 	break;
   410     case RENDER_SHADOW:
   411 	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   412 	break;
   413     case RENDER_OBJCFG:
   414     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   415     	break;
   416     case RENDER_TSPCLIP:
   417     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   418     	break;
   419     case RENDER_FARCLIP:
   420 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   421 	break;
   422     case RENDER_BGPLANE:
   423     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   424     	break;
   425     case RENDER_ISPCFG:
   426     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   427     	break;
   428     case VRAM_CFG1:
   429 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   430 	break;
   431     case VRAM_CFG2:
   432 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   433 	break;
   434     case VRAM_CFG3:
   435 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   436 	break;
   437     case RENDER_FOGTBLCOL:
   438     case RENDER_FOGVRTCOL:
   439 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   440 	break;
   441     case RENDER_FOGCOEFF:
   442 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   443 	break;
   444     case RENDER_CLAMPHI:
   445     case RENDER_CLAMPLO:
   446 	MMIO_WRITE( PVR2, reg, val );
   447 	break;
   448     case RENDER_TEXSIZE:
   449 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   450 	break;
   451     case RENDER_PALETTE:
   452 	MMIO_WRITE( PVR2, reg, val&0x00000003 );
   453 	break;
   455 	/********** CRTC registers *************/
   456     case DISP_HBORDER:
   457     case DISP_VBORDER:
   458 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   459 	break;
   460     case DISP_TOTAL:
   461 	val = val & 0x03FF03FF;
   462 	MMIO_WRITE( PVR2, reg, val );
   463 	pvr2_update_raster_posn(sh4r.slice_cycle);
   464 	pvr2_state.total_lines = (val >> 16) + 1;
   465 	pvr2_state.line_size = (val & 0x03FF) + 1;
   466 	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
   467 	pvr2_state.retrace_end_line = 0x2A;
   468 	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
   469 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
   470 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
   471 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0, 
   472 					  pvr2_state.irq_hpos_time_ns );
   473 	break;
   474     case DISP_SYNCCFG:
   475 	MMIO_WRITE( PVR2, reg, val&0x000003FF );
   476 	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
   477 	break;
   478     case DISP_SYNCTIME:
   479 	pvr2_state.vsync_lines = (val >> 8) & 0x0F;
   480 	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
   481 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   482 	break;
   483     case DISP_CFG2:
   484 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   485 	break;
   486     case DISP_HPOS:
   487 	val = val & 0x03FF;
   488 	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
   489 	MMIO_WRITE( PVR2, reg, val );
   490 	break;
   491     case DISP_VPOS:
   492 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   493 	break;
   495 	/*********** Tile accelerator registers ***********/
   496     case TA_POLYPOS:
   497     case TA_LISTPOS:
   498 	/* Readonly registers */
   499 	break;
   500     case TA_TILEBASE:
   501     case TA_LISTEND:
   502     case TA_LISTBASE:
   503 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   504 	break;
   505     case RENDER_TILEBASE:
   506     case TA_POLYBASE:
   507     case TA_POLYEND:
   508 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   509 	break;
   510     case TA_TILESIZE:
   511 	MMIO_WRITE( PVR2, reg, val&0x000F003F );
   512 	break;
   513     case TA_TILECFG:
   514 	MMIO_WRITE( PVR2, reg, val&0x00133333 );
   515 	break;
   516     case TA_INIT:
   517 	if( val & 0x80000000 )
   518 	    pvr2_ta_init();
   519 	break;
   520     case TA_REINIT:
   521 	break;
   522 	/**************** Scaler registers? ****************/
   523     case RENDER_SCALER:
   524 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   525 	break;
   527     case YUV_ADDR:
   528 	val = val & 0x00FFFFF8;
   529 	MMIO_WRITE( PVR2, reg, val );
   530 	pvr2_yuv_init( val );
   531 	break;
   532     case YUV_CFG:
   533 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   534 	pvr2_yuv_set_config(val);
   535 	break;
   537 	/**************** Unknowns ***************/
   538     case PVRUNK1:
   539     	MMIO_WRITE( PVR2, reg, val&0x000007FF );
   540     	break;
   541     case PVRUNK2:
   542 	MMIO_WRITE( PVR2, reg, val&0x00000007 );
   543 	break;
   544     case PVRUNK3:
   545 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   546 	break;
   547     case PVRUNK5:
   548 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   549 	break;
   550     case PVRUNK6:
   551 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   552 	break;
   553     case PVRUNK7:
   554 	MMIO_WRITE( PVR2, reg, val&0x00000001 );
   555 	break;
   556     }
   557 }
   559 /**
   560  * Calculate the current read value of the syncstat register, using
   561  * the current SH4 clock time as an offset from the last timeslice.
   562  * The register reads (LSB to MSB) as:
   563  *     0..9  Current scan line
   564  *     10    Odd/even field (1 = odd, 0 = even)
   565  *     11    Display active (including border and overscan)
   566  *     12    Horizontal sync off
   567  *     13    Vertical sync off
   568  * Note this method is probably incorrect for anything other than straight
   569  * interlaced PAL/NTSC, and needs further testing. 
   570  */
   571 uint32_t pvr2_get_sync_status()
   572 {
   573     pvr2_update_raster_posn(sh4r.slice_cycle);
   574     uint32_t result = pvr2_state.line_count;
   576     if( pvr2_state.odd_even_field ) {
   577 	result |= 0x0400;
   578     }
   579     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
   580 	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
   581 	    result |= 0x1000; /* !HSYNC */
   582 	}
   583 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   584 	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
   585 		result |= 0x2800; /* Display active */
   586 	    } else {
   587 		result |= 0x2000; /* Front porch */
   588 	    }
   589 	}
   590     } else {
   591 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
   592 	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
   593 		result |= 0x3800; /* Display active */
   594 	    } else {
   595 		result |= 0x3000;
   596 	    }
   597 	} else {
   598 	    result |= 0x1000; /* Back porch */
   599 	}
   600     }
   601     return result;
   602 }
   604 /**
   605  * Schedule a "scanline" event. This actually goes off at
   606  * 2 * line in even fields and 2 * line + 1 in odd fields.
   607  * Otherwise this behaves as per pvr2_schedule_line_event().
   608  * The raster position should be updated before calling this
   609  * method.
   610  * @param eventid Event to fire at the specified time
   611  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
   612  *  displays). 
   613  * @param hpos_ns Nanoseconds into the line at which to fire.
   614  */
   615 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
   616 {
   617     uint32_t field = pvr2_state.odd_even_field;
   618     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
   619 	field = !field;
   620     }
   621     if( hpos_ns > pvr2_state.line_time_ns ) {
   622 	hpos_ns = pvr2_state.line_time_ns;
   623     }
   625     line <<= 1;
   626     if( field ) {
   627 	line += 1;
   628     }
   630     if( line < pvr2_state.total_lines ) {
   631 	uint32_t lines;
   632 	uint32_t time;
   633 	if( line <= pvr2_state.line_count ) {
   634 	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
   635 	} else {
   636 	    lines = (line - pvr2_state.line_count);
   637 	}
   638 	if( lines <= minimum_lines ) {
   639 	    lines += pvr2_state.total_lines;
   640 	}
   641 	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
   642 	event_schedule( eventid, time );
   643     } else {
   644 	event_cancel( eventid );
   645     }
   646 }
   648 MMIO_REGION_READ_FN( PVR2, reg )
   649 {
   650     switch( reg ) {
   651         case DISP_SYNCSTAT:
   652             return pvr2_get_sync_status();
   653         default:
   654             return MMIO_READ( PVR2, reg );
   655     }
   656 }
   658 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
   659 {
   660     MMIO_WRITE( PVR2PAL, reg, val );
   661     pvr2_state.palette_changed = TRUE;
   662 }
   664 void pvr2_check_palette_changed()
   665 {
   666     if( pvr2_state.palette_changed ) {
   667 	texcache_invalidate_palette();
   668 	pvr2_state.palette_changed = FALSE;
   669     }
   670 }
   672 MMIO_REGION_READ_DEFFN( PVR2PAL );
   674 void pvr2_set_base_address( uint32_t base ) 
   675 {
   676     mmio_region_PVR2_write( DISP_ADDR1, base );
   677 }
   682 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   683 {
   684     return 0xFFFFFFFF;
   685 }
   687 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   688 {
   689     pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
   690 }
   692 /**
   693  * Find the render buffer corresponding to the requested output frame
   694  * (does not consider texture renders). 
   695  * @return the render_buffer if found, or null if no such buffer.
   696  *
   697  * Note: Currently does not consider "partial matches", ie partial
   698  * frame overlap - it probably needs to do this.
   699  */
   700 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
   701 {
   702     int i;
   703     for( i=0; i<render_buffer_count; i++ ) {
   704 	if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
   705 	    return render_buffers[i];
   706 	}
   707     }
   708     return NULL;
   709 }
   711 /**
   712  * Determine the next render buffer to write into. The order of preference is:
   713  *   1. An existing buffer with the same address. (not flushed unless the new
   714  * size is smaller than the old one).
   715  *   2. An existing buffer with the same size chosen by LRU order. Old buffer
   716  *       is flushed to vram.
   717  *   3. A new buffer if one can be created.
   718  *   4. The current display buff
   719  * Note: The current display field(s) will never be overwritten except as a last
   720  * resort.
   721  */
   722 render_buffer_t pvr2_next_render_buffer()
   723 {
   724     render_buffer_t result = NULL;
   725     uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
   726     uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
   727     uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
   728     uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
   729     gboolean render_to_tex;
   730     if( render_addr & 0x01000000 ) { /* vram64 */
   731 	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
   732     } else { /* vram32 */
   733 	render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
   734     }
   736     int width, height, i;
   737     int colour_format = pvr2_render_colour_format[render_mode&0x07];
   738     pvr2_render_getsize( &width, &height );
   740     /* Check existing buffers for an available buffer */
   741     for( i=0; i<render_buffer_count; i++ ) {
   742 	if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
   743 	    /* needs to be the right dimensions */
   744 	    if( render_buffers[i]->address == render_addr ) {
   745 		/* perfect */
   746 		result = render_buffers[i];
   747 		break;
   748 	    } else if( render_buffers[i]->address == -1 && result == NULL ) {
   749 		result = render_buffers[i];
   750 	    }
   751 	} else if( render_buffers[i]->address == render_addr ) {
   752 	    /* right address, wrong size - if it's larger, flush it, otherwise 
   753 	     * nuke it quietly */
   754 	    if( render_buffers[i]->width * render_buffers[i]->height >
   755 		width*height ) {
   756 		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
   757 	    }
   758 	    render_buffers[i]->address == -1;
   759 	}
   760     }
   762     /* Nothing available - make one */
   763     if( result == NULL ) {
   764 	if( render_buffer_count == MAX_RENDER_BUFFERS ) {
   765 	    /* maximum buffers reached - need to throw one away */
   766 	    uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
   767 	    uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
   768 	    for( i=0; i<render_buffer_count; i++ ) {
   769 		if( render_buffers[i]->address != field1_addr &&
   770 		    render_buffers[i]->address != field2_addr ) {
   771 		    /* Never throw away the current "front buffer(s)" */
   772 		    result = render_buffers[i];
   773 		    pvr2_render_buffer_copy_to_sh4( result );
   774 		    if( result->width != width || result->height != height ) {
   775 			display_driver->destroy_render_buffer(render_buffers[i]);
   776 			result = display_driver->create_render_buffer(width,height);
   777 			render_buffers[i] = result;
   778 		    }
   779 		    break;
   780 		}
   781 	    }
   782 	} else {
   783 	    result = display_driver->create_render_buffer(width,height);
   784 	    if( result != NULL ) { 
   785 		render_buffers[render_buffer_count++] = result;
   786 	    } else {
   787 		ERROR( "Failed to obtain a render buffer!" );
   788 		return NULL;
   789 	    }
   790 	}
   791     }
   793     /* Setup the buffer */
   794     result->rowstride = render_stride;
   795     result->colour_format = colour_format;
   796     result->scale = render_scale;
   797     result->size = width * height * colour_formats[colour_format].bpp;
   798     result->address = render_addr;
   799     result->flushed = FALSE;
   800     return result;
   801 }
   803 /**
   804  * Invalidate any caching on the supplied address. Specifically, if it falls
   805  * within any of the render buffers, flush the buffer back to PVR2 ram.
   806  */
   807 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
   808 {
   809     int i;
   810     address = address & 0x1FFFFFFF;
   811     for( i=0; i<render_buffer_count; i++ ) {
   812 	uint32_t bufaddr = render_buffers[i]->address;
   813 	uint32_t size = render_buffers[i]->size;
   814 	if( bufaddr != -1 && bufaddr <= address && 
   815 	    (bufaddr + render_buffers[i]->size) > address ) {
   816 	    if( !render_buffers[i]->flushed ) {
   817 		pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
   818 		render_buffers[i]->flushed = TRUE;
   819 	    }
   820 	    if( isWrite ) {
   821 		render_buffers[i]->address = -1; /* Invalid */
   822 	    }
   823 	    return TRUE; /* should never have overlapping buffers */
   824 	}
   825     }
   826     return FALSE;
   827 }
.