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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 378:f10fbdd4e24b
prev374:8f80a795513e
next384:c9d5c194984b
author nkeynes
date Wed Sep 12 09:20:38 2007 +0000 (13 years ago)
permissions -rw-r--r--
last change Start splitting the common SH4 parts into sh4.c, with sh4core.c to become
just the emulation core.
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     1 /**
     2  * $Id: sh4core.c,v 1.45 2007-09-12 09:20:38 nkeynes Exp $
     3  * 
     4  * SH4 emulation core, and parent module for all the SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include "dream.h"
    23 #include "sh4/sh4core.h"
    24 #include "sh4/sh4mmio.h"
    25 #include "sh4/intc.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "syscall.h"
    30 #define SH4_CALLTRACE 1
    32 #define MAX_INT 0x7FFFFFFF
    33 #define MIN_INT 0x80000000
    34 #define MAX_INTF 2147483647.0
    35 #define MIN_INTF -2147483648.0
    37 #define EXV_EXCEPTION    0x100  /* General exception vector */
    38 #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    39 #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    41 /********************** SH4 Module Definition ****************************/
    43 uint32_t sh4_run_slice( uint32_t );
    45 static uint16_t *sh4_icache = NULL;
    46 static uint32_t sh4_icache_addr = 0;
    48 uint32_t sh4_run_slice( uint32_t nanosecs ) 
    49 {
    50     int i;
    51     sh4r.slice_cycle = 0;
    53     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
    54 	if( sh4r.event_pending < nanosecs ) {
    55 	    sh4r.sh4_state = SH4_STATE_RUNNING;
    56 	    sh4r.slice_cycle = sh4r.event_pending;
    57 	}
    58     }
    60     if( sh4_breakpoint_count == 0 ) {
    61 	for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    62 	    if( SH4_EVENT_PENDING() ) {
    63 		if( sh4r.event_types & PENDING_EVENT ) {
    64 		    event_execute();
    65 		}
    66 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    67 		if( sh4r.event_types & PENDING_IRQ ) {
    68 		    sh4_accept_interrupt();
    69 		}
    70 	    }
    71 	    if( !sh4_execute_instruction() ) {
    72 		break;
    73 	    }
    74 	}
    75     } else {
    76 	for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
    77 	    if( SH4_EVENT_PENDING() ) {
    78 		if( sh4r.event_types & PENDING_EVENT ) {
    79 		    event_execute();
    80 		}
    81 		/* Eventq execute may (quite likely) deliver an immediate IRQ */
    82 		if( sh4r.event_types & PENDING_IRQ ) {
    83 		    sh4_accept_interrupt();
    84 		}
    85 	    }
    87 	    if( !sh4_execute_instruction() )
    88 		break;
    89 #ifdef ENABLE_DEBUG_MODE
    90 	    for( i=0; i<sh4_breakpoint_count; i++ ) {
    91 		if( sh4_breakpoints[i].address == sh4r.pc ) {
    92 		    break;
    93 		}
    94 	    }
    95 	    if( i != sh4_breakpoint_count ) {
    96 		dreamcast_stop();
    97 		if( sh4_breakpoints[i].type == BREAK_ONESHOT )
    98 		    sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
    99 		break;
   100 	    }
   101 #endif	
   102 	}
   103     }
   105     /* If we aborted early, but the cpu is still technically running,
   106      * we're doing a hard abort - cut the timeslice back to what we
   107      * actually executed
   108      */
   109     if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
   110 	nanosecs = sh4r.slice_cycle;
   111     }
   112     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   113 	TMU_run_slice( nanosecs );
   114 	SCIF_run_slice( nanosecs );
   115     }
   116     return nanosecs;
   117 }
   119 /********************** SH4 emulation core  ****************************/
   121 void sh4_set_pc( int pc )
   122 {
   123     sh4r.pc = pc;
   124     sh4r.new_pc = pc+2;
   125 }
   127 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
   128 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
   130 #if(SH4_CALLTRACE == 1)
   131 #define MAX_CALLSTACK 32
   132 static struct call_stack {
   133     sh4addr_t call_addr;
   134     sh4addr_t target_addr;
   135     sh4addr_t stack_pointer;
   136 } call_stack[MAX_CALLSTACK];
   138 static int call_stack_depth = 0;
   139 int sh4_call_trace_on = 0;
   141 static inline trace_call( sh4addr_t source, sh4addr_t dest ) 
   142 {
   143     if( call_stack_depth < MAX_CALLSTACK ) {
   144 	call_stack[call_stack_depth].call_addr = source;
   145 	call_stack[call_stack_depth].target_addr = dest;
   146 	call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
   147     }
   148     call_stack_depth++;
   149 }
   151 static inline trace_return( sh4addr_t source, sh4addr_t dest )
   152 {
   153     if( call_stack_depth > 0 ) {
   154 	call_stack_depth--;
   155     }
   156 }
   158 void fprint_stack_trace( FILE *f )
   159 {
   160     int i = call_stack_depth -1;
   161     if( i >= MAX_CALLSTACK )
   162 	i = MAX_CALLSTACK - 1;
   163     for( ; i >= 0; i-- ) {
   164 	fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n", 
   165 		 (call_stack_depth - i), call_stack[i].call_addr,
   166 		 call_stack[i].target_addr, call_stack[i].stack_pointer );
   167     }
   168 }
   170 #define TRACE_CALL( source, dest ) trace_call(source, dest)
   171 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
   172 #else
   173 #define TRACE_CALL( dest, rts ) 
   174 #define TRACE_RETURN( source, dest )
   175 #endif
   177 #define RAISE( x, v ) do{			\
   178     if( sh4r.vbr == 0 ) { \
   179         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   180         dreamcast_stop(); return FALSE;	\
   181     } else { \
   182         sh4r.spc = sh4r.pc;	\
   183         sh4r.ssr = sh4_read_sr(); \
   184         sh4r.sgr = sh4r.r[15]; \
   185         MMIO_WRITE(MMU,EXPEVT,x); \
   186         sh4r.pc = sh4r.vbr + v; \
   187         sh4r.new_pc = sh4r.pc + 2; \
   188         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   189 	if( sh4r.in_delay_slot ) { \
   190 	    sh4r.in_delay_slot = 0; \
   191 	    sh4r.spc -= 2; \
   192 	} \
   193     } \
   194     return TRUE; } while(0)
   196 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   197 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   198 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   199 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   200 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   201 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   203 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   205 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
   206 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
   208 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
   209 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   210 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
   211 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   212 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
   214 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
   215 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
   216 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
   218 static void sh4_switch_banks( )
   219 {
   220     uint32_t tmp[8];
   222     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   223     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   224     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   225 }
   227 void sh4_write_sr( uint32_t newval )
   228 {
   229     if( (newval ^ sh4r.sr) & SR_RB )
   230         sh4_switch_banks();
   231     sh4r.sr = newval;
   232     sh4r.t = (newval&SR_T) ? 1 : 0;
   233     sh4r.s = (newval&SR_S) ? 1 : 0;
   234     sh4r.m = (newval&SR_M) ? 1 : 0;
   235     sh4r.q = (newval&SR_Q) ? 1 : 0;
   236     intc_mask_changed();
   237 }
   239 static void sh4_write_float( uint32_t addr, int reg )
   240 {
   241     if( IS_FPU_DOUBLESIZE() ) {
   242 	if( reg & 1 ) {
   243 	    sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
   244 	    sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
   245 	} else {
   246 	    sh4_write_long( addr, *((uint32_t *)&FR(reg)) ); 
   247 	    sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
   248 	}
   249     } else {
   250 	sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
   251     }
   252 }
   254 static void sh4_read_float( uint32_t addr, int reg )
   255 {
   256     if( IS_FPU_DOUBLESIZE() ) {
   257 	if( reg & 1 ) {
   258 	    *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
   259 	    *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
   260 	} else {
   261 	    *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   262 	    *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
   263 	}
   264     } else {
   265 	*((uint32_t *)&FR(reg)) = sh4_read_long(addr);
   266     }
   267 }
   269 uint32_t sh4_read_sr( void )
   270 {
   271     /* synchronize sh4r.sr with the various bitflags */
   272     sh4r.sr &= SR_MQSTMASK;
   273     if( sh4r.t ) sh4r.sr |= SR_T;
   274     if( sh4r.s ) sh4r.sr |= SR_S;
   275     if( sh4r.m ) sh4r.sr |= SR_M;
   276     if( sh4r.q ) sh4r.sr |= SR_Q;
   277     return sh4r.sr;
   278 }
   280 /**
   281  * Raise a general CPU exception for the specified exception code.
   282  * (NOT for TRAPA or TLB exceptions)
   283  */
   284 gboolean sh4_raise_exception( int code )
   285 {
   286     RAISE( code, EXV_EXCEPTION );
   287 }
   289 gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
   290     if( sh4r.in_delay_slot ) {
   291 	return sh4_raise_exception(slot_code);
   292     } else {
   293 	return sh4_raise_exception(normal_code);
   294     }
   295 }
   297 gboolean sh4_raise_tlb_exception( int code )
   298 {
   299     RAISE( code, EXV_TLBMISS );
   300 }
   302 void sh4_accept_interrupt( void )
   303 {
   304     uint32_t code = intc_accept_interrupt();
   305     sh4r.ssr = sh4_read_sr();
   306     sh4r.spc = sh4r.pc;
   307     sh4r.sgr = sh4r.r[15];
   308     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   309     MMIO_WRITE( MMU, INTEVT, code );
   310     sh4r.pc = sh4r.vbr + 0x600;
   311     sh4r.new_pc = sh4r.pc + 2;
   312     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   313 }
   315 gboolean sh4_execute_instruction( void )
   316 {
   317     uint32_t pc;
   318     unsigned short ir;
   319     uint32_t tmp;
   320     float ftmp;
   321     double dtmp;
   323 #define R0 sh4r.r[0]
   324     pc = sh4r.pc;
   325     if( pc > 0xFFFFFF00 ) {
   326 	/* SYSCALL Magic */
   327 	syscall_invoke( pc );
   328 	sh4r.in_delay_slot = 0;
   329 	pc = sh4r.pc = sh4r.pr;
   330 	sh4r.new_pc = sh4r.pc + 2;
   331     }
   332     CHECKRALIGN16(pc);
   334     /* Read instruction */
   335     uint32_t pageaddr = pc >> 12;
   336     if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
   337 	ir = sh4_icache[(pc&0xFFF)>>1];
   338     } else {
   339 	sh4_icache = (uint16_t *)mem_get_page(pc);
   340 	if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
   341 	    /* If someone's actually been so daft as to try to execute out of an IO
   342 	     * region, fallback on the full-blown memory read
   343 	     */
   344 	    sh4_icache = NULL;
   345 	    ir = MEM_READ_WORD(pc);
   346 	} else {
   347 	    sh4_icache_addr = pageaddr;
   348 	    ir = sh4_icache[(pc&0xFFF)>>1];
   349 	}
   350     }
   351         switch( (ir&0xF000) >> 12 ) {
   352             case 0x0:
   353                 switch( ir&0xF ) {
   354                     case 0x2:
   355                         switch( (ir&0x80) >> 7 ) {
   356                             case 0x0:
   357                                 switch( (ir&0x70) >> 4 ) {
   358                                     case 0x0:
   359                                         { /* STC SR, Rn */
   360                                         uint32_t Rn = ((ir>>8)&0xF); 
   361                                         CHECKPRIV();
   362                                         sh4r.r[Rn] = sh4_read_sr();
   363                                         }
   364                                         break;
   365                                     case 0x1:
   366                                         { /* STC GBR, Rn */
   367                                         uint32_t Rn = ((ir>>8)&0xF); 
   368                                         CHECKPRIV();
   369                                         sh4r.r[Rn] = sh4r.gbr;
   370                                         }
   371                                         break;
   372                                     case 0x2:
   373                                         { /* STC VBR, Rn */
   374                                         uint32_t Rn = ((ir>>8)&0xF); 
   375                                         CHECKPRIV();
   376                                         sh4r.r[Rn] = sh4r.vbr;
   377                                         }
   378                                         break;
   379                                     case 0x3:
   380                                         { /* STC SSR, Rn */
   381                                         uint32_t Rn = ((ir>>8)&0xF); 
   382                                         CHECKPRIV();
   383                                         sh4r.r[Rn] = sh4r.ssr;
   384                                         }
   385                                         break;
   386                                     case 0x4:
   387                                         { /* STC SPC, Rn */
   388                                         uint32_t Rn = ((ir>>8)&0xF); 
   389                                         CHECKPRIV();
   390                                         sh4r.r[Rn] = sh4r.spc;
   391                                         }
   392                                         break;
   393                                     default:
   394                                         UNDEF();
   395                                         break;
   396                                 }
   397                                 break;
   398                             case 0x1:
   399                                 { /* STC Rm_BANK, Rn */
   400                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
   401                                 CHECKPRIV();
   402                                 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
   403                                 }
   404                                 break;
   405                         }
   406                         break;
   407                     case 0x3:
   408                         switch( (ir&0xF0) >> 4 ) {
   409                             case 0x0:
   410                                 { /* BSRF Rn */
   411                                 uint32_t Rn = ((ir>>8)&0xF); 
   412                                 CHECKSLOTILLEGAL();
   413                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   414                                 sh4r.in_delay_slot = 1;
   415                                 sh4r.pr = sh4r.pc + 4;
   416                                 sh4r.pc = sh4r.new_pc;
   417                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   418                                 TRACE_CALL( pc, sh4r.new_pc );
   419                                 return TRUE;
   420                                 }
   421                                 break;
   422                             case 0x2:
   423                                 { /* BRAF Rn */
   424                                 uint32_t Rn = ((ir>>8)&0xF); 
   425                                 CHECKSLOTILLEGAL();
   426                                 CHECKDEST( pc + 4 + sh4r.r[Rn] );
   427                                 sh4r.in_delay_slot = 1;
   428                                 sh4r.pc = sh4r.new_pc;
   429                                 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
   430                                 return TRUE;
   431                                 }
   432                                 break;
   433                             case 0x8:
   434                                 { /* PREF @Rn */
   435                                 uint32_t Rn = ((ir>>8)&0xF); 
   436                                 tmp = sh4r.r[Rn];
   437                                 if( (tmp & 0xFC000000) == 0xE0000000 ) {
   438                            	 sh4_flush_store_queue(tmp);
   439                                 }
   440                                 }
   441                                 break;
   442                             case 0x9:
   443                                 { /* OCBI @Rn */
   444                                 uint32_t Rn = ((ir>>8)&0xF); 
   445                                 }
   446                                 break;
   447                             case 0xA:
   448                                 { /* OCBP @Rn */
   449                                 uint32_t Rn = ((ir>>8)&0xF); 
   450                                 }
   451                                 break;
   452                             case 0xB:
   453                                 { /* OCBWB @Rn */
   454                                 uint32_t Rn = ((ir>>8)&0xF); 
   455                                 }
   456                                 break;
   457                             case 0xC:
   458                                 { /* MOVCA.L R0, @Rn */
   459                                 uint32_t Rn = ((ir>>8)&0xF); 
   460                                 tmp = sh4r.r[Rn];
   461                                 CHECKWALIGN32(tmp);
   462                                 MEM_WRITE_LONG( tmp, R0 );
   463                                 }
   464                                 break;
   465                             default:
   466                                 UNDEF();
   467                                 break;
   468                         }
   469                         break;
   470                     case 0x4:
   471                         { /* MOV.B Rm, @(R0, Rn) */
   472                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   473                         MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   474                         }
   475                         break;
   476                     case 0x5:
   477                         { /* MOV.W Rm, @(R0, Rn) */
   478                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   479                         CHECKWALIGN16( R0 + sh4r.r[Rn] );
   480                         MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   481                         }
   482                         break;
   483                     case 0x6:
   484                         { /* MOV.L Rm, @(R0, Rn) */
   485                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   486                         CHECKWALIGN32( R0 + sh4r.r[Rn] );
   487                         MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
   488                         }
   489                         break;
   490                     case 0x7:
   491                         { /* MUL.L Rm, Rn */
   492                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   493                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   494                                                (sh4r.r[Rm] * sh4r.r[Rn]);
   495                         }
   496                         break;
   497                     case 0x8:
   498                         switch( (ir&0xFF0) >> 4 ) {
   499                             case 0x0:
   500                                 { /* CLRT */
   501                                 sh4r.t = 0;
   502                                 }
   503                                 break;
   504                             case 0x1:
   505                                 { /* SETT */
   506                                 sh4r.t = 1;
   507                                 }
   508                                 break;
   509                             case 0x2:
   510                                 { /* CLRMAC */
   511                                 sh4r.mac = 0;
   512                                 }
   513                                 break;
   514                             case 0x3:
   515                                 { /* LDTLB */
   516                                 /* TODO */
   517                                 }
   518                                 break;
   519                             case 0x4:
   520                                 { /* CLRS */
   521                                 sh4r.s = 0;
   522                                 }
   523                                 break;
   524                             case 0x5:
   525                                 { /* SETS */
   526                                 sh4r.s = 1;
   527                                 }
   528                                 break;
   529                             default:
   530                                 UNDEF();
   531                                 break;
   532                         }
   533                         break;
   534                     case 0x9:
   535                         switch( (ir&0xF0) >> 4 ) {
   536                             case 0x0:
   537                                 { /* NOP */
   538                                 /* NOP */
   539                                 }
   540                                 break;
   541                             case 0x1:
   542                                 { /* DIV0U */
   543                                 sh4r.m = sh4r.q = sh4r.t = 0;
   544                                 }
   545                                 break;
   546                             case 0x2:
   547                                 { /* MOVT Rn */
   548                                 uint32_t Rn = ((ir>>8)&0xF); 
   549                                 sh4r.r[Rn] = sh4r.t;
   550                                 }
   551                                 break;
   552                             default:
   553                                 UNDEF();
   554                                 break;
   555                         }
   556                         break;
   557                     case 0xA:
   558                         switch( (ir&0xF0) >> 4 ) {
   559                             case 0x0:
   560                                 { /* STS MACH, Rn */
   561                                 uint32_t Rn = ((ir>>8)&0xF); 
   562                                 sh4r.r[Rn] = (sh4r.mac>>32);
   563                                 }
   564                                 break;
   565                             case 0x1:
   566                                 { /* STS MACL, Rn */
   567                                 uint32_t Rn = ((ir>>8)&0xF); 
   568                                 sh4r.r[Rn] = (uint32_t)sh4r.mac;
   569                                 }
   570                                 break;
   571                             case 0x2:
   572                                 { /* STS PR, Rn */
   573                                 uint32_t Rn = ((ir>>8)&0xF); 
   574                                 sh4r.r[Rn] = sh4r.pr;
   575                                 }
   576                                 break;
   577                             case 0x3:
   578                                 { /* STC SGR, Rn */
   579                                 uint32_t Rn = ((ir>>8)&0xF); 
   580                                 CHECKPRIV();
   581                                 sh4r.r[Rn] = sh4r.sgr;
   582                                 }
   583                                 break;
   584                             case 0x5:
   585                                 { /* STS FPUL, Rn */
   586                                 uint32_t Rn = ((ir>>8)&0xF); 
   587                                 sh4r.r[Rn] = sh4r.fpul;
   588                                 }
   589                                 break;
   590                             case 0x6:
   591                                 { /* STS FPSCR, Rn */
   592                                 uint32_t Rn = ((ir>>8)&0xF); 
   593                                 sh4r.r[Rn] = sh4r.fpscr;
   594                                 }
   595                                 break;
   596                             case 0xF:
   597                                 { /* STC DBR, Rn */
   598                                 uint32_t Rn = ((ir>>8)&0xF); 
   599                                 CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr;
   600                                 }
   601                                 break;
   602                             default:
   603                                 UNDEF();
   604                                 break;
   605                         }
   606                         break;
   607                     case 0xB:
   608                         switch( (ir&0xFF0) >> 4 ) {
   609                             case 0x0:
   610                                 { /* RTS */
   611                                 CHECKSLOTILLEGAL();
   612                                 CHECKDEST( sh4r.pr );
   613                                 sh4r.in_delay_slot = 1;
   614                                 sh4r.pc = sh4r.new_pc;
   615                                 sh4r.new_pc = sh4r.pr;
   616                                 TRACE_RETURN( pc, sh4r.new_pc );
   617                                 return TRUE;
   618                                 }
   619                                 break;
   620                             case 0x1:
   621                                 { /* SLEEP */
   622                                 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   623                             	sh4r.sh4_state = SH4_STATE_STANDBY;
   624                                 } else {
   625                             	sh4r.sh4_state = SH4_STATE_SLEEP;
   626                                 }
   627                                 return FALSE; /* Halt CPU */
   628                                 }
   629                                 break;
   630                             case 0x2:
   631                                 { /* RTE */
   632                                 CHECKPRIV();
   633                                 CHECKDEST( sh4r.spc );
   634                                 CHECKSLOTILLEGAL();
   635                                 sh4r.in_delay_slot = 1;
   636                                 sh4r.pc = sh4r.new_pc;
   637                                 sh4r.new_pc = sh4r.spc;
   638                                 sh4_write_sr( sh4r.ssr );
   639                                 return TRUE;
   640                                 }
   641                                 break;
   642                             default:
   643                                 UNDEF();
   644                                 break;
   645                         }
   646                         break;
   647                     case 0xC:
   648                         { /* MOV.B @(R0, Rm), Rn */
   649                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   650                         sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] );
   651                         }
   652                         break;
   653                     case 0xD:
   654                         { /* MOV.W @(R0, Rm), Rn */
   655                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   656                         CHECKRALIGN16( R0 + sh4r.r[Rm] );
   657                                            sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
   658                         }
   659                         break;
   660                     case 0xE:
   661                         { /* MOV.L @(R0, Rm), Rn */
   662                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   663                         CHECKRALIGN32( R0 + sh4r.r[Rm] );
   664                                            sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
   665                         }
   666                         break;
   667                     case 0xF:
   668                         { /* MAC.L @Rm+, @Rn+ */
   669                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   670                         CHECKRALIGN32( sh4r.r[Rm] );
   671                         CHECKRALIGN32( sh4r.r[Rn] );
   672                         int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
   673                         sh4r.r[Rn] += 4;
   674                         tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
   675                         sh4r.r[Rm] += 4;
   676                         if( sh4r.s ) {
   677                             /* 48-bit Saturation. Yuch */
   678                             if( tmpl < (int64_t)0xFFFF800000000000LL )
   679                                 tmpl = 0xFFFF800000000000LL;
   680                             else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
   681                                 tmpl = 0x00007FFFFFFFFFFFLL;
   682                         }
   683                         sh4r.mac = tmpl;
   684                         }
   685                         break;
   686                     default:
   687                         UNDEF();
   688                         break;
   689                 }
   690                 break;
   691             case 0x1:
   692                 { /* MOV.L Rm, @(disp, Rn) */
   693                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
   694                 tmp = sh4r.r[Rn] + disp;
   695                 CHECKWALIGN32( tmp );
   696                 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
   697                 }
   698                 break;
   699             case 0x2:
   700                 switch( ir&0xF ) {
   701                     case 0x0:
   702                         { /* MOV.B Rm, @Rn */
   703                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   704                         MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   705                         }
   706                         break;
   707                     case 0x1:
   708                         { /* MOV.W Rm, @Rn */
   709                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   710                         CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   711                         }
   712                         break;
   713                     case 0x2:
   714                         { /* MOV.L Rm, @Rn */
   715                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   716                         CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   717                         }
   718                         break;
   719                     case 0x4:
   720                         { /* MOV.B Rm, @-Rn */
   721                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   722                         sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] );
   723                         }
   724                         break;
   725                     case 0x5:
   726                         { /* MOV.W Rm, @-Rn */
   727                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   728                         sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] );
   729                         }
   730                         break;
   731                     case 0x6:
   732                         { /* MOV.L Rm, @-Rn */
   733                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   734                         sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] );
   735                         }
   736                         break;
   737                     case 0x7:
   738                         { /* DIV0S Rm, Rn */
   739                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   740                         sh4r.q = sh4r.r[Rn]>>31;
   741                         sh4r.m = sh4r.r[Rm]>>31;
   742                         sh4r.t = sh4r.q ^ sh4r.m;
   743                         }
   744                         break;
   745                     case 0x8:
   746                         { /* TST Rm, Rn */
   747                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   748                         sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1);
   749                         }
   750                         break;
   751                     case 0x9:
   752                         { /* AND Rm, Rn */
   753                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   754                         sh4r.r[Rn] &= sh4r.r[Rm];
   755                         }
   756                         break;
   757                     case 0xA:
   758                         { /* XOR Rm, Rn */
   759                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   760                         sh4r.r[Rn] ^= sh4r.r[Rm];
   761                         }
   762                         break;
   763                     case 0xB:
   764                         { /* OR Rm, Rn */
   765                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   766                         sh4r.r[Rn] |= sh4r.r[Rm];
   767                         }
   768                         break;
   769                     case 0xC:
   770                         { /* CMP/STR Rm, Rn */
   771                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   772                         /* set T = 1 if any byte in RM & RN is the same */
   773                         tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
   774                         sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   775                                  (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   776                         }
   777                         break;
   778                     case 0xD:
   779                         { /* XTRCT Rm, Rn */
   780                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   781                         sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16);
   782                         }
   783                         break;
   784                     case 0xE:
   785                         { /* MULU.W Rm, Rn */
   786                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   787                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   788                                    (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
   789                         }
   790                         break;
   791                     case 0xF:
   792                         { /* MULS.W Rm, Rn */
   793                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   794                         sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   795                                    (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
   796                         }
   797                         break;
   798                     default:
   799                         UNDEF();
   800                         break;
   801                 }
   802                 break;
   803             case 0x3:
   804                 switch( ir&0xF ) {
   805                     case 0x0:
   806                         { /* CMP/EQ Rm, Rn */
   807                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   808                         sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 );
   809                         }
   810                         break;
   811                     case 0x2:
   812                         { /* CMP/HS Rm, Rn */
   813                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   814                         sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 );
   815                         }
   816                         break;
   817                     case 0x3:
   818                         { /* CMP/GE Rm, Rn */
   819                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   820                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   821                         }
   822                         break;
   823                     case 0x4:
   824                         { /* DIV1 Rm, Rn */
   825                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   826                         /* This is just from the sh4p manual with some
   827                          * simplifications (someone want to check it's correct? :)
   828                          * Why they couldn't just provide a real DIV instruction...
   829                          */
   830                         uint32_t tmp0, tmp1, tmp2, dir;
   832                         dir = sh4r.q ^ sh4r.m;
   833                         sh4r.q = (sh4r.r[Rn] >> 31);
   834                         tmp2 = sh4r.r[Rm];
   835                         sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
   836                         tmp0 = sh4r.r[Rn];
   837                         if( dir ) {
   838                              sh4r.r[Rn] += tmp2;
   839                              tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
   840                         } else {
   841                              sh4r.r[Rn] -= tmp2;
   842                              tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
   843                         }
   844                         sh4r.q ^= sh4r.m ^ tmp1;
   845                         sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   846                         }
   847                         break;
   848                     case 0x5:
   849                         { /* DMULU.L Rm, Rn */
   850                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   851                         sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]);
   852                         }
   853                         break;
   854                     case 0x6:
   855                         { /* CMP/HI Rm, Rn */
   856                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   857                         sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 );
   858                         }
   859                         break;
   860                     case 0x7:
   861                         { /* CMP/GT Rm, Rn */
   862                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   863                         sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 );
   864                         }
   865                         break;
   866                     case 0x8:
   867                         { /* SUB Rm, Rn */
   868                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   869                         sh4r.r[Rn] -= sh4r.r[Rm];
   870                         }
   871                         break;
   872                     case 0xA:
   873                         { /* SUBC Rm, Rn */
   874                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   875                         tmp = sh4r.r[Rn];
   876                         sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
   877                         sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
   878                         }
   879                         break;
   880                     case 0xB:
   881                         UNIMP(ir); /* SUBV Rm, Rn */
   882                         break;
   883                     case 0xC:
   884                         { /* ADD Rm, Rn */
   885                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   886                         sh4r.r[Rn] += sh4r.r[Rm];
   887                         }
   888                         break;
   889                     case 0xD:
   890                         { /* DMULS.L Rm, Rn */
   891                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   892                         sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]);
   893                         }
   894                         break;
   895                     case 0xE:
   896                         { /* ADDC Rm, Rn */
   897                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   898                         tmp = sh4r.r[Rn];
   899                         sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
   900                         sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
   901                         }
   902                         break;
   903                     case 0xF:
   904                         { /* ADDV Rm, Rn */
   905                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
   906                         tmp = sh4r.r[Rn] + sh4r.r[Rm];
   907                         sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
   908                         sh4r.r[Rn] = tmp;
   909                         }
   910                         break;
   911                     default:
   912                         UNDEF();
   913                         break;
   914                 }
   915                 break;
   916             case 0x4:
   917                 switch( ir&0xF ) {
   918                     case 0x0:
   919                         switch( (ir&0xF0) >> 4 ) {
   920                             case 0x0:
   921                                 { /* SHLL Rn */
   922                                 uint32_t Rn = ((ir>>8)&0xF); 
   923                                 sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1;
   924                                 }
   925                                 break;
   926                             case 0x1:
   927                                 { /* DT Rn */
   928                                 uint32_t Rn = ((ir>>8)&0xF); 
   929                                 sh4r.r[Rn] --;
   930                                 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
   931                                 }
   932                                 break;
   933                             case 0x2:
   934                                 { /* SHAL Rn */
   935                                 uint32_t Rn = ((ir>>8)&0xF); 
   936                                 sh4r.t = sh4r.r[Rn] >> 31;
   937                                 sh4r.r[Rn] <<= 1;
   938                                 }
   939                                 break;
   940                             default:
   941                                 UNDEF();
   942                                 break;
   943                         }
   944                         break;
   945                     case 0x1:
   946                         switch( (ir&0xF0) >> 4 ) {
   947                             case 0x0:
   948                                 { /* SHLR Rn */
   949                                 uint32_t Rn = ((ir>>8)&0xF); 
   950                                 sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1;
   951                                 }
   952                                 break;
   953                             case 0x1:
   954                                 { /* CMP/PZ Rn */
   955                                 uint32_t Rn = ((ir>>8)&0xF); 
   956                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 );
   957                                 }
   958                                 break;
   959                             case 0x2:
   960                                 { /* SHAR Rn */
   961                                 uint32_t Rn = ((ir>>8)&0xF); 
   962                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
   963                                 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
   964                                 }
   965                                 break;
   966                             default:
   967                                 UNDEF();
   968                                 break;
   969                         }
   970                         break;
   971                     case 0x2:
   972                         switch( (ir&0xF0) >> 4 ) {
   973                             case 0x0:
   974                                 { /* STS.L MACH, @-Rn */
   975                                 uint32_t Rn = ((ir>>8)&0xF); 
   976                                 sh4r.r[Rn] -= 4;
   977                                 CHECKWALIGN32( sh4r.r[Rn] );
   978                                 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
   979                                 }
   980                                 break;
   981                             case 0x1:
   982                                 { /* STS.L MACL, @-Rn */
   983                                 uint32_t Rn = ((ir>>8)&0xF); 
   984                                 sh4r.r[Rn] -= 4;
   985                                 CHECKWALIGN32( sh4r.r[Rn] );
   986                                 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
   987                                 }
   988                                 break;
   989                             case 0x2:
   990                                 { /* STS.L PR, @-Rn */
   991                                 uint32_t Rn = ((ir>>8)&0xF); 
   992                                 sh4r.r[Rn] -= 4;
   993                                 CHECKWALIGN32( sh4r.r[Rn] );
   994                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
   995                                 }
   996                                 break;
   997                             case 0x3:
   998                                 { /* STC.L SGR, @-Rn */
   999                                 uint32_t Rn = ((ir>>8)&0xF); 
  1000                                 CHECKPRIV();
  1001                                 sh4r.r[Rn] -= 4;
  1002                                 CHECKWALIGN32( sh4r.r[Rn] );
  1003                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
  1005                                 break;
  1006                             case 0x5:
  1007                                 { /* STS.L FPUL, @-Rn */
  1008                                 uint32_t Rn = ((ir>>8)&0xF); 
  1009                                 sh4r.r[Rn] -= 4;
  1010                                 CHECKWALIGN32( sh4r.r[Rn] );
  1011                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
  1013                                 break;
  1014                             case 0x6:
  1015                                 { /* STS.L FPSCR, @-Rn */
  1016                                 uint32_t Rn = ((ir>>8)&0xF); 
  1017                                 sh4r.r[Rn] -= 4;
  1018                                 CHECKWALIGN32( sh4r.r[Rn] );
  1019                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
  1021                                 break;
  1022                             case 0xF:
  1023                                 { /* STC.L DBR, @-Rn */
  1024                                 uint32_t Rn = ((ir>>8)&0xF); 
  1025                                 CHECKPRIV();
  1026                                 sh4r.r[Rn] -= 4;
  1027                                 CHECKWALIGN32( sh4r.r[Rn] );
  1028                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
  1030                                 break;
  1031                             default:
  1032                                 UNDEF();
  1033                                 break;
  1035                         break;
  1036                     case 0x3:
  1037                         switch( (ir&0x80) >> 7 ) {
  1038                             case 0x0:
  1039                                 switch( (ir&0x70) >> 4 ) {
  1040                                     case 0x0:
  1041                                         { /* STC.L SR, @-Rn */
  1042                                         uint32_t Rn = ((ir>>8)&0xF); 
  1043                                         CHECKPRIV();
  1044                                         sh4r.r[Rn] -= 4;
  1045                                         CHECKWALIGN32( sh4r.r[Rn] );
  1046                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
  1048                                         break;
  1049                                     case 0x1:
  1050                                         { /* STC.L GBR, @-Rn */
  1051                                         uint32_t Rn = ((ir>>8)&0xF); 
  1052                                         sh4r.r[Rn] -= 4;
  1053                                         CHECKWALIGN32( sh4r.r[Rn] );
  1054                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
  1056                                         break;
  1057                                     case 0x2:
  1058                                         { /* STC.L VBR, @-Rn */
  1059                                         uint32_t Rn = ((ir>>8)&0xF); 
  1060                                         CHECKPRIV();
  1061                                         sh4r.r[Rn] -= 4;
  1062                                         CHECKWALIGN32( sh4r.r[Rn] );
  1063                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
  1065                                         break;
  1066                                     case 0x3:
  1067                                         { /* STC.L SSR, @-Rn */
  1068                                         uint32_t Rn = ((ir>>8)&0xF); 
  1069                                         CHECKPRIV();
  1070                                         sh4r.r[Rn] -= 4;
  1071                                         CHECKWALIGN32( sh4r.r[Rn] );
  1072                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
  1074                                         break;
  1075                                     case 0x4:
  1076                                         { /* STC.L SPC, @-Rn */
  1077                                         uint32_t Rn = ((ir>>8)&0xF); 
  1078                                         CHECKPRIV();
  1079                                         sh4r.r[Rn] -= 4;
  1080                                         CHECKWALIGN32( sh4r.r[Rn] );
  1081                                         MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
  1083                                         break;
  1084                                     default:
  1085                                         UNDEF();
  1086                                         break;
  1088                                 break;
  1089                             case 0x1:
  1090                                 { /* STC.L Rm_BANK, @-Rn */
  1091                                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); 
  1092                                 CHECKPRIV();
  1093                                 sh4r.r[Rn] -= 4;
  1094                                 CHECKWALIGN32( sh4r.r[Rn] );
  1095                                 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
  1097                                 break;
  1099                         break;
  1100                     case 0x4:
  1101                         switch( (ir&0xF0) >> 4 ) {
  1102                             case 0x0:
  1103                                 { /* ROTL Rn */
  1104                                 uint32_t Rn = ((ir>>8)&0xF); 
  1105                                 sh4r.t = sh4r.r[Rn] >> 31;
  1106                                 sh4r.r[Rn] <<= 1;
  1107                                 sh4r.r[Rn] |= sh4r.t;
  1109                                 break;
  1110                             case 0x2:
  1111                                 { /* ROTCL Rn */
  1112                                 uint32_t Rn = ((ir>>8)&0xF); 
  1113                                 tmp = sh4r.r[Rn] >> 31;
  1114                                 sh4r.r[Rn] <<= 1;
  1115                                 sh4r.r[Rn] |= sh4r.t;
  1116                                 sh4r.t = tmp;
  1118                                 break;
  1119                             default:
  1120                                 UNDEF();
  1121                                 break;
  1123                         break;
  1124                     case 0x5:
  1125                         switch( (ir&0xF0) >> 4 ) {
  1126                             case 0x0:
  1127                                 { /* ROTR Rn */
  1128                                 uint32_t Rn = ((ir>>8)&0xF); 
  1129                                 sh4r.t = sh4r.r[Rn] & 0x00000001;
  1130                                 sh4r.r[Rn] >>= 1;
  1131                                 sh4r.r[Rn] |= (sh4r.t << 31);
  1133                                 break;
  1134                             case 0x1:
  1135                                 { /* CMP/PL Rn */
  1136                                 uint32_t Rn = ((ir>>8)&0xF); 
  1137                                 sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 );
  1139                                 break;
  1140                             case 0x2:
  1141                                 { /* ROTCR Rn */
  1142                                 uint32_t Rn = ((ir>>8)&0xF); 
  1143                                 tmp = sh4r.r[Rn] & 0x00000001;
  1144                                 sh4r.r[Rn] >>= 1;
  1145                                 sh4r.r[Rn] |= (sh4r.t << 31 );
  1146                                 sh4r.t = tmp;
  1148                                 break;
  1149                             default:
  1150                                 UNDEF();
  1151                                 break;
  1153                         break;
  1154                     case 0x6:
  1155                         switch( (ir&0xF0) >> 4 ) {
  1156                             case 0x0:
  1157                                 { /* LDS.L @Rm+, MACH */
  1158                                 uint32_t Rm = ((ir>>8)&0xF); 
  1159                                 CHECKRALIGN32( sh4r.r[Rm] );
  1160                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1161                                            (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
  1162                                 sh4r.r[Rm] += 4;
  1164                                 break;
  1165                             case 0x1:
  1166                                 { /* LDS.L @Rm+, MACL */
  1167                                 uint32_t Rm = ((ir>>8)&0xF); 
  1168                                 CHECKRALIGN32( sh4r.r[Rm] );
  1169                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1170                                            (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
  1171                                 sh4r.r[Rm] += 4;
  1173                                 break;
  1174                             case 0x2:
  1175                                 { /* LDS.L @Rm+, PR */
  1176                                 uint32_t Rm = ((ir>>8)&0xF); 
  1177                                 CHECKRALIGN32( sh4r.r[Rm] );
  1178                                 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
  1179                                 sh4r.r[Rm] += 4;
  1181                                 break;
  1182                             case 0x3:
  1183                                 { /* LDC.L @Rm+, SGR */
  1184                                 uint32_t Rm = ((ir>>8)&0xF); 
  1185                                 CHECKPRIV();
  1186                                 CHECKRALIGN32( sh4r.r[Rm] );
  1187                                 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
  1188                                 sh4r.r[Rm] +=4;
  1190                                 break;
  1191                             case 0x5:
  1192                                 { /* LDS.L @Rm+, FPUL */
  1193                                 uint32_t Rm = ((ir>>8)&0xF); 
  1194                                 CHECKRALIGN32( sh4r.r[Rm] );
  1195                                 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
  1196                                 sh4r.r[Rm] +=4;
  1198                                 break;
  1199                             case 0x6:
  1200                                 { /* LDS.L @Rm+, FPSCR */
  1201                                 uint32_t Rm = ((ir>>8)&0xF); 
  1202                                 CHECKRALIGN32( sh4r.r[Rm] );
  1203                                 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
  1204                                 sh4r.r[Rm] +=4;
  1205                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1207                                 break;
  1208                             case 0xF:
  1209                                 { /* LDC.L @Rm+, DBR */
  1210                                 uint32_t Rm = ((ir>>8)&0xF); 
  1211                                 CHECKPRIV();
  1212                                 CHECKRALIGN32( sh4r.r[Rm] );
  1213                                 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
  1214                                 sh4r.r[Rm] +=4;
  1216                                 break;
  1217                             default:
  1218                                 UNDEF();
  1219                                 break;
  1221                         break;
  1222                     case 0x7:
  1223                         switch( (ir&0x80) >> 7 ) {
  1224                             case 0x0:
  1225                                 switch( (ir&0x70) >> 4 ) {
  1226                                     case 0x0:
  1227                                         { /* LDC.L @Rm+, SR */
  1228                                         uint32_t Rm = ((ir>>8)&0xF); 
  1229                                         CHECKSLOTILLEGAL();
  1230                                         CHECKPRIV();
  1231                                         CHECKWALIGN32( sh4r.r[Rm] );
  1232                                         sh4_write_sr( MEM_READ_LONG(sh4r.r[Rm]) );
  1233                                         sh4r.r[Rm] +=4;
  1235                                         break;
  1236                                     case 0x1:
  1237                                         { /* LDC.L @Rm+, GBR */
  1238                                         uint32_t Rm = ((ir>>8)&0xF); 
  1239                                         CHECKRALIGN32( sh4r.r[Rm] );
  1240                                         sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
  1241                                         sh4r.r[Rm] +=4;
  1243                                         break;
  1244                                     case 0x2:
  1245                                         { /* LDC.L @Rm+, VBR */
  1246                                         uint32_t Rm = ((ir>>8)&0xF); 
  1247                                         CHECKPRIV();
  1248                                         CHECKRALIGN32( sh4r.r[Rm] );
  1249                                         sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
  1250                                         sh4r.r[Rm] +=4;
  1252                                         break;
  1253                                     case 0x3:
  1254                                         { /* LDC.L @Rm+, SSR */
  1255                                         uint32_t Rm = ((ir>>8)&0xF); 
  1256                                         CHECKPRIV();
  1257                                         CHECKRALIGN32( sh4r.r[Rm] );
  1258                                         sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
  1259                                         sh4r.r[Rm] +=4;
  1261                                         break;
  1262                                     case 0x4:
  1263                                         { /* LDC.L @Rm+, SPC */
  1264                                         uint32_t Rm = ((ir>>8)&0xF); 
  1265                                         CHECKPRIV();
  1266                                         CHECKRALIGN32( sh4r.r[Rm] );
  1267                                         sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
  1268                                         sh4r.r[Rm] +=4;
  1270                                         break;
  1271                                     default:
  1272                                         UNDEF();
  1273                                         break;
  1275                                 break;
  1276                             case 0x1:
  1277                                 { /* LDC.L @Rm+, Rn_BANK */
  1278                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1279                                 CHECKPRIV();
  1280                                 CHECKRALIGN32( sh4r.r[Rm] );
  1281                                 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
  1282                                 sh4r.r[Rm] += 4;
  1284                                 break;
  1286                         break;
  1287                     case 0x8:
  1288                         switch( (ir&0xF0) >> 4 ) {
  1289                             case 0x0:
  1290                                 { /* SHLL2 Rn */
  1291                                 uint32_t Rn = ((ir>>8)&0xF); 
  1292                                 sh4r.r[Rn] <<= 2;
  1294                                 break;
  1295                             case 0x1:
  1296                                 { /* SHLL8 Rn */
  1297                                 uint32_t Rn = ((ir>>8)&0xF); 
  1298                                 sh4r.r[Rn] <<= 8;
  1300                                 break;
  1301                             case 0x2:
  1302                                 { /* SHLL16 Rn */
  1303                                 uint32_t Rn = ((ir>>8)&0xF); 
  1304                                 sh4r.r[Rn] <<= 16;
  1306                                 break;
  1307                             default:
  1308                                 UNDEF();
  1309                                 break;
  1311                         break;
  1312                     case 0x9:
  1313                         switch( (ir&0xF0) >> 4 ) {
  1314                             case 0x0:
  1315                                 { /* SHLR2 Rn */
  1316                                 uint32_t Rn = ((ir>>8)&0xF); 
  1317                                 sh4r.r[Rn] >>= 2;
  1319                                 break;
  1320                             case 0x1:
  1321                                 { /* SHLR8 Rn */
  1322                                 uint32_t Rn = ((ir>>8)&0xF); 
  1323                                 sh4r.r[Rn] >>= 8;
  1325                                 break;
  1326                             case 0x2:
  1327                                 { /* SHLR16 Rn */
  1328                                 uint32_t Rn = ((ir>>8)&0xF); 
  1329                                 sh4r.r[Rn] >>= 16;
  1331                                 break;
  1332                             default:
  1333                                 UNDEF();
  1334                                 break;
  1336                         break;
  1337                     case 0xA:
  1338                         switch( (ir&0xF0) >> 4 ) {
  1339                             case 0x0:
  1340                                 { /* LDS Rm, MACH */
  1341                                 uint32_t Rm = ((ir>>8)&0xF); 
  1342                                 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
  1343                                            (((uint64_t)sh4r.r[Rm])<<32);
  1345                                 break;
  1346                             case 0x1:
  1347                                 { /* LDS Rm, MACL */
  1348                                 uint32_t Rm = ((ir>>8)&0xF); 
  1349                                 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1350                                            (uint64_t)((uint32_t)(sh4r.r[Rm]));
  1352                                 break;
  1353                             case 0x2:
  1354                                 { /* LDS Rm, PR */
  1355                                 uint32_t Rm = ((ir>>8)&0xF); 
  1356                                 sh4r.pr = sh4r.r[Rm];
  1358                                 break;
  1359                             case 0x3:
  1360                                 { /* LDC Rm, SGR */
  1361                                 uint32_t Rm = ((ir>>8)&0xF); 
  1362                                 CHECKPRIV();
  1363                                 sh4r.sgr = sh4r.r[Rm];
  1365                                 break;
  1366                             case 0x5:
  1367                                 { /* LDS Rm, FPUL */
  1368                                 uint32_t Rm = ((ir>>8)&0xF); 
  1369                                 sh4r.fpul = sh4r.r[Rm];
  1371                                 break;
  1372                             case 0x6:
  1373                                 { /* LDS Rm, FPSCR */
  1374                                 uint32_t Rm = ((ir>>8)&0xF); 
  1375                                 sh4r.fpscr = sh4r.r[Rm]; 
  1376                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  1378                                 break;
  1379                             case 0xF:
  1380                                 { /* LDC Rm, DBR */
  1381                                 uint32_t Rm = ((ir>>8)&0xF); 
  1382                                 CHECKPRIV();
  1383                                 sh4r.dbr = sh4r.r[Rm];
  1385                                 break;
  1386                             default:
  1387                                 UNDEF();
  1388                                 break;
  1390                         break;
  1391                     case 0xB:
  1392                         switch( (ir&0xF0) >> 4 ) {
  1393                             case 0x0:
  1394                                 { /* JSR @Rn */
  1395                                 uint32_t Rn = ((ir>>8)&0xF); 
  1396                                 CHECKDEST( sh4r.r[Rn] );
  1397                                 CHECKSLOTILLEGAL();
  1398                                 sh4r.in_delay_slot = 1;
  1399                                 sh4r.pc = sh4r.new_pc;
  1400                                 sh4r.new_pc = sh4r.r[Rn];
  1401                                 sh4r.pr = pc + 4;
  1402                                 TRACE_CALL( pc, sh4r.new_pc );
  1403                                 return TRUE;
  1405                                 break;
  1406                             case 0x1:
  1407                                 { /* TAS.B @Rn */
  1408                                 uint32_t Rn = ((ir>>8)&0xF); 
  1409                                 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
  1410                                 sh4r.t = ( tmp == 0 ? 1 : 0 );
  1411                                 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
  1413                                 break;
  1414                             case 0x2:
  1415                                 { /* JMP @Rn */
  1416                                 uint32_t Rn = ((ir>>8)&0xF); 
  1417                                 CHECKDEST( sh4r.r[Rn] );
  1418                                 CHECKSLOTILLEGAL();
  1419                                 sh4r.in_delay_slot = 1;
  1420                                 sh4r.pc = sh4r.new_pc;
  1421                                 sh4r.new_pc = sh4r.r[Rn];
  1422                                 return TRUE;
  1424                                 break;
  1425                             default:
  1426                                 UNDEF();
  1427                                 break;
  1429                         break;
  1430                     case 0xC:
  1431                         { /* SHAD Rm, Rn */
  1432                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1433                         tmp = sh4r.r[Rm];
  1434                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1435                         else if( (tmp & 0x1F) == 0 )  
  1436                             sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
  1437                         else 
  1438                     	sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
  1440                         break;
  1441                     case 0xD:
  1442                         { /* SHLD Rm, Rn */
  1443                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1444                         tmp = sh4r.r[Rm];
  1445                         if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
  1446                         else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
  1447                         else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
  1449                         break;
  1450                     case 0xE:
  1451                         switch( (ir&0x80) >> 7 ) {
  1452                             case 0x0:
  1453                                 switch( (ir&0x70) >> 4 ) {
  1454                                     case 0x0:
  1455                                         { /* LDC Rm, SR */
  1456                                         uint32_t Rm = ((ir>>8)&0xF); 
  1457                                         CHECKSLOTILLEGAL();
  1458                                         CHECKPRIV();
  1459                                         sh4_write_sr( sh4r.r[Rm] );
  1461                                         break;
  1462                                     case 0x1:
  1463                                         { /* LDC Rm, GBR */
  1464                                         uint32_t Rm = ((ir>>8)&0xF); 
  1465                                         sh4r.gbr = sh4r.r[Rm];
  1467                                         break;
  1468                                     case 0x2:
  1469                                         { /* LDC Rm, VBR */
  1470                                         uint32_t Rm = ((ir>>8)&0xF); 
  1471                                         CHECKPRIV();
  1472                                         sh4r.vbr = sh4r.r[Rm];
  1474                                         break;
  1475                                     case 0x3:
  1476                                         { /* LDC Rm, SSR */
  1477                                         uint32_t Rm = ((ir>>8)&0xF); 
  1478                                         CHECKPRIV();
  1479                                         sh4r.ssr = sh4r.r[Rm];
  1481                                         break;
  1482                                     case 0x4:
  1483                                         { /* LDC Rm, SPC */
  1484                                         uint32_t Rm = ((ir>>8)&0xF); 
  1485                                         CHECKPRIV();
  1486                                         sh4r.spc = sh4r.r[Rm];
  1488                                         break;
  1489                                     default:
  1490                                         UNDEF();
  1491                                         break;
  1493                                 break;
  1494                             case 0x1:
  1495                                 { /* LDC Rm, Rn_BANK */
  1496                                 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); 
  1497                                 CHECKPRIV();
  1498                                 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
  1500                                 break;
  1502                         break;
  1503                     case 0xF:
  1504                         { /* MAC.W @Rm+, @Rn+ */
  1505                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1506                         CHECKRALIGN16( sh4r.r[Rn] );
  1507                         CHECKRALIGN16( sh4r.r[Rm] );
  1508                         int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
  1509                         sh4r.r[Rn] += 2;
  1510                         stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
  1511                         sh4r.r[Rm] += 2;
  1512                         if( sh4r.s ) {
  1513                     	int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
  1514                     	if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
  1515                     	    sh4r.mac = 0x000000017FFFFFFFLL;
  1516                     	} else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
  1517                     	    sh4r.mac = 0x0000000180000000LL;
  1518                     	} else {
  1519                     	    sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
  1520                     		((uint32_t)(sh4r.mac + stmp));
  1522                         } else {
  1523                     	sh4r.mac += SIGNEXT32(stmp);
  1526                         break;
  1528                 break;
  1529             case 0x5:
  1530                 { /* MOV.L @(disp, Rm), Rn */
  1531                 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; 
  1532                 tmp = sh4r.r[Rm] + disp;
  1533                 CHECKRALIGN32( tmp );
  1534                 sh4r.r[Rn] = MEM_READ_LONG( tmp );
  1536                 break;
  1537             case 0x6:
  1538                 switch( ir&0xF ) {
  1539                     case 0x0:
  1540                         { /* MOV.B @Rm, Rn */
  1541                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1542                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] );
  1544                         break;
  1545                     case 0x1:
  1546                         { /* MOV.W @Rm, Rn */
  1547                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1548                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] );
  1550                         break;
  1551                     case 0x2:
  1552                         { /* MOV.L @Rm, Rn */
  1553                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1554                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] );
  1556                         break;
  1557                     case 0x3:
  1558                         { /* MOV Rm, Rn */
  1559                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1560                         sh4r.r[Rn] = sh4r.r[Rm];
  1562                         break;
  1563                     case 0x4:
  1564                         { /* MOV.B @Rm+, Rn */
  1565                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1566                         sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++;
  1568                         break;
  1569                     case 0x5:
  1570                         { /* MOV.W @Rm+, Rn */
  1571                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1572                         CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2;
  1574                         break;
  1575                     case 0x6:
  1576                         { /* MOV.L @Rm+, Rn */
  1577                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1578                         CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4;
  1580                         break;
  1581                     case 0x7:
  1582                         { /* NOT Rm, Rn */
  1583                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1584                         sh4r.r[Rn] = ~sh4r.r[Rm];
  1586                         break;
  1587                     case 0x8:
  1588                         { /* SWAP.B Rm, Rn */
  1589                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1590                         sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8);
  1592                         break;
  1593                     case 0x9:
  1594                         { /* SWAP.W Rm, Rn */
  1595                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1596                         sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16);
  1598                         break;
  1599                     case 0xA:
  1600                         { /* NEGC Rm, Rn */
  1601                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1602                         tmp = 0 - sh4r.r[Rm];
  1603                         sh4r.r[Rn] = tmp - sh4r.t;
  1604                         sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
  1606                         break;
  1607                     case 0xB:
  1608                         { /* NEG Rm, Rn */
  1609                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1610                         sh4r.r[Rn] = 0 - sh4r.r[Rm];
  1612                         break;
  1613                     case 0xC:
  1614                         { /* EXTU.B Rm, Rn */
  1615                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1616                         sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF;
  1618                         break;
  1619                     case 0xD:
  1620                         { /* EXTU.W Rm, Rn */
  1621                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1622                         sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF;
  1624                         break;
  1625                     case 0xE:
  1626                         { /* EXTS.B Rm, Rn */
  1627                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1628                         sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF );
  1630                         break;
  1631                     case 0xF:
  1632                         { /* EXTS.W Rm, Rn */
  1633                         uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1634                         sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF );
  1636                         break;
  1638                 break;
  1639             case 0x7:
  1640                 { /* ADD #imm, Rn */
  1641                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1642                 sh4r.r[Rn] += imm;
  1644                 break;
  1645             case 0x8:
  1646                 switch( (ir&0xF00) >> 8 ) {
  1647                     case 0x0:
  1648                         { /* MOV.B R0, @(disp, Rn) */
  1649                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1650                         MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 );
  1652                         break;
  1653                     case 0x1:
  1654                         { /* MOV.W R0, @(disp, Rn) */
  1655                         uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1656                         tmp = sh4r.r[Rn] + disp;
  1657                         CHECKWALIGN16( tmp );
  1658                         MEM_WRITE_WORD( tmp, R0 );
  1660                         break;
  1661                     case 0x4:
  1662                         { /* MOV.B @(disp, Rm), R0 */
  1663                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); 
  1664                         R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp );
  1666                         break;
  1667                     case 0x5:
  1668                         { /* MOV.W @(disp, Rm), R0 */
  1669                         uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; 
  1670                         tmp = sh4r.r[Rm] + disp;
  1671                         CHECKRALIGN16( tmp );
  1672                         R0 = MEM_READ_WORD( tmp );
  1674                         break;
  1675                     case 0x8:
  1676                         { /* CMP/EQ #imm, R0 */
  1677                         int32_t imm = SIGNEXT8(ir&0xFF); 
  1678                         sh4r.t = ( R0 == imm ? 1 : 0 );
  1680                         break;
  1681                     case 0x9:
  1682                         { /* BT disp */
  1683                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1684                         CHECKSLOTILLEGAL();
  1685                         if( sh4r.t ) {
  1686                             CHECKDEST( sh4r.pc + disp + 4 )
  1687                             sh4r.pc += disp + 4;
  1688                             sh4r.new_pc = sh4r.pc + 2;
  1689                             return TRUE;
  1692                         break;
  1693                     case 0xB:
  1694                         { /* BF disp */
  1695                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1696                         CHECKSLOTILLEGAL();
  1697                         if( !sh4r.t ) {
  1698                             CHECKDEST( sh4r.pc + disp + 4 )
  1699                             sh4r.pc += disp + 4;
  1700                             sh4r.new_pc = sh4r.pc + 2;
  1701                             return TRUE;
  1704                         break;
  1705                     case 0xD:
  1706                         { /* BT/S disp */
  1707                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1708                         CHECKSLOTILLEGAL();
  1709                         if( sh4r.t ) {
  1710                             CHECKDEST( sh4r.pc + disp + 4 )
  1711                             sh4r.in_delay_slot = 1;
  1712                             sh4r.pc = sh4r.new_pc;
  1713                             sh4r.new_pc = pc + disp + 4;
  1714                             sh4r.in_delay_slot = 1;
  1715                             return TRUE;
  1718                         break;
  1719                     case 0xF:
  1720                         { /* BF/S disp */
  1721                         int32_t disp = SIGNEXT8(ir&0xFF)<<1; 
  1722                         CHECKSLOTILLEGAL();
  1723                         if( !sh4r.t ) {
  1724                             CHECKDEST( sh4r.pc + disp + 4 )
  1725                             sh4r.in_delay_slot = 1;
  1726                             sh4r.pc = sh4r.new_pc;
  1727                             sh4r.new_pc = pc + disp + 4;
  1728                             return TRUE;
  1731                         break;
  1732                     default:
  1733                         UNDEF();
  1734                         break;
  1736                 break;
  1737             case 0x9:
  1738                 { /* MOV.W @(disp, PC), Rn */
  1739                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; 
  1740                 CHECKSLOTILLEGAL();
  1741                 tmp = pc + 4 + disp;
  1742                 sh4r.r[Rn] = MEM_READ_WORD( tmp );
  1744                 break;
  1745             case 0xA:
  1746                 { /* BRA disp */
  1747                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1748                 CHECKSLOTILLEGAL();
  1749                 CHECKDEST( sh4r.pc + disp + 4 );
  1750                 sh4r.in_delay_slot = 1;
  1751                 sh4r.pc = sh4r.new_pc;
  1752                 sh4r.new_pc = pc + 4 + disp;
  1753                 return TRUE;
  1755                 break;
  1756             case 0xB:
  1757                 { /* BSR disp */
  1758                 int32_t disp = SIGNEXT12(ir&0xFFF)<<1; 
  1759                 CHECKDEST( sh4r.pc + disp + 4 );
  1760                 CHECKSLOTILLEGAL();
  1761                 sh4r.in_delay_slot = 1;
  1762                 sh4r.pr = pc + 4;
  1763                 sh4r.pc = sh4r.new_pc;
  1764                 sh4r.new_pc = pc + 4 + disp;
  1765                 TRACE_CALL( pc, sh4r.new_pc );
  1766                 return TRUE;
  1768                 break;
  1769             case 0xC:
  1770                 switch( (ir&0xF00) >> 8 ) {
  1771                     case 0x0:
  1772                         { /* MOV.B R0, @(disp, GBR) */
  1773                         uint32_t disp = (ir&0xFF); 
  1774                         MEM_WRITE_BYTE( sh4r.gbr + disp, R0 );
  1776                         break;
  1777                     case 0x1:
  1778                         { /* MOV.W R0, @(disp, GBR) */
  1779                         uint32_t disp = (ir&0xFF)<<1; 
  1780                         tmp = sh4r.gbr + disp;
  1781                         CHECKWALIGN16( tmp );
  1782                         MEM_WRITE_WORD( tmp, R0 );
  1784                         break;
  1785                     case 0x2:
  1786                         { /* MOV.L R0, @(disp, GBR) */
  1787                         uint32_t disp = (ir&0xFF)<<2; 
  1788                         tmp = sh4r.gbr + disp;
  1789                         CHECKWALIGN32( tmp );
  1790                         MEM_WRITE_LONG( tmp, R0 );
  1792                         break;
  1793                     case 0x3:
  1794                         { /* TRAPA #imm */
  1795                         uint32_t imm = (ir&0xFF); 
  1796                         CHECKSLOTILLEGAL();
  1797                         MMIO_WRITE( MMU, TRA, imm<<2 );
  1798                         sh4r.pc += 2;
  1799                         sh4_raise_exception( EXC_TRAP );
  1801                         break;
  1802                     case 0x4:
  1803                         { /* MOV.B @(disp, GBR), R0 */
  1804                         uint32_t disp = (ir&0xFF); 
  1805                         R0 = MEM_READ_BYTE( sh4r.gbr + disp );
  1807                         break;
  1808                     case 0x5:
  1809                         { /* MOV.W @(disp, GBR), R0 */
  1810                         uint32_t disp = (ir&0xFF)<<1; 
  1811                         tmp = sh4r.gbr + disp;
  1812                         CHECKRALIGN16( tmp );
  1813                         R0 = MEM_READ_WORD( tmp );
  1815                         break;
  1816                     case 0x6:
  1817                         { /* MOV.L @(disp, GBR), R0 */
  1818                         uint32_t disp = (ir&0xFF)<<2; 
  1819                         tmp = sh4r.gbr + disp;
  1820                         CHECKRALIGN32( tmp );
  1821                         R0 = MEM_READ_LONG( tmp );
  1823                         break;
  1824                     case 0x7:
  1825                         { /* MOVA @(disp, PC), R0 */
  1826                         uint32_t disp = (ir&0xFF)<<2; 
  1827                         CHECKSLOTILLEGAL();
  1828                         R0 = (pc&0xFFFFFFFC) + disp + 4;
  1830                         break;
  1831                     case 0x8:
  1832                         { /* TST #imm, R0 */
  1833                         uint32_t imm = (ir&0xFF); 
  1834                         sh4r.t = (R0 & imm ? 0 : 1);
  1836                         break;
  1837                     case 0x9:
  1838                         { /* AND #imm, R0 */
  1839                         uint32_t imm = (ir&0xFF); 
  1840                         R0 &= imm;
  1842                         break;
  1843                     case 0xA:
  1844                         { /* XOR #imm, R0 */
  1845                         uint32_t imm = (ir&0xFF); 
  1846                         R0 ^= imm;
  1848                         break;
  1849                     case 0xB:
  1850                         { /* OR #imm, R0 */
  1851                         uint32_t imm = (ir&0xFF); 
  1852                         R0 |= imm;
  1854                         break;
  1855                     case 0xC:
  1856                         { /* TST.B #imm, @(R0, GBR) */
  1857                         uint32_t imm = (ir&0xFF); 
  1858                         sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 );
  1860                         break;
  1861                     case 0xD:
  1862                         { /* AND.B #imm, @(R0, GBR) */
  1863                         uint32_t imm = (ir&0xFF); 
  1864                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1866                         break;
  1867                     case 0xE:
  1868                         { /* XOR.B #imm, @(R0, GBR) */
  1869                         uint32_t imm = (ir&0xFF); 
  1870                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1872                         break;
  1873                     case 0xF:
  1874                         { /* OR.B #imm, @(R0, GBR) */
  1875                         uint32_t imm = (ir&0xFF); 
  1876                         MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1878                         break;
  1880                 break;
  1881             case 0xD:
  1882                 { /* MOV.L @(disp, PC), Rn */
  1883                 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; 
  1884                 CHECKSLOTILLEGAL();
  1885                 tmp = (pc&0xFFFFFFFC) + disp + 4;
  1886                 sh4r.r[Rn] = MEM_READ_LONG( tmp );
  1888                 break;
  1889             case 0xE:
  1890                 { /* MOV #imm, Rn */
  1891                 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); 
  1892                 sh4r.r[Rn] = imm;
  1894                 break;
  1895             case 0xF:
  1896                 switch( ir&0xF ) {
  1897                     case 0x0:
  1898                         { /* FADD FRm, FRn */
  1899                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1900                         CHECKFPUEN();
  1901                         if( IS_FPU_DOUBLEPREC() ) {
  1902                     	DR(FRn) += DR(FRm);
  1903                         } else {
  1904                     	FR(FRn) += FR(FRm);
  1907                         break;
  1908                     case 0x1:
  1909                         { /* FSUB FRm, FRn */
  1910                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1911                         CHECKFPUEN();
  1912                         if( IS_FPU_DOUBLEPREC() ) {
  1913                     	DR(FRn) -= DR(FRm);
  1914                         } else {
  1915                     	FR(FRn) -= FR(FRm);
  1918                         break;
  1919                     case 0x2:
  1920                         { /* FMUL FRm, FRn */
  1921                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1922                         CHECKFPUEN();
  1923                         if( IS_FPU_DOUBLEPREC() ) {
  1924                     	DR(FRn) *= DR(FRm);
  1925                         } else {
  1926                     	FR(FRn) *= FR(FRm);
  1929                         break;
  1930                     case 0x3:
  1931                         { /* FDIV FRm, FRn */
  1932                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1933                         CHECKFPUEN();
  1934                         if( IS_FPU_DOUBLEPREC() ) {
  1935                     	DR(FRn) /= DR(FRm);
  1936                         } else {
  1937                     	FR(FRn) /= FR(FRm);
  1940                         break;
  1941                     case 0x4:
  1942                         { /* FCMP/EQ FRm, FRn */
  1943                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1944                         CHECKFPUEN();
  1945                         if( IS_FPU_DOUBLEPREC() ) {
  1946                     	sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
  1947                         } else {
  1948                     	sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
  1951                         break;
  1952                     case 0x5:
  1953                         { /* FCMP/GT FRm, FRn */
  1954                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1955                         CHECKFPUEN();
  1956                         if( IS_FPU_DOUBLEPREC() ) {
  1957                     	sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
  1958                         } else {
  1959                     	sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
  1962                         break;
  1963                     case 0x6:
  1964                         { /* FMOV @(R0, Rm), FRn */
  1965                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1966                         MEM_FP_READ( sh4r.r[Rm] + R0, FRn );
  1968                         break;
  1969                     case 0x7:
  1970                         { /* FMOV FRm, @(R0, Rn) */
  1971                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1972                         MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm );
  1974                         break;
  1975                     case 0x8:
  1976                         { /* FMOV @Rm, FRn */
  1977                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1978                         MEM_FP_READ( sh4r.r[Rm], FRn );
  1980                         break;
  1981                     case 0x9:
  1982                         { /* FMOV @Rm+, FRn */
  1983                         uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); 
  1984                         MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH;
  1986                         break;
  1987                     case 0xA:
  1988                         { /* FMOV FRm, @Rn */
  1989                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1990                         MEM_FP_WRITE( sh4r.r[Rn], FRm );
  1992                         break;
  1993                     case 0xB:
  1994                         { /* FMOV FRm, @-Rn */
  1995                         uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  1996                         sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm );
  1998                         break;
  1999                     case 0xC:
  2000                         { /* FMOV FRm, FRn */
  2001                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2002                         if( IS_FPU_DOUBLESIZE() )
  2003                     	DR(FRn) = DR(FRm);
  2004                         else
  2005                     	FR(FRn) = FR(FRm);
  2007                         break;
  2008                     case 0xD:
  2009                         switch( (ir&0xF0) >> 4 ) {
  2010                             case 0x0:
  2011                                 { /* FSTS FPUL, FRn */
  2012                                 uint32_t FRn = ((ir>>8)&0xF); 
  2013                                 CHECKFPUEN(); FR(FRn) = FPULf;
  2015                                 break;
  2016                             case 0x1:
  2017                                 { /* FLDS FRm, FPUL */
  2018                                 uint32_t FRm = ((ir>>8)&0xF); 
  2019                                 CHECKFPUEN(); FPULf = FR(FRm);
  2021                                 break;
  2022                             case 0x2:
  2023                                 { /* FLOAT FPUL, FRn */
  2024                                 uint32_t FRn = ((ir>>8)&0xF); 
  2025                                 CHECKFPUEN();
  2026                                 if( IS_FPU_DOUBLEPREC() ) {
  2027                             	if( FRn&1 ) { // No, really...
  2028                             	    dtmp = (double)FPULi;
  2029                             	    FR(FRn) = *(((float *)&dtmp)+1);
  2030                             	} else {
  2031                             	    DRF(FRn>>1) = (double)FPULi;
  2033                                 } else {
  2034                             	FR(FRn) = (float)FPULi;
  2037                                 break;
  2038                             case 0x3:
  2039                                 { /* FTRC FRm, FPUL */
  2040                                 uint32_t FRm = ((ir>>8)&0xF); 
  2041                                 CHECKFPUEN();
  2042                                 if( IS_FPU_DOUBLEPREC() ) {
  2043                             	if( FRm&1 ) {
  2044                             	    dtmp = 0;
  2045                             	    *(((float *)&dtmp)+1) = FR(FRm);
  2046                             	} else {
  2047                             	    dtmp = DRF(FRm>>1);
  2049                                     if( dtmp >= MAX_INTF )
  2050                                         FPULi = MAX_INT;
  2051                                     else if( dtmp <= MIN_INTF )
  2052                                         FPULi = MIN_INT;
  2053                                     else 
  2054                                         FPULi = (int32_t)dtmp;
  2055                                 } else {
  2056                             	ftmp = FR(FRm);
  2057                             	if( ftmp >= MAX_INTF )
  2058                             	    FPULi = MAX_INT;
  2059                             	else if( ftmp <= MIN_INTF )
  2060                             	    FPULi = MIN_INT;
  2061                             	else
  2062                             	    FPULi = (int32_t)ftmp;
  2065                                 break;
  2066                             case 0x4:
  2067                                 { /* FNEG FRn */
  2068                                 uint32_t FRn = ((ir>>8)&0xF); 
  2069                                 CHECKFPUEN();
  2070                                 if( IS_FPU_DOUBLEPREC() ) {
  2071                             	DR(FRn) = -DR(FRn);
  2072                                 } else {
  2073                                     FR(FRn) = -FR(FRn);
  2076                                 break;
  2077                             case 0x5:
  2078                                 { /* FABS FRn */
  2079                                 uint32_t FRn = ((ir>>8)&0xF); 
  2080                                 CHECKFPUEN();
  2081                                 if( IS_FPU_DOUBLEPREC() ) {
  2082                             	DR(FRn) = fabs(DR(FRn));
  2083                                 } else {
  2084                                     FR(FRn) = fabsf(FR(FRn));
  2087                                 break;
  2088                             case 0x6:
  2089                                 { /* FSQRT FRn */
  2090                                 uint32_t FRn = ((ir>>8)&0xF); 
  2091                                 CHECKFPUEN();
  2092                                 if( IS_FPU_DOUBLEPREC() ) {
  2093                             	DR(FRn) = sqrt(DR(FRn));
  2094                                 } else {
  2095                                     FR(FRn) = sqrtf(FR(FRn));
  2098                                 break;
  2099                             case 0x7:
  2100                                 { /* FSRRA FRn */
  2101                                 uint32_t FRn = ((ir>>8)&0xF); 
  2102                                 CHECKFPUEN();
  2103                                 if( !IS_FPU_DOUBLEPREC() ) {
  2104                             	FR(FRn) = 1.0/sqrtf(FR(FRn));
  2107                                 break;
  2108                             case 0x8:
  2109                                 { /* FLDI0 FRn */
  2110                                 uint32_t FRn = ((ir>>8)&0xF); 
  2111                                 CHECKFPUEN();
  2112                                 if( IS_FPU_DOUBLEPREC() ) {
  2113                             	DR(FRn) = 0.0;
  2114                                 } else {
  2115                                     FR(FRn) = 0.0;
  2118                                 break;
  2119                             case 0x9:
  2120                                 { /* FLDI1 FRn */
  2121                                 uint32_t FRn = ((ir>>8)&0xF); 
  2122                                 CHECKFPUEN();
  2123                                 if( IS_FPU_DOUBLEPREC() ) {
  2124                             	DR(FRn) = 1.0;
  2125                                 } else {
  2126                                     FR(FRn) = 1.0;
  2129                                 break;
  2130                             case 0xA:
  2131                                 { /* FCNVSD FPUL, FRn */
  2132                                 uint32_t FRn = ((ir>>8)&0xF); 
  2133                                 CHECKFPUEN();
  2134                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2135                             	DR(FRn) = (double)FPULf;
  2138                                 break;
  2139                             case 0xB:
  2140                                 { /* FCNVDS FRm, FPUL */
  2141                                 uint32_t FRm = ((ir>>8)&0xF); 
  2142                                 CHECKFPUEN();
  2143                                 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
  2144                             	FPULf = (float)DR(FRm);
  2147                                 break;
  2148                             case 0xE:
  2149                                 { /* FIPR FVm, FVn */
  2150                                 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); 
  2151                                 CHECKFPUEN();
  2152                                 if( !IS_FPU_DOUBLEPREC() ) {
  2153                                     int tmp2 = FVn<<2;
  2154                                     tmp = FVm<<2;
  2155                                     FR(tmp2+3) = FR(tmp)*FR(tmp2) +
  2156                                         FR(tmp+1)*FR(tmp2+1) +
  2157                                         FR(tmp+2)*FR(tmp2+2) +
  2158                                         FR(tmp+3)*FR(tmp2+3);
  2161                                 break;
  2162                             case 0xF:
  2163                                 switch( (ir&0x100) >> 8 ) {
  2164                                     case 0x0:
  2165                                         { /* FSCA FPUL, FRn */
  2166                                         uint32_t FRn = ((ir>>9)&0x7)<<1; 
  2167                                         CHECKFPUEN();
  2168                                         if( !IS_FPU_DOUBLEPREC() ) {
  2169                                             float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
  2170                                             FR(FRn) = sinf(angle);
  2171                                             FR((FRn)+1) = cosf(angle);
  2174                                         break;
  2175                                     case 0x1:
  2176                                         switch( (ir&0x200) >> 9 ) {
  2177                                             case 0x0:
  2178                                                 { /* FTRV XMTRX, FVn */
  2179                                                 uint32_t FVn = ((ir>>10)&0x3); 
  2180                                                 CHECKFPUEN();
  2181                                                 if( !IS_FPU_DOUBLEPREC() ) {
  2182                                                     tmp = FVn<<2;
  2183                                             	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
  2184                                                     float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
  2185                                                     FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
  2186                                             	    xf[9]*fv[2] + xf[13]*fv[3];
  2187                                                     FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
  2188                                             	    xf[8]*fv[2] + xf[12]*fv[3];
  2189                                                     FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
  2190                                             	    xf[11]*fv[2] + xf[15]*fv[3];
  2191                                                     FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
  2192                                             	    xf[10]*fv[2] + xf[14]*fv[3];
  2195                                                 break;
  2196                                             case 0x1:
  2197                                                 switch( (ir&0xC00) >> 10 ) {
  2198                                                     case 0x0:
  2199                                                         { /* FSCHG */
  2200                                                         CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ;
  2202                                                         break;
  2203                                                     case 0x2:
  2204                                                         { /* FRCHG */
  2205                                                         CHECKFPUEN(); 
  2206                                                         sh4r.fpscr ^= FPSCR_FR; 
  2207                                                         sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
  2209                                                         break;
  2210                                                     case 0x3:
  2211                                                         { /* UNDEF */
  2212                                                         UNDEF(ir);
  2214                                                         break;
  2215                                                     default:
  2216                                                         UNDEF();
  2217                                                         break;
  2219                                                 break;
  2221                                         break;
  2223                                 break;
  2224                             default:
  2225                                 UNDEF();
  2226                                 break;
  2228                         break;
  2229                     case 0xE:
  2230                         { /* FMAC FR0, FRm, FRn */
  2231                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
  2232                         CHECKFPUEN();
  2233                         if( IS_FPU_DOUBLEPREC() ) {
  2234                             DR(FRn) += DR(FRm)*DR(0);
  2235                         } else {
  2236                     	FR(FRn) += FR(FRm)*FR(0);
  2239                         break;
  2240                     default:
  2241                         UNDEF();
  2242                         break;
  2244                 break;
  2247     sh4r.pc = sh4r.new_pc;
  2248     sh4r.new_pc += 2;
  2249     sh4r.in_delay_slot = 0;
  2250     return TRUE;
.