filename | src/sh4/sh4dasm.c |
changeset | 359:c588dce7ebde |
prev | 302:96b5cc24309c |
next | 430:467519b050f4 |
author | nkeynes |
date | Wed Sep 12 09:20:38 2007 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Start splitting the common SH4 parts into sh4.c, with sh4core.c to become just the emulation core. |
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1 /**
2 * $Id: sh4dasm.c,v 1.11 2007-08-23 12:33:27 nkeynes Exp $
3 *
4 * SH4 CPU definition and disassembly functions
5 *
6 * Copyright (c) 2005 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #include "sh4core.h"
20 #include "sh4dasm.h"
21 #include "mem.h"
23 #define UNIMP(ir) snprintf( buf, len, "??? " )
26 const struct reg_desc_struct sh4_reg_map[] =
27 { {"R0", REG_INT, &sh4r.r[0]}, {"R1", REG_INT, &sh4r.r[1]},
28 {"R2", REG_INT, &sh4r.r[2]}, {"R3", REG_INT, &sh4r.r[3]},
29 {"R4", REG_INT, &sh4r.r[4]}, {"R5", REG_INT, &sh4r.r[5]},
30 {"R6", REG_INT, &sh4r.r[6]}, {"R7", REG_INT, &sh4r.r[7]},
31 {"R8", REG_INT, &sh4r.r[8]}, {"R9", REG_INT, &sh4r.r[9]},
32 {"R10",REG_INT, &sh4r.r[10]}, {"R11",REG_INT, &sh4r.r[11]},
33 {"R12",REG_INT, &sh4r.r[12]}, {"R13",REG_INT, &sh4r.r[13]},
34 {"R14",REG_INT, &sh4r.r[14]}, {"R15",REG_INT, &sh4r.r[15]},
35 {"SR", REG_INT, &sh4r.sr}, {"GBR", REG_INT, &sh4r.gbr},
36 {"SSR",REG_INT, &sh4r.ssr}, {"SPC", REG_INT, &sh4r.spc},
37 {"SGR",REG_INT, &sh4r.sgr}, {"DBR", REG_INT, &sh4r.dbr},
38 {"VBR",REG_INT, &sh4r.vbr},
39 {"PC", REG_INT, &sh4r.pc}, {"PR", REG_INT, &sh4r.pr},
40 {"MACL",REG_INT, &sh4r.mac},{"MACH",REG_INT, ((uint32_t *)&sh4r.mac)+1},
41 {"FPUL", REG_INT, &sh4r.fpul}, {"FPSCR", REG_INT, &sh4r.fpscr},
42 {NULL, 0, NULL} };
45 const struct cpu_desc_struct sh4_cpu_desc =
46 { "SH4", sh4_disasm_instruction, sh4_execute_instruction, mem_has_page,
47 sh4_set_breakpoint, sh4_clear_breakpoint, sh4_get_breakpoint, 2,
48 (char *)&sh4r, sizeof(sh4r), sh4_reg_map,
49 &sh4r.pc };
51 uint32_t sh4_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode )
52 {
53 uint16_t ir = sh4_read_word(pc);
55 #define UNDEF(ir) snprintf( buf, len, "???? " );
56 #define RN(ir) ((ir&0x0F00)>>8)
57 #define RN_BANK(ir) ((ir&0x0070)>>4)
58 #define RM(ir) ((ir&0x00F0)>>4)
59 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *not* sign extended */
60 #define DISP8(ir) (ir&0x00FF)
61 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
62 #define UIMM8(ir) (ir&0x00FF)
63 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
64 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
65 #define FVN(ir) ((ir&0x0C00)>>10)
66 #define FVM(ir) ((ir&0x0300)>>8)
68 sprintf( opcode, "%02X %02X", ir&0xFF, ir>>8 );
70 switch( (ir&0xF000) >> 12 ) {
71 case 0x0:
72 switch( ir&0xF ) {
73 case 0x2:
74 switch( (ir&0x80) >> 7 ) {
75 case 0x0:
76 switch( (ir&0x70) >> 4 ) {
77 case 0x0:
78 { /* STC SR, Rn */
79 uint32_t Rn = ((ir>>8)&0xF);
80 snprintf( buf, len, "STC SR, R%d", Rn );
81 }
82 break;
83 case 0x1:
84 { /* STC GBR, Rn */
85 uint32_t Rn = ((ir>>8)&0xF);
86 snprintf( buf, len, "STC GBR, R%d", Rn );
87 }
88 break;
89 case 0x2:
90 { /* STC VBR, Rn */
91 uint32_t Rn = ((ir>>8)&0xF);
92 snprintf( buf, len, "STC VBR, R%d", Rn );
93 }
94 break;
95 case 0x3:
96 { /* STC SSR, Rn */
97 uint32_t Rn = ((ir>>8)&0xF);
98 snprintf( buf, len, "STC SSR, R%d", Rn );
99 }
100 break;
101 case 0x4:
102 { /* STC SPC, Rn */
103 uint32_t Rn = ((ir>>8)&0xF);
104 snprintf( buf, len, "STC SPC, R%d", Rn );
105 }
106 break;
107 default:
108 UNDEF();
109 break;
110 }
111 break;
112 case 0x1:
113 { /* STC Rm_BANK, Rn */
114 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
115 snprintf( buf, len, "STC R%d_BANK, R%d", Rm_BANK, Rn );
116 }
117 break;
118 }
119 break;
120 case 0x3:
121 switch( (ir&0xF0) >> 4 ) {
122 case 0x0:
123 { /* BSRF Rn */
124 uint32_t Rn = ((ir>>8)&0xF);
125 snprintf( buf, len, "BSRF R%d", Rn );
126 }
127 break;
128 case 0x2:
129 { /* BRAF Rn */
130 uint32_t Rn = ((ir>>8)&0xF);
131 snprintf( buf, len, "BRAF R%d", Rn );
132 }
133 break;
134 case 0x8:
135 { /* PREF @Rn */
136 uint32_t Rn = ((ir>>8)&0xF);
137 snprintf( buf, len, "PREF R%d", Rn );
138 }
139 break;
140 case 0x9:
141 { /* OCBI @Rn */
142 uint32_t Rn = ((ir>>8)&0xF);
143 snprintf( buf, len, "OCBI @R%d", Rn );
144 }
145 break;
146 case 0xA:
147 { /* OCBP @Rn */
148 uint32_t Rn = ((ir>>8)&0xF);
149 snprintf( buf, len, "OCBP @R%d", Rn );
150 }
151 break;
152 case 0xB:
153 { /* OCBWB @Rn */
154 uint32_t Rn = ((ir>>8)&0xF);
155 snprintf( buf, len, "OCBWB @R%d", Rn );
156 }
157 break;
158 case 0xC:
159 { /* MOVCA.L R0, @Rn */
160 uint32_t Rn = ((ir>>8)&0xF);
161 snprintf( buf, len, "MOVCA.L R0, @R%d", Rn );
162 }
163 break;
164 default:
165 UNDEF();
166 break;
167 }
168 break;
169 case 0x4:
170 { /* MOV.B Rm, @(R0, Rn) */
171 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
172 snprintf( buf, len, "MOV.B R%d, @(R0, R%d)", Rm, Rn );
173 }
174 break;
175 case 0x5:
176 { /* MOV.W Rm, @(R0, Rn) */
177 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
178 snprintf( buf, len, "MOV.W R%d, @(R0, R%d)", Rm, Rn );
179 }
180 break;
181 case 0x6:
182 { /* MOV.L Rm, @(R0, Rn) */
183 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
184 snprintf( buf, len, "MOV.L R%d, @(R0, R%d)", Rm, Rn );
185 }
186 break;
187 case 0x7:
188 { /* MUL.L Rm, Rn */
189 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
190 snprintf( buf, len, "MUL.L R%d, R%d", Rm, Rn );
191 }
192 break;
193 case 0x8:
194 switch( (ir&0xFF0) >> 4 ) {
195 case 0x0:
196 { /* CLRT */
197 snprintf( buf, len, "CLRT " );
198 }
199 break;
200 case 0x1:
201 { /* SETT */
202 snprintf( buf, len, "SETT " );
203 }
204 break;
205 case 0x2:
206 { /* CLRMAC */
207 snprintf( buf, len, "CLRMAC " );
208 }
209 break;
210 case 0x3:
211 { /* LDTLB */
212 snprintf( buf, len, "LDTLB " );
213 }
214 break;
215 case 0x4:
216 { /* CLRS */
217 snprintf( buf, len, "CLRS " );
218 }
219 break;
220 case 0x5:
221 { /* SETS */
222 snprintf( buf, len, "SETS " );
223 }
224 break;
225 default:
226 UNDEF();
227 break;
228 }
229 break;
230 case 0x9:
231 switch( (ir&0xF0) >> 4 ) {
232 case 0x0:
233 { /* NOP */
234 snprintf( buf, len, "NOP " );
235 }
236 break;
237 case 0x1:
238 { /* DIV0U */
239 snprintf( buf, len, "DIV0U " );
240 }
241 break;
242 case 0x2:
243 { /* MOVT Rn */
244 uint32_t Rn = ((ir>>8)&0xF);
245 snprintf( buf, len, "MOVT R%d", Rn );
246 }
247 break;
248 default:
249 UNDEF();
250 break;
251 }
252 break;
253 case 0xA:
254 switch( (ir&0xF0) >> 4 ) {
255 case 0x0:
256 { /* STS MACH, Rn */
257 uint32_t Rn = ((ir>>8)&0xF);
258 snprintf( buf, len, "STS MACH, R%d", Rn );
259 }
260 break;
261 case 0x1:
262 { /* STS MACL, Rn */
263 uint32_t Rn = ((ir>>8)&0xF);
264 snprintf( buf, len, "STS MACL, R%d", Rn );
265 }
266 break;
267 case 0x2:
268 { /* STS PR, Rn */
269 uint32_t Rn = ((ir>>8)&0xF);
270 snprintf( buf, len, "STS PR, R%d", Rn );
271 }
272 break;
273 case 0x3:
274 { /* STC SGR, Rn */
275 uint32_t Rn = ((ir>>8)&0xF);
276 snprintf( buf, len, "STC SGR, R%d", Rn );
277 }
278 break;
279 case 0x5:
280 { /* STS FPUL, Rn */
281 uint32_t Rn = ((ir>>8)&0xF);
282 snprintf( buf, len, "STS FPUL, R%d", Rn );
283 }
284 break;
285 case 0x6:
286 { /* STS FPSCR, Rn */
287 uint32_t Rn = ((ir>>8)&0xF);
288 snprintf( buf, len, "STS FPSCR, R%d", Rn );
289 }
290 break;
291 case 0xF:
292 { /* STC DBR, Rn */
293 uint32_t Rn = ((ir>>8)&0xF);
294 snprintf( buf, len, "STC DBR, R%d", Rn );
295 }
296 break;
297 default:
298 UNDEF();
299 break;
300 }
301 break;
302 case 0xB:
303 switch( (ir&0xFF0) >> 4 ) {
304 case 0x0:
305 { /* RTS */
306 snprintf( buf, len, "RTS " );
307 }
308 break;
309 case 0x1:
310 { /* SLEEP */
311 snprintf( buf, len, "SLEEP " );
312 }
313 break;
314 case 0x2:
315 { /* RTE */
316 snprintf( buf, len, "RTE " );
317 }
318 break;
319 default:
320 UNDEF();
321 break;
322 }
323 break;
324 case 0xC:
325 { /* MOV.B @(R0, Rm), Rn */
326 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
327 snprintf( buf, len, "MOV.B @(R0, R%d), R%d", Rm, Rn );
328 }
329 break;
330 case 0xD:
331 { /* MOV.W @(R0, Rm), Rn */
332 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
333 snprintf( buf, len, "MOV.W @(R0, R%d), R%d", Rm, Rn );
334 }
335 break;
336 case 0xE:
337 { /* MOV.L @(R0, Rm), Rn */
338 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
339 snprintf( buf, len, "MOV.L @(R0, R%d), R%d", Rm, Rn );
340 }
341 break;
342 case 0xF:
343 { /* MAC.L @Rm+, @Rn+ */
344 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
345 snprintf( buf, len, "MAC.L @R%d+, @R%d+", Rm, Rn );
346 }
347 break;
348 default:
349 UNDEF();
350 break;
351 }
352 break;
353 case 0x1:
354 { /* MOV.L Rm, @(disp, Rn) */
355 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
356 snprintf( buf, len, "MOV.L R%d, @(%d, R%d)", Rm, disp, Rn );
357 }
358 break;
359 case 0x2:
360 switch( ir&0xF ) {
361 case 0x0:
362 { /* MOV.B Rm, @Rn */
363 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
364 snprintf( buf, len, "MOV.B R%d, @R%d", Rm, Rn );
365 }
366 break;
367 case 0x1:
368 { /* MOV.W Rm, @Rn */
369 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
370 snprintf( buf, len, "MOV.W R%d, @R%d", Rm, Rn );
371 }
372 break;
373 case 0x2:
374 { /* MOV.L Rm, @Rn */
375 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
376 snprintf( buf, len, "MOV.L R%d, @R%d", Rm, Rn );
377 }
378 break;
379 case 0x4:
380 { /* MOV.B Rm, @-Rn */
381 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
382 snprintf( buf, len, "MOV.B R%d, @-R%d", Rm, Rn );
383 }
384 break;
385 case 0x5:
386 { /* MOV.W Rm, @-Rn */
387 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
388 snprintf( buf, len, "MOV.W R%d, @-R%d", Rm, Rn );
389 }
390 break;
391 case 0x6:
392 { /* MOV.L Rm, @-Rn */
393 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
394 snprintf( buf, len, "MOV.L R%d, @-R%d", Rm, Rn );
395 }
396 break;
397 case 0x7:
398 { /* DIV0S Rm, Rn */
399 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
400 snprintf( buf, len, "DIV0S R%d, R%d", Rm, Rn );
401 }
402 break;
403 case 0x8:
404 { /* TST Rm, Rn */
405 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
406 snprintf( buf, len, "TST R%d, R%d", Rm, Rn );
407 }
408 break;
409 case 0x9:
410 { /* AND Rm, Rn */
411 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
412 snprintf( buf, len, "AND R%d, R%d", Rm, Rn );
413 }
414 break;
415 case 0xA:
416 { /* XOR Rm, Rn */
417 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
418 snprintf( buf, len, "XOR R%d, R%d", Rm, Rn );
419 }
420 break;
421 case 0xB:
422 { /* OR Rm, Rn */
423 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
424 snprintf( buf, len, "OR R%d, R%d", Rm, Rn );
425 }
426 break;
427 case 0xC:
428 { /* CMP/STR Rm, Rn */
429 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
430 snprintf( buf, len, "CMP/STR R%d, R%d", Rm, Rn );
431 }
432 break;
433 case 0xD:
434 { /* XTRCT Rm, Rn */
435 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
436 snprintf( buf, len, "XTRCT R%d, R%d", Rm, Rn );
437 }
438 break;
439 case 0xE:
440 { /* MULU.W Rm, Rn */
441 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
442 snprintf( buf, len, "MULU.W R%d, R%d", Rm, Rn );
443 }
444 break;
445 case 0xF:
446 { /* MULS.W Rm, Rn */
447 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
448 snprintf( buf, len, "MULS.W R%d, R%d", Rm, Rn );
449 }
450 break;
451 default:
452 UNDEF();
453 break;
454 }
455 break;
456 case 0x3:
457 switch( ir&0xF ) {
458 case 0x0:
459 { /* CMP/EQ Rm, Rn */
460 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
461 snprintf( buf, len, "CMP/EQ R%d, R%d", Rm, Rn );
462 }
463 break;
464 case 0x2:
465 { /* CMP/HS Rm, Rn */
466 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
467 snprintf( buf, len, "CMP/HS R%d, R%d", Rm, Rn );
468 }
469 break;
470 case 0x3:
471 { /* CMP/GE Rm, Rn */
472 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
473 snprintf( buf, len, "CMP/GE R%d, R%d", Rm, Rn );
474 }
475 break;
476 case 0x4:
477 { /* DIV1 Rm, Rn */
478 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
479 snprintf( buf, len, "DIV1 R%d, R%d", Rm, Rn );
480 }
481 break;
482 case 0x5:
483 { /* DMULU.L Rm, Rn */
484 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
485 snprintf( buf, len, "DMULU.L R%d, R%d", Rm, Rn );
486 }
487 break;
488 case 0x6:
489 { /* CMP/HI Rm, Rn */
490 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
491 snprintf( buf, len, "CMP/HI R%d, R%d", Rm, Rn );
492 }
493 break;
494 case 0x7:
495 { /* CMP/GT Rm, Rn */
496 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
497 snprintf( buf, len, "CMP/GT R%d, R%d", Rm, Rn );
498 }
499 break;
500 case 0x8:
501 { /* SUB Rm, Rn */
502 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
503 snprintf( buf, len, "SUB R%d, R%d", Rm, Rn );
504 }
505 break;
506 case 0xA:
507 { /* SUBC Rm, Rn */
508 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
509 snprintf( buf, len, "SUBC R%d, R%d", Rm, Rn );
510 }
511 break;
512 case 0xB:
513 { /* SUBV Rm, Rn */
514 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
515 snprintf( buf, len, "SUBV R%d, R%d", Rm, Rn );
516 }
517 break;
518 case 0xC:
519 { /* ADD Rm, Rn */
520 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
521 snprintf( buf, len, "ADD R%d, R%d", Rm, Rn );
522 }
523 break;
524 case 0xD:
525 { /* DMULS.L Rm, Rn */
526 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
527 snprintf( buf, len, "DMULS.L R%d, R%d", Rm, Rn );
528 }
529 break;
530 case 0xE:
531 { /* ADDC Rm, Rn */
532 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
533 snprintf( buf, len, "ADDC R%d, R%d", Rm, Rn );
534 }
535 break;
536 case 0xF:
537 { /* ADDV Rm, Rn */
538 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
539 snprintf( buf, len, "ADDV R%d, R%d", Rm, Rn );
540 }
541 break;
542 default:
543 UNDEF();
544 break;
545 }
546 break;
547 case 0x4:
548 switch( ir&0xF ) {
549 case 0x0:
550 switch( (ir&0xF0) >> 4 ) {
551 case 0x0:
552 { /* SHLL Rn */
553 uint32_t Rn = ((ir>>8)&0xF);
554 snprintf( buf, len, "SHLL R%d", Rn );
555 }
556 break;
557 case 0x1:
558 { /* DT Rn */
559 uint32_t Rn = ((ir>>8)&0xF);
560 snprintf( buf, len, "DT R%d", Rn );
561 }
562 break;
563 case 0x2:
564 { /* SHAL Rn */
565 uint32_t Rn = ((ir>>8)&0xF);
566 snprintf( buf, len, "SHAL R%d", Rn );
567 }
568 break;
569 default:
570 UNDEF();
571 break;
572 }
573 break;
574 case 0x1:
575 switch( (ir&0xF0) >> 4 ) {
576 case 0x0:
577 { /* SHLR Rn */
578 uint32_t Rn = ((ir>>8)&0xF);
579 snprintf( buf, len, "SHLR R%d", Rn );
580 }
581 break;
582 case 0x1:
583 { /* CMP/PZ Rn */
584 uint32_t Rn = ((ir>>8)&0xF);
585 snprintf( buf, len, "CMP/PZ R%d", Rn );
586 }
587 break;
588 case 0x2:
589 { /* SHAR Rn */
590 uint32_t Rn = ((ir>>8)&0xF);
591 snprintf( buf, len, "SHAR R%d", Rn );
592 }
593 break;
594 default:
595 UNDEF();
596 break;
597 }
598 break;
599 case 0x2:
600 switch( (ir&0xF0) >> 4 ) {
601 case 0x0:
602 { /* STS.L MACH, @-Rn */
603 uint32_t Rn = ((ir>>8)&0xF);
604 snprintf( buf, len, "STS.L MACH, @-R%d", Rn );
605 }
606 break;
607 case 0x1:
608 { /* STS.L MACL, @-Rn */
609 uint32_t Rn = ((ir>>8)&0xF);
610 snprintf( buf, len, "STS.L MACL, @-R%d", Rn );
611 }
612 break;
613 case 0x2:
614 { /* STS.L PR, @-Rn */
615 uint32_t Rn = ((ir>>8)&0xF);
616 snprintf( buf, len, "STS.L PR, @-R%d", Rn );
617 }
618 break;
619 case 0x3:
620 { /* STC.L SGR, @-Rn */
621 uint32_t Rn = ((ir>>8)&0xF);
622 snprintf( buf, len, "STC.L SGR, @-R%d", Rn );
623 }
624 break;
625 case 0x5:
626 { /* STS.L FPUL, @-Rn */
627 uint32_t Rn = ((ir>>8)&0xF);
628 snprintf( buf, len, "STS.L FPUL, @-R%d", Rn );
629 }
630 break;
631 case 0x6:
632 { /* STS.L FPSCR, @-Rn */
633 uint32_t Rn = ((ir>>8)&0xF);
634 snprintf( buf, len, "STS.L FPSCR, @-R%d", Rn );
635 }
636 break;
637 case 0xF:
638 { /* STC.L DBR, @-Rn */
639 uint32_t Rn = ((ir>>8)&0xF);
640 snprintf( buf, len, "STC.L DBR, @-R%d", Rn );
641 }
642 break;
643 default:
644 UNDEF();
645 break;
646 }
647 break;
648 case 0x3:
649 switch( (ir&0x80) >> 7 ) {
650 case 0x0:
651 switch( (ir&0x70) >> 4 ) {
652 case 0x0:
653 { /* STC.L SR, @-Rn */
654 uint32_t Rn = ((ir>>8)&0xF);
655 snprintf( buf, len, "STC.L SR, @-R%d", Rn );
656 }
657 break;
658 case 0x1:
659 { /* STC.L GBR, @-Rn */
660 uint32_t Rn = ((ir>>8)&0xF);
661 snprintf( buf, len, "STC.L GBR, @-R%d", Rn );
662 }
663 break;
664 case 0x2:
665 { /* STC.L VBR, @-Rn */
666 uint32_t Rn = ((ir>>8)&0xF);
667 snprintf( buf, len, "STC.L VBR, @-R%d", Rn );
668 }
669 break;
670 case 0x3:
671 { /* STC.L SSR, @-Rn */
672 uint32_t Rn = ((ir>>8)&0xF);
673 snprintf( buf, len, "STC.L SSR, @-R%d", Rn );
674 }
675 break;
676 case 0x4:
677 { /* STC.L SPC, @-Rn */
678 uint32_t Rn = ((ir>>8)&0xF);
679 snprintf( buf, len, "STC.L SPC, @-R%d", Rn );
680 }
681 break;
682 default:
683 UNDEF();
684 break;
685 }
686 break;
687 case 0x1:
688 { /* STC.L Rm_BANK, @-Rn */
689 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);
690 snprintf( buf, len, "STC.L @-R%d_BANK, @-R%d", Rm_BANK, Rn );
691 }
692 break;
693 }
694 break;
695 case 0x4:
696 switch( (ir&0xF0) >> 4 ) {
697 case 0x0:
698 { /* ROTL Rn */
699 uint32_t Rn = ((ir>>8)&0xF);
700 snprintf( buf, len, "ROTL R%d", Rn );
701 }
702 break;
703 case 0x2:
704 { /* ROTCL Rn */
705 uint32_t Rn = ((ir>>8)&0xF);
706 snprintf( buf, len, "ROTCL R%d", Rn );
707 }
708 break;
709 default:
710 UNDEF();
711 break;
712 }
713 break;
714 case 0x5:
715 switch( (ir&0xF0) >> 4 ) {
716 case 0x0:
717 { /* ROTR Rn */
718 uint32_t Rn = ((ir>>8)&0xF);
719 snprintf( buf, len, "ROTR R%d", Rn );
720 }
721 break;
722 case 0x1:
723 { /* CMP/PL Rn */
724 uint32_t Rn = ((ir>>8)&0xF);
725 snprintf( buf, len, "CMP/PL R%d", Rn );
726 }
727 break;
728 case 0x2:
729 { /* ROTCR Rn */
730 uint32_t Rn = ((ir>>8)&0xF);
731 snprintf( buf, len, "ROTCR R%d", Rn );
732 }
733 break;
734 default:
735 UNDEF();
736 break;
737 }
738 break;
739 case 0x6:
740 switch( (ir&0xF0) >> 4 ) {
741 case 0x0:
742 { /* LDS.L @Rm+, MACH */
743 uint32_t Rm = ((ir>>8)&0xF);
744 snprintf( buf, len, "LDS.L @R%d+, MACH", Rm );
745 }
746 break;
747 case 0x1:
748 { /* LDS.L @Rm+, MACL */
749 uint32_t Rm = ((ir>>8)&0xF);
750 snprintf( buf, len, "LDS.L @R%d+, MACL", Rm );
751 }
752 break;
753 case 0x2:
754 { /* LDS.L @Rm+, PR */
755 uint32_t Rm = ((ir>>8)&0xF);
756 snprintf( buf, len, "LDS.L @R%d+, PR", Rm );
757 }
758 break;
759 case 0x3:
760 { /* LDC.L @Rm+, SGR */
761 uint32_t Rm = ((ir>>8)&0xF);
762 snprintf( buf, len, "LDC.L @R%d+, SGR", Rm );
763 }
764 break;
765 case 0x5:
766 { /* LDS.L @Rm+, FPUL */
767 uint32_t Rm = ((ir>>8)&0xF);
768 snprintf( buf, len, "LDS.L @R%d+, FPUL", Rm );
769 }
770 break;
771 case 0x6:
772 { /* LDS.L @Rm+, FPSCR */
773 uint32_t Rm = ((ir>>8)&0xF);
774 snprintf( buf, len, "LDS.L @R%d+, FPSCR", Rm );
775 }
776 break;
777 case 0xF:
778 { /* LDC.L @Rm+, DBR */
779 uint32_t Rm = ((ir>>8)&0xF);
780 snprintf( buf, len, "LDC.L @R%d+, DBR", Rm );
781 }
782 break;
783 default:
784 UNDEF();
785 break;
786 }
787 break;
788 case 0x7:
789 switch( (ir&0x80) >> 7 ) {
790 case 0x0:
791 switch( (ir&0x70) >> 4 ) {
792 case 0x0:
793 { /* LDC.L @Rm+, SR */
794 uint32_t Rm = ((ir>>8)&0xF);
795 snprintf( buf, len, "LDC.L @R%d+, SR", Rm );
796 }
797 break;
798 case 0x1:
799 { /* LDC.L @Rm+, GBR */
800 uint32_t Rm = ((ir>>8)&0xF);
801 snprintf( buf, len, "LDC.L @R%d+, GBR", Rm );
802 }
803 break;
804 case 0x2:
805 { /* LDC.L @Rm+, VBR */
806 uint32_t Rm = ((ir>>8)&0xF);
807 snprintf( buf, len, "LDC.L @R%d+, VBR", Rm );
808 }
809 break;
810 case 0x3:
811 { /* LDC.L @Rm+, SSR */
812 uint32_t Rm = ((ir>>8)&0xF);
813 snprintf( buf, len, "LDC.L @R%d+, SSR", Rm );
814 }
815 break;
816 case 0x4:
817 { /* LDC.L @Rm+, SPC */
818 uint32_t Rm = ((ir>>8)&0xF);
819 snprintf( buf, len, "LDC.L @R%d+, SPC", Rm );
820 }
821 break;
822 default:
823 UNDEF();
824 break;
825 }
826 break;
827 case 0x1:
828 { /* LDC.L @Rm+, Rn_BANK */
829 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
830 snprintf( buf, len, "LDC.L @R%d+, @R%d+_BANK", Rm, Rn_BANK );
831 }
832 break;
833 }
834 break;
835 case 0x8:
836 switch( (ir&0xF0) >> 4 ) {
837 case 0x0:
838 { /* SHLL2 Rn */
839 uint32_t Rn = ((ir>>8)&0xF);
840 snprintf( buf, len, "SHLL2 R%d", Rn );
841 }
842 break;
843 case 0x1:
844 { /* SHLL8 Rn */
845 uint32_t Rn = ((ir>>8)&0xF);
846 snprintf( buf, len, "SHLL8 R%d", Rn );
847 }
848 break;
849 case 0x2:
850 { /* SHLL16 Rn */
851 uint32_t Rn = ((ir>>8)&0xF);
852 snprintf( buf, len, "SHLL16 R%d", Rn );
853 }
854 break;
855 default:
856 UNDEF();
857 break;
858 }
859 break;
860 case 0x9:
861 switch( (ir&0xF0) >> 4 ) {
862 case 0x0:
863 { /* SHLR2 Rn */
864 uint32_t Rn = ((ir>>8)&0xF);
865 snprintf( buf, len, "SHLR2 R%d", Rn );
866 }
867 break;
868 case 0x1:
869 { /* SHLR8 Rn */
870 uint32_t Rn = ((ir>>8)&0xF);
871 snprintf( buf, len, "SHLR8 R%d", Rn );
872 }
873 break;
874 case 0x2:
875 { /* SHLR16 Rn */
876 uint32_t Rn = ((ir>>8)&0xF);
877 snprintf( buf, len, "SHLR16 R%d", Rn );
878 }
879 break;
880 default:
881 UNDEF();
882 break;
883 }
884 break;
885 case 0xA:
886 switch( (ir&0xF0) >> 4 ) {
887 case 0x0:
888 { /* LDS Rm, MACH */
889 uint32_t Rm = ((ir>>8)&0xF);
890 snprintf( buf, len, "LDS R%d, MACH", Rm );
891 }
892 break;
893 case 0x1:
894 { /* LDS Rm, MACL */
895 uint32_t Rm = ((ir>>8)&0xF);
896 snprintf( buf, len, "LDS R%d, MACL", Rm );
897 }
898 break;
899 case 0x2:
900 { /* LDS Rm, PR */
901 uint32_t Rm = ((ir>>8)&0xF);
902 snprintf( buf, len, "LDS R%d, PR", Rm );
903 }
904 break;
905 case 0x3:
906 { /* LDC Rm, SGR */
907 uint32_t Rm = ((ir>>8)&0xF);
908 snprintf( buf, len, "LDC R%d, SGR", Rm );
909 }
910 break;
911 case 0x5:
912 { /* LDS Rm, FPUL */
913 uint32_t Rm = ((ir>>8)&0xF);
914 snprintf( buf, len, "LDS R%d, FPUL", Rm );
915 }
916 break;
917 case 0x6:
918 { /* LDS Rm, FPSCR */
919 uint32_t Rm = ((ir>>8)&0xF);
920 snprintf( buf, len, "LDS R%d, FPSCR", Rm );
921 }
922 break;
923 case 0xF:
924 { /* LDC Rm, DBR */
925 uint32_t Rm = ((ir>>8)&0xF);
926 snprintf( buf, len, "LDC R%d, DBR", Rm );
927 }
928 break;
929 default:
930 UNDEF();
931 break;
932 }
933 break;
934 case 0xB:
935 switch( (ir&0xF0) >> 4 ) {
936 case 0x0:
937 { /* JSR @Rn */
938 uint32_t Rn = ((ir>>8)&0xF);
939 snprintf( buf, len, "JSR @R%d", Rn );
940 }
941 break;
942 case 0x1:
943 { /* TAS.B @Rn */
944 uint32_t Rn = ((ir>>8)&0xF);
945 snprintf( buf, len, "TAS.B R%d", Rn );
946 }
947 break;
948 case 0x2:
949 { /* JMP @Rn */
950 uint32_t Rn = ((ir>>8)&0xF);
951 snprintf( buf, len, "JMP @R%d", Rn );
952 }
953 break;
954 default:
955 UNDEF();
956 break;
957 }
958 break;
959 case 0xC:
960 { /* SHAD Rm, Rn */
961 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
962 snprintf( buf, len, "SHAD R%d, R%d", Rm, Rn );
963 }
964 break;
965 case 0xD:
966 { /* SHLD Rm, Rn */
967 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
968 snprintf( buf, len, "SHLD R%d, R%d", Rm, Rn );
969 }
970 break;
971 case 0xE:
972 switch( (ir&0x80) >> 7 ) {
973 case 0x0:
974 switch( (ir&0x70) >> 4 ) {
975 case 0x0:
976 { /* LDC Rm, SR */
977 uint32_t Rm = ((ir>>8)&0xF);
978 snprintf( buf, len, "LDC R%d, SR", Rm );
979 }
980 break;
981 case 0x1:
982 { /* LDC Rm, GBR */
983 uint32_t Rm = ((ir>>8)&0xF);
984 snprintf( buf, len, "LDC R%d, GBR", Rm );
985 }
986 break;
987 case 0x2:
988 { /* LDC Rm, VBR */
989 uint32_t Rm = ((ir>>8)&0xF);
990 snprintf( buf, len, "LDC R%d, VBR", Rm );
991 }
992 break;
993 case 0x3:
994 { /* LDC Rm, SSR */
995 uint32_t Rm = ((ir>>8)&0xF);
996 snprintf( buf, len, "LDC R%d, SSR", Rm );
997 }
998 break;
999 case 0x4:
1000 { /* LDC Rm, SPC */
1001 uint32_t Rm = ((ir>>8)&0xF);
1002 snprintf( buf, len, "LDC R%d, SPC", Rm );
1003 }
1004 break;
1005 default:
1006 UNDEF();
1007 break;
1008 }
1009 break;
1010 case 0x1:
1011 { /* LDC Rm, Rn_BANK */
1012 uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);
1013 snprintf( buf, len, "LDC R%d, R%d_BANK", Rm, Rn_BANK );
1014 }
1015 break;
1016 }
1017 break;
1018 case 0xF:
1019 { /* MAC.W @Rm+, @Rn+ */
1020 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1021 snprintf( buf, len, "MAC.W @R%d+, @R%d+", Rm, Rn );
1022 }
1023 break;
1024 }
1025 break;
1026 case 0x5:
1027 { /* MOV.L @(disp, Rm), Rn */
1028 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;
1029 snprintf( buf, len, "MOV.L @(%d, R%d), @R%d", disp, Rm, Rn );
1030 }
1031 break;
1032 case 0x6:
1033 switch( ir&0xF ) {
1034 case 0x0:
1035 { /* MOV.B @Rm, Rn */
1036 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1037 snprintf( buf, len, "MOV.B @R%d, R%d", Rm, Rn );
1038 }
1039 break;
1040 case 0x1:
1041 { /* MOV.W @Rm, Rn */
1042 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1043 snprintf( buf, len, "MOV.W @R%d, R%d", Rm, Rn );
1044 }
1045 break;
1046 case 0x2:
1047 { /* MOV.L @Rm, Rn */
1048 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1049 snprintf( buf, len, "MOV.L @R%d, R%d", Rm, Rn );
1050 }
1051 break;
1052 case 0x3:
1053 { /* MOV Rm, Rn */
1054 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1055 snprintf( buf, len, "MOV R%d, R%d", Rm, Rn );
1056 }
1057 break;
1058 case 0x4:
1059 { /* MOV.B @Rm+, Rn */
1060 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1061 snprintf( buf, len, "MOV.B @R%d+, R%d", Rm, Rn );
1062 }
1063 break;
1064 case 0x5:
1065 { /* MOV.W @Rm+, Rn */
1066 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1067 snprintf( buf, len, "MOV.W @R%d+, R%d", Rm, Rn );
1068 }
1069 break;
1070 case 0x6:
1071 { /* MOV.L @Rm+, Rn */
1072 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1073 snprintf( buf, len, "MOV.L @R%d+, R%d", Rm, Rn );
1074 }
1075 break;
1076 case 0x7:
1077 { /* NOT Rm, Rn */
1078 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1079 snprintf( buf, len, "NOT R%d, R%d", Rm, Rn );
1080 }
1081 break;
1082 case 0x8:
1083 { /* SWAP.B Rm, Rn */
1084 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1085 snprintf( buf, len, "SWAP.B R%d, R%d", Rm, Rn );
1086 }
1087 break;
1088 case 0x9:
1089 { /* SWAP.W Rm, Rn */
1090 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1091 snprintf( buf, len, "SWAP.W R%d, R%d", Rm, Rn );
1092 }
1093 break;
1094 case 0xA:
1095 { /* NEGC Rm, Rn */
1096 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1097 snprintf( buf, len, "NEGC R%d, R%d", Rm, Rn );
1098 }
1099 break;
1100 case 0xB:
1101 { /* NEG Rm, Rn */
1102 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1103 snprintf( buf, len, "NEG R%d, R%d", Rm, Rn );
1104 }
1105 break;
1106 case 0xC:
1107 { /* EXTU.B Rm, Rn */
1108 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1109 snprintf( buf, len, "EXTU.B R%d, R%d", Rm, Rn );
1110 }
1111 break;
1112 case 0xD:
1113 { /* EXTU.W Rm, Rn */
1114 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1115 snprintf( buf, len, "EXTU.W R%d, R%d", Rm, Rn );
1116 }
1117 break;
1118 case 0xE:
1119 { /* EXTS.B Rm, Rn */
1120 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1121 snprintf( buf, len, "EXTS.B R%d, R%d", Rm, Rn );
1122 }
1123 break;
1124 case 0xF:
1125 { /* EXTS.W Rm, Rn */
1126 uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1127 snprintf( buf, len, "EXTS.W R%d, R%d", Rm, Rn );
1128 }
1129 break;
1130 }
1131 break;
1132 case 0x7:
1133 { /* ADD #imm, Rn */
1134 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1135 snprintf( buf, len, "ADD #%d, R%d", imm, Rn );
1136 }
1137 break;
1138 case 0x8:
1139 switch( (ir&0xF00) >> 8 ) {
1140 case 0x0:
1141 { /* MOV.B R0, @(disp, Rn) */
1142 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1143 snprintf( buf, len, "MOV.B R0, @(%d, R%d)", disp, Rn );
1144 }
1145 break;
1146 case 0x1:
1147 { /* MOV.W R0, @(disp, Rn) */
1148 uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1149 snprintf( buf, len, "MOV.W R0, @(%d, Rn)", disp, Rn );
1150 }
1151 break;
1152 case 0x4:
1153 { /* MOV.B @(disp, Rm), R0 */
1154 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);
1155 snprintf( buf, len, "MOV.B @(%d, R%d), R0", disp, Rm );
1156 }
1157 break;
1158 case 0x5:
1159 { /* MOV.W @(disp, Rm), R0 */
1160 uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;
1161 snprintf( buf, len, "MOV.W @(%d, R%d), R0", disp, Rm );
1162 }
1163 break;
1164 case 0x8:
1165 { /* CMP/EQ #imm, R0 */
1166 int32_t imm = SIGNEXT8(ir&0xFF);
1167 snprintf( buf, len, "CMP/EQ #%d, R0", imm );
1168 }
1169 break;
1170 case 0x9:
1171 { /* BT disp */
1172 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1173 snprintf( buf, len, "BT $%xh", disp+pc+4 );
1174 }
1175 break;
1176 case 0xB:
1177 { /* BF disp */
1178 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1179 snprintf( buf, len, "BF $%xh", disp+pc+4 );
1180 }
1181 break;
1182 case 0xD:
1183 { /* BT/S disp */
1184 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1185 snprintf( buf, len, "BT/S $%xh", disp+pc+4 );
1186 }
1187 break;
1188 case 0xF:
1189 { /* BF/S disp */
1190 int32_t disp = SIGNEXT8(ir&0xFF)<<1;
1191 snprintf( buf, len, "BF/S $%xh", disp+pc+4 );
1192 }
1193 break;
1194 default:
1195 UNDEF();
1196 break;
1197 }
1198 break;
1199 case 0x9:
1200 { /* MOV.W @(disp, PC), Rn */
1201 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;
1202 snprintf( buf, len, "MOV.W @($%xh), R%d ; <- #%08x", disp + pc + 4, Rn, sh4_read_word(disp+pc+4) );
1203 }
1204 break;
1205 case 0xA:
1206 { /* BRA disp */
1207 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1208 snprintf( buf, len, "BRA $%xh", disp+pc+4 );
1209 }
1210 break;
1211 case 0xB:
1212 { /* BSR disp */
1213 int32_t disp = SIGNEXT12(ir&0xFFF)<<1;
1214 snprintf( buf, len, "BSR $%xh", disp+pc+4 );
1215 }
1216 break;
1217 case 0xC:
1218 switch( (ir&0xF00) >> 8 ) {
1219 case 0x0:
1220 { /* MOV.B R0, @(disp, GBR) */
1221 uint32_t disp = (ir&0xFF);
1222 snprintf( buf, len, "MOV.B R0, @(%d, GBR)", disp );
1223 }
1224 break;
1225 case 0x1:
1226 { /* MOV.W R0, @(disp, GBR) */
1227 uint32_t disp = (ir&0xFF)<<1;
1228 snprintf( buf, len, "MOV.W R0, @(%d, GBR)", disp);
1229 }
1230 break;
1231 case 0x2:
1232 { /* MOV.L R0, @(disp, GBR) */
1233 uint32_t disp = (ir&0xFF)<<2;
1234 snprintf( buf, len, "MOV.L R0, @(%d, GBR)", disp );
1235 }
1236 break;
1237 case 0x3:
1238 { /* TRAPA #imm */
1239 uint32_t imm = (ir&0xFF);
1240 snprintf( buf, len, "TRAPA #%d", imm );
1241 }
1242 break;
1243 case 0x4:
1244 { /* MOV.B @(disp, GBR), R0 */
1245 uint32_t disp = (ir&0xFF);
1246 snprintf( buf, len, "MOV.B @(%d, GBR), R0", disp );
1247 }
1248 break;
1249 case 0x5:
1250 { /* MOV.W @(disp, GBR), R0 */
1251 uint32_t disp = (ir&0xFF)<<1;
1252 snprintf( buf, len, "MOV.W @(%d, GBR), R0", disp );
1253 }
1254 break;
1255 case 0x6:
1256 { /* MOV.L @(disp, GBR), R0 */
1257 uint32_t disp = (ir&0xFF)<<2;
1258 snprintf( buf, len, "MOV.L @(%d, GBR), R0",disp );
1259 }
1260 break;
1261 case 0x7:
1262 { /* MOVA @(disp, PC), R0 */
1263 uint32_t disp = (ir&0xFF)<<2;
1264 snprintf( buf, len, "MOVA @($%xh), R0", disp + (pc&0xFFFFFFFC) + 4 );
1265 }
1266 break;
1267 case 0x8:
1268 { /* TST #imm, R0 */
1269 uint32_t imm = (ir&0xFF);
1270 snprintf( buf, len, "TST #%d, R0", imm );
1271 }
1272 break;
1273 case 0x9:
1274 { /* AND #imm, R0 */
1275 uint32_t imm = (ir&0xFF);
1276 snprintf( buf, len, "ADD #%d, R0", imm );
1277 }
1278 break;
1279 case 0xA:
1280 { /* XOR #imm, R0 */
1281 uint32_t imm = (ir&0xFF);
1282 snprintf( buf, len, "XOR #%d, R0", imm );
1283 }
1284 break;
1285 case 0xB:
1286 { /* OR #imm, R0 */
1287 uint32_t imm = (ir&0xFF);
1288 snprintf( buf, len, "OR #%d, R0", imm );
1289 }
1290 break;
1291 case 0xC:
1292 { /* TST.B #imm, @(R0, GBR) */
1293 uint32_t imm = (ir&0xFF);
1294 snprintf( buf, len, "TST.B #%d, @(R0, GBR)", imm );
1295 }
1296 break;
1297 case 0xD:
1298 { /* AND.B #imm, @(R0, GBR) */
1299 uint32_t imm = (ir&0xFF);
1300 snprintf( buf, len, "AND.B #%d, @(R0, GBR)", imm );
1301 }
1302 break;
1303 case 0xE:
1304 { /* XOR.B #imm, @(R0, GBR) */
1305 uint32_t imm = (ir&0xFF);
1306 snprintf( buf, len, "XOR.B #%d, @(R0, GBR)", imm );
1307 }
1308 break;
1309 case 0xF:
1310 { /* OR.B #imm, @(R0, GBR) */
1311 uint32_t imm = (ir&0xFF);
1312 snprintf( buf, len, "OR.B #%d, @(R0, GBR)", imm );
1313 }
1314 break;
1315 }
1316 break;
1317 case 0xD:
1318 { /* MOV.L @(disp, PC), Rn */
1319 uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;
1320 snprintf( buf, len, "MOV.L @($%xh), R%d ; <- #%08x", disp + (pc & 0xFFFFFFFC) + 4, Rn, sh4_read_long(disp+(pc&0xFFFFFFFC)+4) );
1321 }
1322 break;
1323 case 0xE:
1324 { /* MOV #imm, Rn */
1325 uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);
1326 snprintf( buf, len, "MOV #%d, R%d", imm, Rn );
1327 }
1328 break;
1329 case 0xF:
1330 switch( ir&0xF ) {
1331 case 0x0:
1332 { /* FADD FRm, FRn */
1333 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1334 snprintf( buf, len, "FADD FR%d, FR%d", FRm, FRn );
1335 }
1336 break;
1337 case 0x1:
1338 { /* FSUB FRm, FRn */
1339 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1340 snprintf( buf, len, "FSUB FRm, FR%d", FRm, FRn );
1341 }
1342 break;
1343 case 0x2:
1344 { /* FMUL FRm, FRn */
1345 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1346 snprintf( buf, len, "FMUL FRm, FR%d", FRm, FRn );
1347 }
1348 break;
1349 case 0x3:
1350 { /* FDIV FRm, FRn */
1351 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1352 snprintf( buf, len, "FDIV FR%d, FR%d", FRm, FRn );
1353 }
1354 break;
1355 case 0x4:
1356 { /* FCMP/EQ FRm, FRn */
1357 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1358 snprintf( buf, len, "FCMP/EQ FR%d, FR%d", FRm, FRn );
1359 }
1360 break;
1361 case 0x5:
1362 { /* FCMP/GT FRm, FRn */
1363 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1364 snprintf( buf, len, "FCMP/QT FR%d, FR%d", FRm, FRn );
1365 }
1366 break;
1367 case 0x6:
1368 { /* FMOV @(R0, Rm), FRn */
1369 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1370 snprintf( buf, len, "FMOV @(R0, R%d), FR%d", Rm, FRn );
1371 }
1372 break;
1373 case 0x7:
1374 { /* FMOV FRm, @(R0, Rn) */
1375 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1376 snprintf( buf, len, "FMOV FR%d, @(R0, R%d)", FRm, Rn );
1377 }
1378 break;
1379 case 0x8:
1380 { /* FMOV @Rm, FRn */
1381 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1382 snprintf( buf, len, "FMOV @R%d, FR%d", Rm, FRn );
1383 }
1384 break;
1385 case 0x9:
1386 { /* FMOV @Rm+, FRn */
1387 uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);
1388 snprintf( buf, len, "FMOV @R%d+, FR%d", Rm, FRn );
1389 }
1390 break;
1391 case 0xA:
1392 { /* FMOV FRm, @Rn */
1393 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1394 snprintf( buf, len, "FMOV FR%d, @R%d", FRm, Rn );
1395 }
1396 break;
1397 case 0xB:
1398 { /* FMOV FRm, @-Rn */
1399 uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1400 snprintf( buf, len, "FMOV FR%d, @-R%d", FRm, Rn );
1401 }
1402 break;
1403 case 0xC:
1404 { /* FMOV FRm, FRn */
1405 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1406 snprintf( buf, len, "FMOV FR%d, FR%d", FRm, FRn );
1407 }
1408 break;
1409 case 0xD:
1410 switch( (ir&0xF0) >> 4 ) {
1411 case 0x0:
1412 { /* FSTS FPUL, FRn */
1413 uint32_t FRn = ((ir>>8)&0xF);
1414 snprintf( buf, len, "FSTS FPUL, FR%d", FRn );
1415 }
1416 break;
1417 case 0x1:
1418 { /* FLDS FRm, FPUL */
1419 uint32_t FRm = ((ir>>8)&0xF);
1420 snprintf( buf, len, "FLDS FR%d, FPUL", FRm );
1421 }
1422 break;
1423 case 0x2:
1424 { /* FLOAT FPUL, FRn */
1425 uint32_t FRn = ((ir>>8)&0xF);
1426 snprintf( buf, len, "FLOAT FPUL, FR%d", FRn );
1427 }
1428 break;
1429 case 0x3:
1430 { /* FTRC FRm, FPUL */
1431 uint32_t FRm = ((ir>>8)&0xF);
1432 snprintf( buf, len, "FTRC FR%d, FPUL", FRm );
1433 }
1434 break;
1435 case 0x4:
1436 { /* FNEG FRn */
1437 uint32_t FRn = ((ir>>8)&0xF);
1438 snprintf( buf, len, "FNEG FR%d", FRn );
1439 }
1440 break;
1441 case 0x5:
1442 { /* FABS FRn */
1443 uint32_t FRn = ((ir>>8)&0xF);
1444 snprintf( buf, len, "FABS FR%d", FRn );
1445 }
1446 break;
1447 case 0x6:
1448 { /* FSQRT FRn */
1449 uint32_t FRn = ((ir>>8)&0xF);
1450 snprintf( buf, len, "FSQRT FR%d", FRn );
1451 }
1452 break;
1453 case 0x7:
1454 { /* FSRRA FRn */
1455 uint32_t FRn = ((ir>>8)&0xF);
1456 snprintf( buf, len, "FSRRA FR%d", FRn );
1457 }
1458 break;
1459 case 0x8:
1460 { /* FLDI0 FRn */
1461 uint32_t FRn = ((ir>>8)&0xF);
1462 snprintf( buf, len, "FLDI0 FR%d", FRn );
1463 }
1464 break;
1465 case 0x9:
1466 { /* FLDI1 FRn */
1467 uint32_t FRn = ((ir>>8)&0xF);
1468 snprintf( buf, len, "FLDI1 FR%d", FRn );
1469 }
1470 break;
1471 case 0xA:
1472 { /* FCNVSD FPUL, FRn */
1473 uint32_t FRn = ((ir>>8)&0xF);
1474 snprintf( buf, len, "FCNVSD FPUL, FR%d", FRn );
1475 }
1476 break;
1477 case 0xB:
1478 { /* FCNVDS FRm, FPUL */
1479 uint32_t FRm = ((ir>>8)&0xF);
1480 snprintf( buf, len, "FCNVDS FR%d, FPUL", FRm );
1481 }
1482 break;
1483 case 0xE:
1484 { /* FIPR FVm, FVn */
1485 uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);
1486 snprintf( buf, len, "FIPR FV%d, FV%d", FVm, FVn );
1487 }
1488 break;
1489 case 0xF:
1490 switch( (ir&0x100) >> 8 ) {
1491 case 0x0:
1492 { /* FSCA FPUL, FRn */
1493 uint32_t FRn = ((ir>>9)&0x7)<<1;
1494 snprintf( buf, len, "FSCA FPUL, FR%d", FRn );
1495 }
1496 break;
1497 case 0x1:
1498 switch( (ir&0x200) >> 9 ) {
1499 case 0x0:
1500 { /* FTRV XMTRX, FVn */
1501 uint32_t FVn = ((ir>>10)&0x3);
1502 snprintf( buf, len, "FTRV XMTRX, FV%d", FVn );
1503 }
1504 break;
1505 case 0x1:
1506 switch( (ir&0xC00) >> 10 ) {
1507 case 0x0:
1508 { /* FSCHG */
1509 snprintf( buf, len, "FSCHG " );
1510 }
1511 break;
1512 case 0x2:
1513 { /* FRCHG */
1514 snprintf( buf, len, "FRCHG " );
1515 }
1516 break;
1517 case 0x3:
1518 { /* UNDEF */
1519 snprintf( buf, len, "UNDEF " );
1520 }
1521 break;
1522 default:
1523 UNDEF();
1524 break;
1525 }
1526 break;
1527 }
1528 break;
1529 }
1530 break;
1531 default:
1532 UNDEF();
1533 break;
1534 }
1535 break;
1536 case 0xE:
1537 { /* FMAC FR0, FRm, FRn */
1538 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);
1539 snprintf( buf, len, "FMAC FR0, FR%d, FR%d", FRm, FRn );
1540 }
1541 break;
1542 default:
1543 UNDEF();
1544 break;
1545 }
1546 break;
1547 }
1549 return pc+2;
1550 }
1553 void sh4_disasm_region( const gchar *filename, int from, int to )
1554 {
1555 int pc;
1556 char buf[80];
1557 char opcode[16];
1558 FILE *f;
1560 f = fopen( filename, "w" );
1561 for( pc = from; pc < to; pc+=2 ) {
1562 buf[0] = '\0';
1563 sh4_disasm_instruction( pc,
1564 buf, sizeof(buf), opcode );
1565 fprintf( f, " %08x: %s %s\n", pc, opcode, buf );
1566 }
1567 fclose(f);
1568 }
.