filename | src/sh4/x86op.h |
changeset | 377:fa18743f6905 |
prev | 375:4627600f7f8e |
next | 380:2e8166bf6832 |
author | nkeynes |
date | Wed Sep 12 09:20:38 2007 +0000 (16 years ago) |
permissions | -rw-r--r-- |
last change | Start splitting the common SH4 parts into sh4.c, with sh4core.c to become just the emulation core. |
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1 /**
2 * $Id: x86op.h,v 1.6 2007-09-12 09:17:24 nkeynes Exp $
3 *
4 * Definitions of x86 opcodes for use by the translator.
5 *
6 * Copyright (c) 2007 Nathan Keynes.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
19 #ifndef __lxdream_x86op_H
20 #define __lxdream_x86op_H
22 #define R_NONE -1
23 #define R_EAX 0
24 #define R_ECX 1
25 #define R_EDX 2
26 #define R_EBX 3
27 #define R_ESP 4
28 #define R_EBP 5
29 #define R_ESI 6
30 #define R_EDI 7
32 #define R_AL 0
33 #define R_CL 1
34 #define R_DL 2
35 #define R_BL 3
36 #define R_AH 4
37 #define R_CH 5
38 #define R_DH 6
39 #define R_BH 7
42 #define OP(x) *xlat_output++ = (x)
43 #define OP32(x) *((uint32_t *)xlat_output) = (x); xlat_output+=4
45 /* Offset of a reg relative to the sh4r structure */
46 #define REG_OFFSET(reg) (((char *)&sh4r.reg) - ((char *)&sh4r))
48 #define R_T REG_OFFSET(t)
49 #define R_Q REG_OFFSET(q)
50 #define R_S REG_OFFSET(s)
51 #define R_M REG_OFFSET(m)
52 #define R_SR REG_OFFSET(sr)
53 #define R_GBR REG_OFFSET(gbr)
54 #define R_SSR REG_OFFSET(ssr)
55 #define R_SPC REG_OFFSET(spc)
56 #define R_VBR REG_OFFSET(vbr)
57 #define R_MACH REG_OFFSET(mac)+4
58 #define R_MACL REG_OFFSET(mac)
59 #define R_PR REG_OFFSET(pr)
60 #define R_SGR REG_OFFSET(sgr)
61 #define R_FPUL REG_OFFSET(fpul)
62 #define R_FPSCR REG_OFFSET(fpscr)
63 #define R_DBR REG_OFFSET(dbr)
65 /**************** Basic X86 operations *********************/
66 /* Note: operands follow SH4 convention (source, dest) rather than x86
67 * conventions (dest, source)
68 */
70 /* Two-reg modrm form - first arg is the r32 reg, second arg is the r/m32 reg */
71 #define MODRM_r32_rm32(r1,r2) OP(0xC0 | (r1<<3) | r2)
72 #define MODRM_rm32_r32(r1,r2) OP(0xC0 | (r2<<3) | r1)
74 /* ebp+disp8 modrm form */
75 #define MODRM_r32_ebp8(r1,disp) OP(0x45 | (r1<<3)); OP(disp)
77 /* ebp+disp32 modrm form */
78 #define MODRM_r32_ebp32(r1,disp) OP(0x85 | (r1<<3)); OP32(disp)
80 #define MODRM_r32_sh4r(r1,disp) if(disp>127){ MODRM_r32_ebp32(r1,disp);}else{ MODRM_r32_ebp8(r1,(unsigned char)disp); }
82 /* Major opcodes */
83 #define ADD_sh4r_r32(disp,r1) OP(0x03); MODRM_r32_sh4r(r1,disp)
84 #define ADD_r32_r32(r1,r2) OP(0x03); MODRM_rm32_r32(r1,r2)
85 #define ADD_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1, 0); OP(imm)
86 #define ADD_imm32_r32(imm32,r1) OP(0x81); MODRM_rm32_r32(r1,0); OP32(imm32)
87 #define ADC_r32_r32(r1,r2) OP(0x13); MODRM_rm32_r32(r1,r2)
88 #define AND_r32_r32(r1,r2) OP(0x23); MODRM_rm32_r32(r1,r2)
89 #define AND_imm8_r8(imm8, r1) OP(0x80); MODRM_rm32_r32(r1,4); OP(imm8)
90 #define AND_imm8s_r32(imm8,r1) OP(0x83); MODRM_rm32_r32(r1,4); OP(imm8)
91 #define AND_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,4); OP32(imm)
92 #define CALL_r32(r1) OP(0xFF); MODRM_rm32_r32(r1,2)
93 #define CLC() OP(0xF8)
94 #define CMC() OP(0xF5)
95 #define CMP_sh4r_r32(disp,r1) OP(0x3B); MODRM_r32_sh4r(r1,disp)
96 #define CMP_r32_r32(r1,r2) OP(0x3B); MODRM_rm32_r32(r1,r2)
97 #define CMP_imm32_r32(imm32, r1) OP(0x81); MODRM_rm32_r32(r1,7); OP32(imm32)
98 #define CMP_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1,7); OP(imm)
99 #define CMP_imm8s_sh4r(imm,disp) OP(0x83); MODRM_r32_sh4r(7,disp) OP(imm)
100 #define DEC_r32(r1) OP(0x48+r1)
101 #define IMUL_r32(r1) OP(0xF7); MODRM_rm32_r32(r1,5)
102 #define INC_r32(r1) OP(0x40+r1)
103 #define JMP_rel8(rel) OP(0xEB); OP(rel)
104 #define MOV_r32_r32(r1,r2) OP(0x89); MODRM_r32_rm32(r1,r2)
105 #define MOV_r32_sh4r(r1,disp) OP(0x89); MODRM_r32_sh4r(r1,disp)
106 #define MOV_moff32_EAX(off) OP(0xA1); OP32(off)
107 #define MOV_sh4r_r32(disp, r1) OP(0x8B); MODRM_r32_sh4r(r1,disp)
108 #define MOVSX_r8_r32(r1,r2) OP(0x0F); OP(0xBE); MODRM_rm32_r32(r1,r2)
109 #define MOVSX_r16_r32(r1,r2) OP(0x0F); OP(0xBF); MODRM_rm32_r32(r1,r2)
110 #define MOVZX_r8_r32(r1,r2) OP(0x0F); OP(0xB6); MODRM_rm32_r32(r1,r2)
111 #define MOVZX_r16_r32(r1,r2) OP(0x0F); OP(0xB7); MODRM_rm32_r32(r1,r2)
112 #define MUL_r32(r1) OP(0xF7); MODRM_rm32_r32(r1,4)
113 #define NEG_r32(r1) OP(0xF7); MODRM_rm32_r32(r1,3)
114 #define NOT_r32(r1) OP(0xF7); MODRM_rm32_r32(r1,2)
115 #define OR_r32_r32(r1,r2) OP(0x0B); MODRM_rm32_r32(r1,r2)
116 #define OR_imm8_r8(imm,r1) OP(0x80); MODRM_rm32_r32(r1,1)
117 #define OR_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,1); OP32(imm)
118 #define OR_sh4r_r32(disp,r1) OP(0x0B); MODRM_r32_sh4r(r1,disp)
119 #define POP_r32(r1) OP(0x58 + r1)
120 #define PUSH_r32(r1) OP(0x50 + r1)
121 #define PUSH_imm32(imm) OP(0x68); OP32(imm)
122 #define RCL1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,2)
123 #define RCR1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,3)
124 #define RET() OP(0xC3)
125 #define ROL1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,0)
126 #define ROR1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,1)
127 #define SAR1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,7)
128 #define SAR_imm8_r32(imm,r1) OP(0xC1); MODRM_rm32_r32(r1,7); OP(imm)
129 #define SAR_r32_CL(r1) OP(0xD3); MODRM_rm32_r32(r1,7)
130 #define SBB_r32_r32(r1,r2) OP(0x1B); MODRM_rm32_r32(r1,r2)
131 #define SHL1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,4)
132 #define SHL_r32_CL(r1) OP(0xD3); MODRM_rm32_r32(r1,4)
133 #define SHL_imm8_r32(imm,r1) OP(0xC1); MODRM_rm32_r32(r1,4); OP(imm)
134 #define SHR1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,5)
135 #define SHR_r32_CL(r1) OP(0xD3); MODRM_rm32_r32(r1,5)
136 #define SHR_imm8_r32(imm,r1) OP(0xC1); MODRM_rm32_r32(r1,5); OP(imm)
137 #define STC() OP(0xF9)
138 #define SUB_r32_r32(r1,r2) OP(0x2B); MODRM_rm32_r32(r1,r2)
139 #define SUB_sh4r_r32(disp,r1) OP(0x2B); MODRM_r32_sh4r(r1, disp)
140 #define TEST_r8_r8(r1,r2) OP(0x84); MODRM_r32_rm32(r1,r2)
141 #define TEST_r32_r32(r1,r2) OP(0x85); MODRM_rm32_r32(r1,r2)
142 #define TEST_imm8_r8(imm8,r1) OP(0xF6); MODRM_rm32_r32(r1,0); OP(imm8)
143 #define TEST_imm32_r32(imm,r1) OP(0xF7); MODRM_rm32_r32(r1,0); OP32(imm)
144 #define XCHG_r8_r8(r1,r2) OP(0x86); MODRM_rm32_r32(r1,r2)
145 #define XOR_r32_r32(r1,r2) OP(0x33); MODRM_rm32_r32(r1,r2)
146 #define XOR_sh4r_r32(disp,r1) OP(0x33); MODRM_r32_sh4r(r1,disp)
147 #define XOR_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,6); OP32(imm)
150 /* Floating point ops */
151 #define FABS_st0() OP(0xD9); OP(0xE1)
152 #define FADDP_st(st) OP(0xDE); OP(0xC0+st)
153 #define FCHS_st0() OP(0xD9); OP(0xE0)
154 #define FCOMIP_st(st) OP(0xDF); OP(0xF0+st)
155 #define FDIVP_st(st) OP(0xDE); OP(0xF8+st)
156 #define FILD_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(0, disp)
157 #define FISTTP_shr4(disp) OP(0xDB); MODRM_r32_sh4r(1, disp)
158 #define FLD0_st0() OP(0xD9); OP(0xEE);
159 #define FLD1_st0() OP(0xD9); OP(0xE8);
160 #define FMULP_st(st) OP(0xDE); OP(0xC8+st)
161 #define FPOP_st() OP(0xDD); OP(0xC0); OP(0xD9); OP(0xF7)
162 #define FSUB_st(st) OP(0xDE); OP(0xE8+st)
163 #define FSQRT_st0() OP(0xD9); OP(0xFA)
165 /* Conditional branches */
166 #define JE_rel8(rel) OP(0x74); OP(rel)
167 #define JA_rel8(rel) OP(0x77); OP(rel)
168 #define JAE_rel8(rel) OP(0x73); OP(rel)
169 #define JG_rel8(rel) OP(0x7F); OP(rel)
170 #define JGE_rel8(rel) OP(0x7D); OP(rel)
171 #define JC_rel8(rel) OP(0x72); OP(rel)
172 #define JO_rel8(rel) OP(0x70); OP(rel)
173 #define JNE_rel8(rel) OP(0x75); OP(rel)
174 #define JNA_rel8(rel) OP(0x76); OP(rel)
175 #define JNAE_rel8(rel) OP(0x72); OP(rel)
176 #define JNG_rel8(rel) OP(0x7E); OP(rel)
177 #define JNGE_rel8(rel) OP(0x7C); OP(rel)
178 #define JNC_rel8(rel) OP(0x73); OP(rel)
179 #define JNO_rel8(rel) OP(0x71); OP(rel)
181 /* 32-bit long forms w/ backpatching to an exit routine */
182 #define JE_exit(rel) OP(0x0F); OP(0x84); sh4_x86_add_backpatch(xlat_output); OP32(rel)
183 #define JA_exit(rel) OP(0x0F); OP(0x87); sh4_x86_add_backpatch(xlat_output); OP32(rel)
184 #define JAE_exit(rel) OP(0x0F); OP(0x83); sh4_x86_add_backpatch(xlat_output); OP32(rel)
185 #define JG_exit(rel) OP(0x0F); OP(0x8F); sh4_x86_add_backpatch(xlat_output); OP32(rel)
186 #define JGE_exit(rel) OP(0x0F); OP(0x8D); sh4_x86_add_backpatch(xlat_output); OP32(rel)
187 #define JC_exit(rel) OP(0x0F); OP(0x82); sh4_x86_add_backpatch(xlat_output); OP32(rel)
188 #define JO_exit(rel) OP(0x0F); OP(0x80); sh4_x86_add_backpatch(xlat_output); OP32(rel)
189 #define JNE_exit(rel) OP(0x0F); OP(0x85); sh4_x86_add_backpatch(xlat_output); OP32(rel)
190 #define JNA_exit(rel) OP(0x0F); OP(0x86); sh4_x86_add_backpatch(xlat_output); OP32(rel)
191 #define JNAE_exit(rel) OP(0x0F);OP(0x82); sh4_x86_add_backpatch(xlat_output); OP32(rel)
192 #define JNG_exit(rel) OP(0x0F); OP(0x8E); sh4_x86_add_backpatch(xlat_output); OP32(rel)
193 #define JNGE_exit(rel) OP(0x0F);OP(0x8C); sh4_x86_add_backpatch(xlat_output); OP32(rel)
194 #define JNC_exit(rel) OP(0x0F); OP(0x83); sh4_x86_add_backpatch(xlat_output); OP32(rel)
195 #define JNO_exit(rel) OP(0x0F); OP(0x81); sh4_x86_add_backpatch(xlat_output); OP32(rel)
198 /* Conditional moves ebp-rel */
199 #define CMOVE_r32_r32(r1,r2) OP(0x0F); OP(0x44); MODRM_rm32_r32(r1,r2)
200 #define CMOVA_r32_r32(r1,r2) OP(0x0F); OP(0x47); MODRM_rm32_r32(r1,r2)
201 #define CMOVAE_r32_r32(r1,r2) OP(0x0F); OP(0x43); MODRM_rm32_r32(r1,r2)
202 #define CMOVG_r32_r32(r1,r2) OP(0x0F); OP(0x4F); MODRM_rm32_r32(r1,r2)
203 #define CMOVGE_r32_r32(r1,r2) OP(0x0F); OP(0x4D); MODRM_rm32_r32(r1,r2)
204 #define CMOVC_r32_r32(r1,r2) OP(0x0F); OP(0x42); MODRM_rm32_r32(r1,r2)
205 #define CMOVO_r32_r32(r1,r2) OP(0x0F); OP(0x40); MODRM_rm32_r32(r1,r2)
208 /* Conditional setcc - writeback to sh4r.t */
209 #define SETE_sh4r(disp) OP(0x0F); OP(0x94); MODRM_r32_sh4r(0, disp);
210 #define SETA_sh4r(disp) OP(0x0F); OP(0x97); MODRM_r32_sh4r(0, disp);
211 #define SETAE_sh4r(disp) OP(0x0F); OP(0x93); MODRM_r32_sh4r(0, disp);
212 #define SETG_sh4r(disp) OP(0x0F); OP(0x9F); MODRM_r32_sh4r(0, disp);
213 #define SETGE_sh4r(disp) OP(0x0F); OP(0x9D); MODRM_r32_sh4r(0, disp);
214 #define SETC_sh4r(disp) OP(0x0F); OP(0x92); MODRM_r32_sh4r(0, disp);
215 #define SETO_sh4r(disp) OP(0x0F); OP(0x90); MODRM_r32_sh4r(0, disp);
217 #define SETNE_sh4r(disp) OP(0x0F); OP(0x95); MODRM_r32_sh4r(0, disp);
218 #define SETNA_sh4r(disp) OP(0x0F); OP(0x96); MODRM_r32_sh4r(0, disp);
219 #define SETNAE_sh4r(disp) OP(0x0F); OP(0x92); MODRM_r32_sh4r(0, disp);
220 #define SETNG_sh4r(disp) OP(0x0F); OP(0x9E); MODRM_r32_sh4r(0, disp);
221 #define SETNGE_sh4r(disp) OP(0x0F); OP(0x9C); MODRM_r32_sh4r(0, disp);
222 #define SETNC_sh4r(disp) OP(0x0F); OP(0x93); MODRM_r32_sh4r(0, disp);
223 #define SETNO_sh4r(disp) OP(0x0F); OP(0x91); MODRM_r32_sh4r(0, disp);
225 #define SETE_t() SETE_sh4r(R_T)
226 #define SETA_t() SETA_sh4r(R_T)
227 #define SETAE_t() SETAE_sh4r(R_T)
228 #define SETG_t() SETG_sh4r(R_T)
229 #define SETGE_t() SETGE_sh4r(R_T)
230 #define SETC_t() SETC_sh4r(R_T)
231 #define SETO_t() SETO_sh4r(R_T)
233 #define SETC_r32(r1) OP(0x0F); OP(0x92); MODRM_rm32_r32(r1, 0)
235 /* Pseudo-op Load carry from T: CMP [EBP+t], #01 ; CMC */
236 #define LDC_t() OP(0x83); MODRM_r32_sh4r(7,R_T); OP(0x01); CMC()
238 #endif /* !__lxdream_x86op_H */
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