lxdream 0.9.1| filename | src/asic.c |
| changeset | 975:007bf7eb944f |
| prev | 929:fd8cb0c82f5f |
| next | 1065:bc1cc0c54917 |
| author | nkeynes |
| date | Thu Jun 25 01:15:25 2009 +0000 (14 years ago) |
| permissions | -rw-r--r-- |
| last change | Move configuration to .lxdream/lxdreamrc on *nix, Library/Application Support/Lxdream on OS X Create standard directories on first run Add current quick state to config file Refactor quick-state handling into dreamcast.c, and use the save directory |
| view | annotate | diff | log | raw |
1 /**
2 * $Id$
3 *
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
5 * and DMA).
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE asic_module
22 #include <assert.h>
23 #include <stdlib.h>
24 #include "dream.h"
25 #include "mem.h"
26 #include "sh4/intc.h"
27 #include "sh4/dmac.h"
28 #include "sh4/sh4.h"
29 #include "dreamcast.h"
30 #include "maple/maple.h"
31 #include "gdrom/ide.h"
32 #include "pvr2/pvr2.h"
33 #include "asic.h"
34 #define MMIO_IMPL
35 #include "asic.h"
36 /*
37 * Open questions:
38 * 1) Does changing the mask after event occurance result in the
39 * interrupt being delivered immediately?
40 * TODO: Logic diagram of ASIC event/interrupt logic.
41 *
42 * ... don't even get me started on the "EXTDMA" page, about which, apparently,
43 * practically nothing is publicly known...
44 */
46 static void asic_check_cleared_events( void );
47 static void asic_init( void );
48 static void asic_reset( void );
49 static uint32_t asic_run_slice( uint32_t nanosecs );
50 static void asic_save_state( FILE *f );
51 static int asic_load_state( FILE *f );
52 static uint32_t g2_update_fifo_status( uint32_t slice_cycle );
54 struct dreamcast_module asic_module = { "ASIC", asic_init, asic_reset, NULL, asic_run_slice,
55 NULL, asic_save_state, asic_load_state };
57 #define G2_BIT5_TICKS 60
58 #define G2_BIT4_TICKS 160
59 #define G2_BIT0_ON_TICKS 120
60 #define G2_BIT0_OFF_TICKS 420
62 struct asic_g2_state {
63 int bit5_off_timer;
64 int bit4_on_timer;
65 int bit4_off_timer;
66 int bit0_on_timer;
67 int bit0_off_timer;
68 };
70 static struct asic_g2_state g2_state;
72 static uint32_t asic_run_slice( uint32_t nanosecs )
73 {
74 g2_update_fifo_status(nanosecs);
75 if( g2_state.bit5_off_timer <= (int32_t)nanosecs ) {
76 g2_state.bit5_off_timer = -1;
77 } else {
78 g2_state.bit5_off_timer -= nanosecs;
79 }
81 if( g2_state.bit4_off_timer <= (int32_t)nanosecs ) {
82 g2_state.bit4_off_timer = -1;
83 } else {
84 g2_state.bit4_off_timer -= nanosecs;
85 }
86 if( g2_state.bit4_on_timer <= (int32_t)nanosecs ) {
87 g2_state.bit4_on_timer = -1;
88 } else {
89 g2_state.bit4_on_timer -= nanosecs;
90 }
92 if( g2_state.bit0_off_timer <= (int32_t)nanosecs ) {
93 g2_state.bit0_off_timer = -1;
94 } else {
95 g2_state.bit0_off_timer -= nanosecs;
96 }
97 if( g2_state.bit0_on_timer <= (int32_t)nanosecs ) {
98 g2_state.bit0_on_timer = -1;
99 } else {
100 g2_state.bit0_on_timer -= nanosecs;
101 }
103 return nanosecs;
104 }
106 static void asic_init( void )
107 {
108 register_io_region( &mmio_region_ASIC );
109 register_io_region( &mmio_region_EXTDMA );
110 asic_reset();
111 }
113 static void asic_reset( void )
114 {
115 memset( &g2_state, 0xFF, sizeof(g2_state) );
116 }
118 static void asic_save_state( FILE *f )
119 {
120 fwrite( &g2_state, sizeof(g2_state), 1, f );
121 }
123 static int asic_load_state( FILE *f )
124 {
125 if( fread( &g2_state, sizeof(g2_state), 1, f ) != 1 )
126 return 1;
127 else
128 return 0;
129 }
132 /**
133 * Setup the timers for the 3 FIFO status bits following a write through the G2
134 * bus from the SH4 side. The timing is roughly as follows: (times are
135 * approximate based on software readings - I wouldn't take this as gospel but
136 * it seems to be enough to fool most programs).
137 * 0ns: Bit 5 (Input fifo?) goes high immediately on the write
138 * 40ns: Bit 5 goes low and bit 4 goes high
139 * 120ns: Bit 4 goes low, bit 0 goes high
140 * 240ns: Bit 0 goes low.
141 *
142 * Additional writes while the FIFO is in operation extend the time that the
143 * bits remain high as one might expect, without altering the time at which
144 * they initially go high.
145 */
146 void asic_g2_write_word()
147 {
148 if( g2_state.bit5_off_timer < (int32_t)sh4r.slice_cycle ) {
149 g2_state.bit5_off_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
150 } else {
151 g2_state.bit5_off_timer += G2_BIT5_TICKS;
152 }
154 if( g2_state.bit4_on_timer < (int32_t)sh4r.slice_cycle ) {
155 g2_state.bit4_on_timer = sh4r.slice_cycle + G2_BIT5_TICKS;
156 }
158 if( g2_state.bit4_off_timer < (int32_t)sh4r.slice_cycle ) {
159 g2_state.bit4_off_timer = g2_state.bit4_on_timer + G2_BIT4_TICKS;
160 } else {
161 g2_state.bit4_off_timer += G2_BIT4_TICKS;
162 }
164 if( g2_state.bit0_on_timer < (int32_t)sh4r.slice_cycle ) {
165 g2_state.bit0_on_timer = sh4r.slice_cycle + G2_BIT0_ON_TICKS;
166 }
168 if( g2_state.bit0_off_timer < (int32_t)sh4r.slice_cycle ) {
169 g2_state.bit0_off_timer = g2_state.bit0_on_timer + G2_BIT0_OFF_TICKS;
170 } else {
171 g2_state.bit0_off_timer += G2_BIT0_OFF_TICKS;
172 }
174 MMIO_WRITE( ASIC, G2STATUS, MMIO_READ(ASIC, G2STATUS) | 0x20 );
175 }
177 static uint32_t g2_update_fifo_status( uint32_t nanos )
178 {
179 uint32_t val = MMIO_READ( ASIC, G2STATUS );
180 if( ((uint32_t)g2_state.bit5_off_timer) <= nanos ) {
181 val = val & (~0x20);
182 g2_state.bit5_off_timer = -1;
183 }
184 if( ((uint32_t)g2_state.bit4_on_timer) <= nanos ) {
185 val = val | 0x10;
186 g2_state.bit4_on_timer = -1;
187 }
188 if( ((uint32_t)g2_state.bit4_off_timer) <= nanos ) {
189 val = val & (~0x10);
190 g2_state.bit4_off_timer = -1;
191 }
193 if( ((uint32_t)g2_state.bit0_on_timer) <= nanos ) {
194 val = val | 0x01;
195 g2_state.bit0_on_timer = -1;
196 }
197 if( ((uint32_t)g2_state.bit0_off_timer) <= nanos ) {
198 val = val & (~0x01);
199 g2_state.bit0_off_timer = -1;
200 }
202 MMIO_WRITE( ASIC, G2STATUS, val );
203 return val;
204 }
206 static int g2_read_status() {
207 return g2_update_fifo_status( sh4r.slice_cycle );
208 }
211 void asic_event( int event )
212 {
213 int offset = ((event&0x60)>>3);
214 int result = (MMIO_READ(ASIC, PIRQ0 + offset)) |= (1<<(event&0x1F));
216 if( result & MMIO_READ(ASIC, IRQA0 + offset) )
217 intc_raise_interrupt( INT_IRQ13 );
218 if( result & MMIO_READ(ASIC, IRQB0 + offset) )
219 intc_raise_interrupt( INT_IRQ11 );
220 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
221 intc_raise_interrupt( INT_IRQ9 );
223 if( event >= 64 ) { /* Third word */
224 asic_event( EVENT_CASCADE2 );
225 } else if( event >= 32 ) { /* Second word */
226 asic_event( EVENT_CASCADE1 );
227 }
228 }
230 void asic_clear_event( int event ) {
231 int offset = ((event&0x60)>>3);
232 uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
233 MMIO_WRITE( ASIC, PIRQ0 + offset, result );
234 if( result == 0 ) {
235 /* clear cascades if necessary */
236 if( event >= 64 ) {
237 MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
238 } else if( event >= 32 ) {
239 MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
240 }
241 }
243 asic_check_cleared_events();
244 }
246 void asic_check_cleared_events( )
247 {
248 int i, setA = 0, setB = 0, setC = 0;
249 uint32_t bits;
250 for( i=0; i<12; i+=4 ) {
251 bits = MMIO_READ( ASIC, PIRQ0 + i );
252 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
253 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
254 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
255 }
256 if( setA == 0 )
257 intc_clear_interrupt( INT_IRQ13 );
258 if( setB == 0 )
259 intc_clear_interrupt( INT_IRQ11 );
260 if( setC == 0 )
261 intc_clear_interrupt( INT_IRQ9 );
262 }
264 void asic_event_mask_changed( )
265 {
266 int i, setA = 0, setB = 0, setC = 0;
267 uint32_t bits;
268 for( i=0; i<12; i+=4 ) {
269 bits = MMIO_READ( ASIC, PIRQ0 + i );
270 setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
271 setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
272 setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
273 }
274 if( setA == 0 )
275 intc_clear_interrupt( INT_IRQ13 );
276 else
277 intc_raise_interrupt( INT_IRQ13 );
278 if( setB == 0 )
279 intc_clear_interrupt( INT_IRQ11 );
280 else
281 intc_raise_interrupt( INT_IRQ11 );
282 if( setC == 0 )
283 intc_clear_interrupt( INT_IRQ9 );
284 else
285 intc_raise_interrupt( INT_IRQ9 );
286 }
288 void g2_dma_transfer( int channel )
289 {
290 uint32_t offset = channel << 5;
292 if( MMIO_READ( EXTDMA, G2DMA0CTL1 + offset ) == 1 ) {
293 if( MMIO_READ( EXTDMA, G2DMA0CTL2 + offset ) == 1 ) {
294 uint32_t extaddr = MMIO_READ( EXTDMA, G2DMA0EXT + offset );
295 uint32_t sh4addr = MMIO_READ( EXTDMA, G2DMA0SH4 + offset );
296 uint32_t length = MMIO_READ( EXTDMA, G2DMA0SIZ + offset ) & 0x1FFFFFFF;
297 uint32_t dir = MMIO_READ( EXTDMA, G2DMA0DIR + offset );
298 // uint32_t mode = MMIO_READ( EXTDMA, G2DMA0MOD + offset );
299 unsigned char buf[length];
300 if( dir == 0 ) { /* SH4 to device */
301 mem_copy_from_sh4( buf, sh4addr, length );
302 mem_copy_to_sh4( extaddr, buf, length );
303 } else { /* Device to SH4 */
304 mem_copy_from_sh4( buf, extaddr, length );
305 mem_copy_to_sh4( sh4addr, buf, length );
306 }
307 MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
308 asic_event( EVENT_G2_DMA0 + channel );
309 } else {
310 MMIO_WRITE( EXTDMA, G2DMA0CTL2 + offset, 0 );
311 }
312 }
313 }
315 void asic_ide_dma_transfer( )
316 {
317 if( MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
318 if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 ) {
319 MMIO_WRITE( EXTDMA, IDEDMATXSIZ, 0 );
321 uint32_t addr = MMIO_READ( EXTDMA, IDEDMASH4 );
322 uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
323 // int dir = MMIO_READ( EXTDMA, IDEDMADIR );
325 uint32_t xfer = ide_read_data_dma( addr, length );
326 MMIO_WRITE( EXTDMA, IDEDMATXSIZ, xfer );
327 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
328 asic_event( EVENT_IDE_DMA );
329 } else { /* 0 */
330 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );
331 }
332 }
333 }
335 void pvr_dma_transfer( )
336 {
337 sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
338 uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
339 unsigned char *data = alloca( count );
340 uint32_t rcount = DMAC_get_buffer( 2, data, count );
341 if( rcount != count )
342 WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
344 pvr2_dma_write( destaddr, data, rcount );
346 MMIO_WRITE( ASIC, PVRDMACTL, 0 );
347 MMIO_WRITE( ASIC, PVRDMACNT, 0 );
348 if( destaddr & 0x01000000 ) { /* Write to texture RAM */
349 MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );
350 }
351 asic_event( EVENT_PVR_DMA );
352 }
354 void pvr_dma2_transfer()
355 {
356 if( MMIO_READ( EXTDMA, PVRDMA2CTL2 ) == 1 ) {
357 if( MMIO_READ( EXTDMA, PVRDMA2CTL1 ) == 1 ) {
358 sh4addr_t extaddr = MMIO_READ( EXTDMA, PVRDMA2EXT );
359 sh4addr_t sh4addr = MMIO_READ( EXTDMA, PVRDMA2SH4 );
360 int dir = MMIO_READ( EXTDMA, PVRDMA2DIR );
361 uint32_t length = MMIO_READ( EXTDMA, PVRDMA2SIZ );
362 unsigned char buf[length];
363 if( dir == 0 ) { /* SH4 to PVR */
364 mem_copy_from_sh4( buf, sh4addr, length );
365 mem_copy_to_sh4( extaddr, buf, length );
366 } else { /* PVR to SH4 */
367 mem_copy_from_sh4( buf, extaddr, length );
368 mem_copy_to_sh4( sh4addr, buf, length );
369 }
370 MMIO_WRITE( EXTDMA, PVRDMA2CTL2, 0 );
371 asic_event( EVENT_PVR_DMA2 );
372 }
373 }
374 }
376 void sort_dma_transfer( )
377 {
378 sh4addr_t table_addr = MMIO_READ( ASIC, SORTDMATBL );
379 sh4addr_t data_addr = MMIO_READ( ASIC, SORTDMADATA );
380 int table_size = MMIO_READ( ASIC, SORTDMATSIZ );
381 int addr_shift = MMIO_READ( ASIC, SORTDMAASIZ ) ? 5 : 0;
382 int count = 1;
384 uint32_t *table32 = (uint32_t *)mem_get_region( table_addr );
385 uint16_t *table16 = (uint16_t *)table32;
386 uint32_t next = table_size ? (*table32++) : (uint32_t)(*table16++);
387 while(1) {
388 next &= 0x07FFFFFF;
389 if( next == 1 ) {
390 next = table_size ? (*table32++) : (uint32_t)(*table16++);
391 count++;
392 continue;
393 } else if( next == 2 ) {
394 asic_event( EVENT_SORT_DMA );
395 break;
396 }
397 uint32_t *data = (uint32_t *)mem_get_region(data_addr + (next<<addr_shift));
398 if( data == NULL ) {
399 break;
400 }
402 uint32_t *poly = pvr2_ta_find_polygon_context(data, 128);
403 if( poly == NULL ) {
404 asic_event( EVENT_SORT_DMA_ERR );
405 break;
406 }
407 uint32_t size = poly[6] & 0xFF;
408 if( size == 0 ) {
409 size = 0x100;
410 }
411 next = poly[7];
412 pvr2_ta_write( (unsigned char *)data, size<<5 );
413 }
415 MMIO_WRITE( ASIC, SORTDMACNT, count );
416 MMIO_WRITE( ASIC, SORTDMACTL, 0 );
417 }
419 MMIO_REGION_READ_FN( ASIC, reg )
420 {
421 int32_t val;
422 reg &= 0xFFF;
423 switch( reg ) {
424 case PIRQ0:
425 case PIRQ1:
426 case PIRQ2:
427 case IRQA0:
428 case IRQA1:
429 case IRQA2:
430 case IRQB0:
431 case IRQB1:
432 case IRQB2:
433 case IRQC0:
434 case IRQC1:
435 case IRQC2:
436 case MAPLE_STATE:
437 val = MMIO_READ(ASIC, reg);
438 return val;
439 case G2STATUS:
440 return g2_read_status();
441 default:
442 val = MMIO_READ(ASIC, reg);
443 return val;
444 }
446 }
448 MMIO_REGION_READ_DEFSUBFNS(ASIC)
450 MMIO_REGION_WRITE_FN( ASIC, reg, val )
451 {
452 reg &= 0xFFF;
453 switch( reg ) {
454 case PIRQ1:
455 break; /* Treat this as read-only for the moment */
456 case PIRQ0:
457 val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
458 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
459 asic_check_cleared_events();
460 break;
461 case PIRQ2:
462 /* Clear any events */
463 val = MMIO_READ(ASIC, reg)&(~val);
464 MMIO_WRITE( ASIC, reg, val );
465 if( val == 0 ) { /* all clear - clear the cascade bit */
466 MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
467 }
468 asic_check_cleared_events();
469 break;
470 case IRQA0:
471 case IRQA1:
472 case IRQA2:
473 case IRQB0:
474 case IRQB1:
475 case IRQB2:
476 case IRQC0:
477 case IRQC1:
478 case IRQC2:
479 MMIO_WRITE( ASIC, reg, val );
480 asic_event_mask_changed();
481 break;
482 case SYSRESET:
483 if( val == 0x7611 ) {
484 dreamcast_reset();
485 } else {
486 WARN( "Unknown value %08X written to SYSRESET port", val );
487 }
488 break;
489 case MAPLE_STATE:
490 MMIO_WRITE( ASIC, reg, val );
491 if( val & 1 ) {
492 uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
493 maple_handle_buffer( maple_addr );
494 MMIO_WRITE( ASIC, reg, 0 );
495 }
496 break;
497 case PVRDMADEST:
498 MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );
499 break;
500 case PVRDMACNT:
501 MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );
502 break;
503 case PVRDMACTL: /* Initiate PVR DMA transfer */
504 val = val & 0x01;
505 MMIO_WRITE( ASIC, reg, val );
506 if( val == 1 ) {
507 pvr_dma_transfer();
508 }
509 break;
510 case SORTDMATBL: case SORTDMADATA:
511 MMIO_WRITE( ASIC, reg, (val & 0x0FFFFFE0) | 0x08000000 );
512 break;
513 case SORTDMATSIZ: case SORTDMAASIZ:
514 MMIO_WRITE( ASIC, reg, (val & 1) );
515 break;
516 case SORTDMACTL:
517 val = val & 1;
518 MMIO_WRITE( ASIC, reg, val );
519 if( val == 1 ) {
520 sort_dma_transfer();
521 }
522 break;
523 case MAPLE_DMA:
524 MMIO_WRITE( ASIC, reg, val );
525 break;
526 default:
527 MMIO_WRITE( ASIC, reg, val );
528 }
529 }
531 MMIO_REGION_READ_FN( EXTDMA, reg )
532 {
533 uint32_t val;
534 reg &= 0xFFF;
535 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
536 return 0xFFFFFFFF; /* disabled */
537 }
539 switch( reg ) {
540 case IDEALTSTATUS:
541 val = idereg.status;
542 return val;
543 case IDEDATA: return ide_read_data_pio( );
544 case IDEFEAT: return idereg.error;
545 case IDECOUNT:return idereg.count;
546 case IDELBA0: return ide_get_drive_status();
547 case IDELBA1: return idereg.lba1;
548 case IDELBA2: return idereg.lba2;
549 case IDEDEV: return idereg.device;
550 case IDECMD:
551 val = ide_read_status();
552 return val;
553 default:
554 val = MMIO_READ( EXTDMA, reg );
555 return val;
556 }
557 }
558 MMIO_REGION_READ_DEFSUBFNS(EXTDMA)
561 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
562 {
563 reg &= 0xFFF;
564 if( !idereg.interface_enabled && IS_IDE_REGISTER(reg) ) {
565 return; /* disabled */
566 }
568 switch( reg ) {
569 case IDEALTSTATUS: /* Device control */
570 ide_write_control( val );
571 break;
572 case IDEDATA:
573 ide_write_data_pio( val );
574 break;
575 case IDEFEAT:
576 if( ide_can_write_regs() )
577 idereg.feature = (uint8_t)val;
578 break;
579 case IDECOUNT:
580 if( ide_can_write_regs() )
581 idereg.count = (uint8_t)val;
582 break;
583 case IDELBA0:
584 if( ide_can_write_regs() )
585 idereg.lba0 = (uint8_t)val;
586 break;
587 case IDELBA1:
588 if( ide_can_write_regs() )
589 idereg.lba1 = (uint8_t)val;
590 break;
591 case IDELBA2:
592 if( ide_can_write_regs() )
593 idereg.lba2 = (uint8_t)val;
594 break;
595 case IDEDEV:
596 if( ide_can_write_regs() )
597 idereg.device = (uint8_t)val;
598 break;
599 case IDECMD:
600 if( ide_can_write_regs() || val == IDE_CMD_NOP ) {
601 ide_write_command( (uint8_t)val );
602 }
603 break;
604 case IDEDMASH4:
605 MMIO_WRITE( EXTDMA, reg, val & 0x1FFFFFE0 );
606 break;
607 case IDEDMASIZ:
608 MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
609 break;
610 case IDEDMADIR:
611 MMIO_WRITE( EXTDMA, reg, val & 1 );
612 break;
613 case IDEDMACTL1:
614 case IDEDMACTL2:
615 MMIO_WRITE( EXTDMA, reg, val & 0x01 );
616 asic_ide_dma_transfer( );
617 break;
618 case IDEACTIVATE:
619 if( val == 0x001FFFFF ) {
620 idereg.interface_enabled = TRUE;
621 /* Conventional wisdom says that this is necessary but not
622 * sufficient to enable the IDE interface.
623 */
624 } else if( val == 0x000042FE ) {
625 idereg.interface_enabled = FALSE;
626 }
627 break;
628 case G2DMA0EXT: case G2DMA0SH4: case G2DMA0SIZ:
629 case G2DMA1EXT: case G2DMA1SH4: case G2DMA1SIZ:
630 case G2DMA2EXT: case G2DMA2SH4: case G2DMA2SIZ:
631 case G2DMA3EXT: case G2DMA3SH4: case G2DMA3SIZ:
632 MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );
633 break;
634 case G2DMA0MOD: case G2DMA1MOD: case G2DMA2MOD: case G2DMA3MOD:
635 MMIO_WRITE( EXTDMA, reg, val & 0x07 );
636 break;
637 case G2DMA0DIR: case G2DMA1DIR: case G2DMA2DIR: case G2DMA3DIR:
638 MMIO_WRITE( EXTDMA, reg, val & 0x01 );
639 break;
640 case G2DMA0CTL1:
641 case G2DMA0CTL2:
642 MMIO_WRITE( EXTDMA, reg, val & 1);
643 g2_dma_transfer( 0 );
644 break;
645 case G2DMA0STOP:
646 MMIO_WRITE( EXTDMA, reg, val & 0x37 );
647 break;
648 case G2DMA1CTL1:
649 case G2DMA1CTL2:
650 MMIO_WRITE( EXTDMA, reg, val & 1);
651 g2_dma_transfer( 1 );
652 break;
654 case G2DMA1STOP:
655 MMIO_WRITE( EXTDMA, reg, val & 0x37 );
656 break;
657 case G2DMA2CTL1:
658 case G2DMA2CTL2:
659 MMIO_WRITE( EXTDMA, reg, val &1 );
660 g2_dma_transfer( 2 );
661 break;
662 case G2DMA2STOP:
663 MMIO_WRITE( EXTDMA, reg, val & 0x37 );
664 break;
665 case G2DMA3CTL1:
666 case G2DMA3CTL2:
667 MMIO_WRITE( EXTDMA, reg, val &1 );
668 g2_dma_transfer( 3 );
669 break;
670 case G2DMA3STOP:
671 MMIO_WRITE( EXTDMA, reg, val & 0x37 );
672 break;
673 case PVRDMA2CTL1:
674 case PVRDMA2CTL2:
675 MMIO_WRITE( EXTDMA, reg, val & 1 );
676 pvr_dma2_transfer();
677 break;
678 default:
679 MMIO_WRITE( EXTDMA, reg, val );
680 }
681 }
.