lxdream 0.9.1| filename | src/sh4/sh4core.c |
| changeset | 229:f27eb26ccdd2 |
| prev | 227:1b98af7fc601 |
| next | 232:9c8ef78376ed |
| author | nkeynes |
| date | Mon Sep 25 11:19:42 2006 +0000 (17 years ago) |
| permissions | -rw-r--r-- |
| last change | Fix SPC assignment for exceptions (the only one it was _correct_ for was TRAPA) |
| view | annotate | diff | log | raw |
1 /**
2 * $Id: sh4core.c,v 1.32 2006-09-25 11:19:42 nkeynes Exp $
3 *
4 * SH4 emulation core, and parent module for all the SH4 peripheral
5 * modules.
6 *
7 * Copyright (c) 2005 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #define MODULE sh4_module
21 #include <math.h>
22 #include "dream.h"
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
25 #include "sh4/intc.h"
26 #include "mem.h"
27 #include "clock.h"
28 #include "syscall.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 /* CPU-generated exception code/vector pairs */
38 #define EXC_POWER_RESET 0x000 /* vector special */
39 #define EXC_MANUAL_RESET 0x020
40 #define EXC_READ_ADDR_ERR 0x0E0
41 #define EXC_WRITE_ADDR_ERR 0x100
42 #define EXC_SLOT_ILLEGAL 0x1A0
43 #define EXC_ILLEGAL 0x180
44 #define EXV_ILLEGAL 0x100
45 #define EXC_TRAP 0x160
46 #define EXV_TRAP 0x100
47 #define EXC_FPDISABLE 0x800
48 #define EXV_FPDISABLE 0x100
50 /********************** SH4 Module Definition ****************************/
52 void sh4_init( void );
53 void sh4_reset( void );
54 uint32_t sh4_run_slice( uint32_t );
55 void sh4_start( void );
56 void sh4_stop( void );
57 void sh4_save_state( FILE *f );
58 int sh4_load_state( FILE *f );
60 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
61 NULL, sh4_run_slice, sh4_stop,
62 sh4_save_state, sh4_load_state };
64 struct sh4_registers sh4r;
66 void sh4_init(void)
67 {
68 register_io_regions( mmio_list_sh4mmio );
69 mmu_init();
70 sh4_reset();
71 }
73 void sh4_reset(void)
74 {
75 /* zero everything out, for the sake of having a consistent state. */
76 memset( &sh4r, 0, sizeof(sh4r) );
78 /* Resume running if we were halted */
79 sh4r.sh4_state = SH4_STATE_RUNNING;
81 sh4r.pc = 0xA0000000;
82 sh4r.new_pc= 0xA0000002;
83 sh4r.vbr = 0x00000000;
84 sh4r.fpscr = 0x00040001;
85 sh4r.sr = 0x700000F0;
87 /* Mem reset will do this, but if we want to reset _just_ the SH4... */
88 MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
90 /* Peripheral modules */
91 INTC_reset();
92 TMU_reset();
93 SCIF_reset();
94 }
96 static struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
97 static int sh4_breakpoint_count = 0;
99 void sh4_set_breakpoint( uint32_t pc, int type )
100 {
101 sh4_breakpoints[sh4_breakpoint_count].address = pc;
102 sh4_breakpoints[sh4_breakpoint_count].type = type;
103 sh4_breakpoint_count++;
104 }
106 gboolean sh4_clear_breakpoint( uint32_t pc, int type )
107 {
108 int i;
110 for( i=0; i<sh4_breakpoint_count; i++ ) {
111 if( sh4_breakpoints[i].address == pc &&
112 sh4_breakpoints[i].type == type ) {
113 while( ++i < sh4_breakpoint_count ) {
114 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
115 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
116 }
117 sh4_breakpoint_count--;
118 return TRUE;
119 }
120 }
121 return FALSE;
122 }
124 int sh4_get_breakpoint( uint32_t pc )
125 {
126 int i;
127 for( i=0; i<sh4_breakpoint_count; i++ ) {
128 if( sh4_breakpoints[i].address == pc )
129 return sh4_breakpoints[i].type;
130 }
131 return 0;
132 }
134 uint32_t sh4_run_slice( uint32_t nanosecs )
135 {
136 int target = sh4r.icount + nanosecs / sh4_cpu_period;
137 int start = sh4r.icount;
138 int i;
140 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
141 if( sh4r.int_pending != 0 )
142 sh4r.sh4_state = SH4_STATE_RUNNING;;
143 }
145 for( sh4r.slice_cycle = 0; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
146 if( !sh4_execute_instruction() )
147 break;
148 #ifdef ENABLE_DEBUG_MODE
149 for( i=0; i<sh4_breakpoint_count; i++ ) {
150 if( sh4_breakpoints[i].address == sh4r.pc ) {
151 break;
152 }
153 }
154 if( i != sh4_breakpoint_count ) {
155 dreamcast_stop();
156 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
157 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
158 break;
159 }
160 #endif
161 }
163 /* If we aborted early, but the cpu is still technically running,
164 * we're doing a hard abort - cut the timeslice back to what we
165 * actually executed
166 */
167 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
168 nanosecs = sh4r.slice_cycle;
169 }
170 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
171 TMU_run_slice( nanosecs );
172 SCIF_run_slice( nanosecs );
173 }
174 sh4r.icount += sh4r.slice_cycle / sh4_cpu_period;
175 return nanosecs;
176 }
178 void sh4_stop(void)
179 {
181 }
183 void sh4_save_state( FILE *f )
184 {
185 fwrite( &sh4r, sizeof(sh4r), 1, f );
186 INTC_save_state( f );
187 TMU_save_state( f );
188 SCIF_save_state( f );
189 }
191 int sh4_load_state( FILE * f )
192 {
193 fread( &sh4r, sizeof(sh4r), 1, f );
194 INTC_load_state( f );
195 TMU_load_state( f );
196 return SCIF_load_state( f );
197 }
199 /********************** SH4 emulation core ****************************/
201 void sh4_set_pc( int pc )
202 {
203 sh4r.pc = pc;
204 sh4r.new_pc = pc+2;
205 }
207 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
208 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
210 #if(SH4_CALLTRACE == 1)
211 #define MAX_CALLSTACK 32
212 static struct call_stack {
213 sh4addr_t call_addr;
214 sh4addr_t target_addr;
215 sh4addr_t stack_pointer;
216 } call_stack[MAX_CALLSTACK];
218 static int call_stack_depth = 0;
219 int sh4_call_trace_on = 0;
221 static inline trace_call( sh4addr_t source, sh4addr_t dest )
222 {
223 if( call_stack_depth < MAX_CALLSTACK ) {
224 call_stack[call_stack_depth].call_addr = source;
225 call_stack[call_stack_depth].target_addr = dest;
226 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
227 }
228 call_stack_depth++;
229 }
231 static inline trace_return( sh4addr_t source, sh4addr_t dest )
232 {
233 if( call_stack_depth > 0 ) {
234 call_stack_depth--;
235 }
236 }
238 void fprint_stack_trace( FILE *f )
239 {
240 int i = call_stack_depth -1;
241 if( i >= MAX_CALLSTACK )
242 i = MAX_CALLSTACK - 1;
243 for( ; i >= 0; i-- ) {
244 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
245 (call_stack_depth - i), call_stack[i].call_addr,
246 call_stack[i].target_addr, call_stack[i].stack_pointer );
247 }
248 }
250 #define TRACE_CALL( source, dest ) trace_call(source, dest)
251 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
252 #else
253 #define TRACE_CALL( dest, rts )
254 #define TRACE_RETURN( source, dest )
255 #endif
257 #define RAISE( x, v, pcadj ) do{ \
258 if( sh4r.vbr == 0 ) { \
259 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
260 dreamcast_stop(); return FALSE; \
261 } else { \
262 sh4r.spc = sh4r.pc + pcadj; \
263 sh4r.ssr = sh4_read_sr(); \
264 sh4r.sgr = sh4r.r[15]; \
265 MMIO_WRITE(MMU,EXPEVT,x); \
266 sh4r.pc = sh4r.vbr + v; \
267 sh4r.new_pc = sh4r.pc + 2; \
268 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
269 } \
270 return TRUE; } while(0)
273 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
274 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
275 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
276 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
277 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
278 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
280 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
282 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
284 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
286 #define CHECK( x, c, v ) if( !x ) RAISE( c, v, 0 )
287 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
288 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP, 0 )
289 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_READ_ADDR_ERR, EXV_TRAP, 0 )
290 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP, 0 )
291 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) RAISE( EXC_WRITE_ADDR_ERR, EXV_TRAP, 0 )
293 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
294 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
295 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL, -2); }
297 static void sh4_switch_banks( )
298 {
299 uint32_t tmp[8];
301 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
302 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
303 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
304 }
306 static void sh4_load_sr( uint32_t newval )
307 {
308 if( (newval ^ sh4r.sr) & SR_RB )
309 sh4_switch_banks();
310 sh4r.sr = newval;
311 sh4r.t = (newval&SR_T) ? 1 : 0;
312 sh4r.s = (newval&SR_S) ? 1 : 0;
313 sh4r.m = (newval&SR_M) ? 1 : 0;
314 sh4r.q = (newval&SR_Q) ? 1 : 0;
315 intc_mask_changed();
316 }
318 static void sh4_write_float( uint32_t addr, int reg )
319 {
320 if( IS_FPU_DOUBLESIZE() ) {
321 if( reg & 1 ) {
322 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
323 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
324 } else {
325 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
326 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
327 }
328 } else {
329 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
330 }
331 }
333 static void sh4_read_float( uint32_t addr, int reg )
334 {
335 if( IS_FPU_DOUBLESIZE() ) {
336 if( reg & 1 ) {
337 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
338 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
339 } else {
340 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
341 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
342 }
343 } else {
344 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
345 }
346 }
348 static uint32_t sh4_read_sr( void )
349 {
350 /* synchronize sh4r.sr with the various bitflags */
351 sh4r.sr &= SR_MQSTMASK;
352 if( sh4r.t ) sh4r.sr |= SR_T;
353 if( sh4r.s ) sh4r.sr |= SR_S;
354 if( sh4r.m ) sh4r.sr |= SR_M;
355 if( sh4r.q ) sh4r.sr |= SR_Q;
356 return sh4r.sr;
357 }
358 /* function for external use */
359 void sh4_raise_exception( int code, int vector )
360 {
361 RAISE(code, vector, 0);
362 }
364 static void sh4_accept_interrupt( void )
365 {
366 uint32_t code = intc_accept_interrupt();
367 sh4r.ssr = sh4_read_sr();
368 sh4r.spc = sh4r.pc;
369 sh4r.sgr = sh4r.r[15];
370 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
371 MMIO_WRITE( MMU, INTEVT, code );
372 sh4r.pc = sh4r.vbr + 0x600;
373 sh4r.new_pc = sh4r.pc + 2;
374 // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
375 }
377 gboolean sh4_execute_instruction( void )
378 {
379 uint32_t pc;
380 unsigned short ir;
381 uint32_t tmp;
382 uint64_t tmpl;
383 float ftmp;
384 double dtmp;
386 #define R0 sh4r.r[0]
387 #define FR0 FR(0)
388 #define DR0 DR(0)
389 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
390 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
391 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
392 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
393 #define DISP8(ir) (ir&0x00FF)
394 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
395 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
396 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
397 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
398 #define FRNn(ir) ((ir&0x0F00)>>8)
399 #define FRMn(ir) ((ir&0x00F0)>>4)
400 #define DRNn(ir) ((ir&0x0E00)>>9)
401 #define DRMn(ir) ((ir&0x00E0)>>5)
402 #define FVN(ir) ((ir&0x0C00)>>8)
403 #define FVM(ir) ((ir&0x0300)>>6)
404 #define FRN(ir) FR(FRNn(ir))
405 #define FRM(ir) FR(FRMn(ir))
406 #define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir))))
407 #define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir))))
408 #define DRN(ir) DRb(DRNn(ir), ir&0x0100)
409 #define DRM(ir) DRb(DRMn(ir),ir&0x0010)
410 #define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir))))
411 #define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir))))
412 #define FPULf *((float *)&sh4r.fpul)
413 #define FPULi (sh4r.fpul)
415 if( SH4_INT_PENDING() )
416 sh4_accept_interrupt();
418 pc = sh4r.pc;
419 if( pc > 0xFFFFFF00 ) {
420 /* SYSCALL Magic */
421 syscall_invoke( pc );
422 sh4r.in_delay_slot = 0;
423 pc = sh4r.pc = sh4r.pr;
424 sh4r.new_pc = sh4r.pc + 2;
425 }
426 CHECKRALIGN16(pc);
427 ir = MEM_READ_WORD(pc);
428 sh4r.icount++;
430 switch( (ir&0xF000)>>12 ) {
431 case 0: /* 0000nnnnmmmmxxxx */
432 switch( ir&0x000F ) {
433 case 2:
434 switch( (ir&0x00F0)>>4 ) {
435 case 0: /* STC SR, Rn */
436 CHECKPRIV();
437 RN(ir) = sh4_read_sr();
438 break;
439 case 1: /* STC GBR, Rn */
440 RN(ir) = sh4r.gbr;
441 break;
442 case 2: /* STC VBR, Rn */
443 CHECKPRIV();
444 RN(ir) = sh4r.vbr;
445 break;
446 case 3: /* STC SSR, Rn */
447 CHECKPRIV();
448 RN(ir) = sh4r.ssr;
449 break;
450 case 4: /* STC SPC, Rn */
451 CHECKPRIV();
452 RN(ir) = sh4r.spc;
453 break;
454 case 8: case 9: case 10: case 11: case 12: case 13:
455 case 14: case 15:/* STC Rm_bank, Rn */
456 CHECKPRIV();
457 RN(ir) = RN_BANK(ir);
458 break;
459 default: UNDEF(ir);
460 }
461 break;
462 case 3:
463 switch( (ir&0x00F0)>>4 ) {
464 case 0: /* BSRF Rn */
465 CHECKDEST( pc + 4 + RN(ir) );
466 CHECKSLOTILLEGAL();
467 sh4r.in_delay_slot = 1;
468 sh4r.pr = sh4r.pc + 4;
469 sh4r.pc = sh4r.new_pc;
470 sh4r.new_pc = pc + 4 + RN(ir);
471 TRACE_CALL( pc, sh4r.new_pc );
472 return TRUE;
473 case 2: /* BRAF Rn */
474 CHECKDEST( pc + 4 + RN(ir) );
475 CHECKSLOTILLEGAL();
476 sh4r.in_delay_slot = 1;
477 sh4r.pc = sh4r.new_pc;
478 sh4r.new_pc = pc + 4 + RN(ir);
479 return TRUE;
480 case 8: /* PREF [Rn] */
481 tmp = RN(ir);
482 if( (tmp & 0xFC000000) == 0xE0000000 ) {
483 /* Store queue operation */
484 int queue = (tmp&0x20)>>2;
485 int32_t *src = &sh4r.store_queue[queue];
486 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
487 uint32_t target = tmp&0x03FFFFE0 | hi;
488 mem_copy_to_sh4( target, src, 32 );
489 }
490 break;
491 case 9: /* OCBI [Rn] */
492 case 10:/* OCBP [Rn] */
493 case 11:/* OCBWB [Rn] */
494 /* anything? */
495 break;
496 case 12:/* MOVCA.L R0, [Rn] */
497 tmp = RN(ir);
498 CHECKWALIGN32(tmp);
499 MEM_WRITE_LONG( tmp, R0 );
500 break;
501 default: UNDEF(ir);
502 }
503 break;
504 case 4: /* MOV.B Rm, [R0 + Rn] */
505 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
506 break;
507 case 5: /* MOV.W Rm, [R0 + Rn] */
508 CHECKWALIGN16( R0 + RN(ir) );
509 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
510 break;
511 case 6: /* MOV.L Rm, [R0 + Rn] */
512 CHECKWALIGN32( R0 + RN(ir) );
513 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
514 break;
515 case 7: /* MUL.L Rm, Rn */
516 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
517 (RM(ir) * RN(ir));
518 break;
519 case 8:
520 switch( (ir&0x0FF0)>>4 ) {
521 case 0: /* CLRT */
522 sh4r.t = 0;
523 break;
524 case 1: /* SETT */
525 sh4r.t = 1;
526 break;
527 case 2: /* CLRMAC */
528 sh4r.mac = 0;
529 break;
530 case 3: /* LDTLB */
531 break;
532 case 4: /* CLRS */
533 sh4r.s = 0;
534 break;
535 case 5: /* SETS */
536 sh4r.s = 1;
537 break;
538 default: UNDEF(ir);
539 }
540 break;
541 case 9:
542 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
543 RN(ir) = sh4r.t;
544 else if( ir == 0x0019 ) /* DIV0U */
545 sh4r.m = sh4r.q = sh4r.t = 0;
546 else if( ir == 0x0009 )
547 /* NOP */;
548 else UNDEF(ir);
549 break;
550 case 10:
551 switch( (ir&0x00F0) >> 4 ) {
552 case 0: /* STS MACH, Rn */
553 RN(ir) = sh4r.mac >> 32;
554 break;
555 case 1: /* STS MACL, Rn */
556 RN(ir) = (uint32_t)sh4r.mac;
557 break;
558 case 2: /* STS PR, Rn */
559 RN(ir) = sh4r.pr;
560 break;
561 case 3: /* STC SGR, Rn */
562 CHECKPRIV();
563 RN(ir) = sh4r.sgr;
564 break;
565 case 5:/* STS FPUL, Rn */
566 RN(ir) = sh4r.fpul;
567 break;
568 case 6: /* STS FPSCR, Rn */
569 RN(ir) = sh4r.fpscr;
570 break;
571 case 15:/* STC DBR, Rn */
572 CHECKPRIV();
573 RN(ir) = sh4r.dbr;
574 break;
575 default: UNDEF(ir);
576 }
577 break;
578 case 11:
579 switch( (ir&0x0FF0)>>4 ) {
580 case 0: /* RTS */
581 CHECKDEST( sh4r.pr );
582 CHECKSLOTILLEGAL();
583 sh4r.in_delay_slot = 1;
584 sh4r.pc = sh4r.new_pc;
585 sh4r.new_pc = sh4r.pr;
586 TRACE_RETURN( pc, sh4r.new_pc );
587 return TRUE;
588 case 1: /* SLEEP */
589 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
590 sh4r.sh4_state = SH4_STATE_STANDBY;
591 } else {
592 sh4r.sh4_state = SH4_STATE_SLEEP;
593 }
594 return FALSE; /* Halt CPU */
595 case 2: /* RTE */
596 CHECKPRIV();
597 CHECKDEST( sh4r.spc );
598 CHECKSLOTILLEGAL();
599 sh4r.in_delay_slot = 1;
600 sh4r.pc = sh4r.new_pc;
601 sh4r.new_pc = sh4r.spc;
602 sh4_load_sr( sh4r.ssr );
603 return TRUE;
604 default:UNDEF(ir);
605 }
606 break;
607 case 12:/* MOV.B [R0+R%d], R%d */
608 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
609 break;
610 case 13:/* MOV.W [R0+R%d], R%d */
611 CHECKRALIGN16( R0 + RM(ir) );
612 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
613 break;
614 case 14:/* MOV.L [R0+R%d], R%d */
615 CHECKRALIGN32( R0 + RM(ir) );
616 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
617 break;
618 case 15:/* MAC.L [Rm++], [Rn++] */
619 CHECKRALIGN32( RM(ir) );
620 CHECKRALIGN32( RN(ir) );
621 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
622 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
623 if( sh4r.s ) {
624 /* 48-bit Saturation. Yuch */
625 tmpl += SIGNEXT48(sh4r.mac);
626 if( tmpl < 0xFFFF800000000000LL )
627 tmpl = 0xFFFF800000000000LL;
628 else if( tmpl > 0x00007FFFFFFFFFFFLL )
629 tmpl = 0x00007FFFFFFFFFFFLL;
630 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
631 (tmpl&0x0000FFFFFFFFFFFFLL);
632 } else sh4r.mac = tmpl;
634 RM(ir) += 4;
635 RN(ir) += 4;
637 break;
638 default: UNDEF(ir);
639 }
640 break;
641 case 1: /* 0001nnnnmmmmdddd */
642 /* MOV.L Rm, [Rn + disp4*4] */
643 tmp = RN(ir) + (DISP4(ir)<<2);
644 CHECKWALIGN32( tmp );
645 MEM_WRITE_LONG( tmp, RM(ir) );
646 break;
647 case 2: /* 0010nnnnmmmmxxxx */
648 switch( ir&0x000F ) {
649 case 0: /* MOV.B Rm, [Rn] */
650 MEM_WRITE_BYTE( RN(ir), RM(ir) );
651 break;
652 case 1: /* MOV.W Rm, [Rn] */
653 CHECKWALIGN16( RN(ir) );
654 MEM_WRITE_WORD( RN(ir), RM(ir) );
655 break;
656 case 2: /* MOV.L Rm, [Rn] */
657 CHECKWALIGN32( RN(ir) );
658 MEM_WRITE_LONG( RN(ir), RM(ir) );
659 break;
660 case 3: UNDEF(ir);
661 break;
662 case 4: /* MOV.B Rm, [--Rn] */
663 RN(ir) --;
664 MEM_WRITE_BYTE( RN(ir), RM(ir) );
665 break;
666 case 5: /* MOV.W Rm, [--Rn] */
667 RN(ir) -= 2;
668 CHECKWALIGN16( RN(ir) );
669 MEM_WRITE_WORD( RN(ir), RM(ir) );
670 break;
671 case 6: /* MOV.L Rm, [--Rn] */
672 RN(ir) -= 4;
673 CHECKWALIGN32( RN(ir) );
674 MEM_WRITE_LONG( RN(ir), RM(ir) );
675 break;
676 case 7: /* DIV0S Rm, Rn */
677 sh4r.q = RN(ir)>>31;
678 sh4r.m = RM(ir)>>31;
679 sh4r.t = sh4r.q ^ sh4r.m;
680 break;
681 case 8: /* TST Rm, Rn */
682 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
683 break;
684 case 9: /* AND Rm, Rn */
685 RN(ir) &= RM(ir);
686 break;
687 case 10:/* XOR Rm, Rn */
688 RN(ir) ^= RM(ir);
689 break;
690 case 11:/* OR Rm, Rn */
691 RN(ir) |= RM(ir);
692 break;
693 case 12:/* CMP/STR Rm, Rn */
694 /* set T = 1 if any byte in RM & RN is the same */
695 tmp = RM(ir) ^ RN(ir);
696 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
697 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
698 break;
699 case 13:/* XTRCT Rm, Rn */
700 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
701 break;
702 case 14:/* MULU.W Rm, Rn */
703 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
704 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
705 break;
706 case 15:/* MULS.W Rm, Rn */
707 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
708 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
709 break;
710 }
711 break;
712 case 3: /* 0011nnnnmmmmxxxx */
713 switch( ir&0x000F ) {
714 case 0: /* CMP/EQ Rm, Rn */
715 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
716 break;
717 case 2: /* CMP/HS Rm, Rn */
718 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
719 break;
720 case 3: /* CMP/GE Rm, Rn */
721 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
722 break;
723 case 4: { /* DIV1 Rm, Rn */
724 /* This is just from the sh4p manual with some
725 * simplifications (someone want to check it's correct? :)
726 * Why they couldn't just provide a real DIV instruction...
727 * Please oh please let the translator batch these things
728 * up into a single DIV... */
729 uint32_t tmp0, tmp1, tmp2, dir;
731 dir = sh4r.q ^ sh4r.m;
732 sh4r.q = (RN(ir) >> 31);
733 tmp2 = RM(ir);
734 RN(ir) = (RN(ir) << 1) | sh4r.t;
735 tmp0 = RN(ir);
736 if( dir ) {
737 RN(ir) += tmp2;
738 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
739 } else {
740 RN(ir) -= tmp2;
741 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
742 }
743 sh4r.q ^= sh4r.m ^ tmp1;
744 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
745 break; }
746 case 5: /* DMULU.L Rm, Rn */
747 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
748 break;
749 case 6: /* CMP/HI Rm, Rn */
750 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
751 break;
752 case 7: /* CMP/GT Rm, Rn */
753 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
754 break;
755 case 8: /* SUB Rm, Rn */
756 RN(ir) -= RM(ir);
757 break;
758 case 10:/* SUBC Rm, Rn */
759 tmp = RN(ir);
760 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
761 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
762 break;
763 case 11:/* SUBV Rm, Rn */
764 UNIMP(ir);
765 break;
766 case 12:/* ADD Rm, Rn */
767 RN(ir) += RM(ir);
768 break;
769 case 13:/* DMULS.L Rm, Rn */
770 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
771 break;
772 case 14:/* ADDC Rm, Rn */
773 tmp = RN(ir);
774 RN(ir) += RM(ir) + sh4r.t;
775 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
776 break;
777 case 15:/* ADDV Rm, Rn */
778 tmp = RN(ir) + RM(ir);
779 sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) );
780 RN(ir) = tmp;
781 break;
782 default: UNDEF(ir);
783 }
784 break;
785 case 4: /* 0100nnnnxxxxxxxx */
786 switch( ir&0x00FF ) {
787 case 0x00: /* SHLL Rn */
788 sh4r.t = RN(ir) >> 31;
789 RN(ir) <<= 1;
790 break;
791 case 0x01: /* SHLR Rn */
792 sh4r.t = RN(ir) & 0x00000001;
793 RN(ir) >>= 1;
794 break;
795 case 0x02: /* STS.L MACH, [--Rn] */
796 RN(ir) -= 4;
797 CHECKWALIGN32( RN(ir) );
798 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
799 break;
800 case 0x03: /* STC.L SR, [--Rn] */
801 CHECKPRIV();
802 RN(ir) -= 4;
803 CHECKWALIGN32( RN(ir) );
804 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
805 break;
806 case 0x04: /* ROTL Rn */
807 sh4r.t = RN(ir) >> 31;
808 RN(ir) <<= 1;
809 RN(ir) |= sh4r.t;
810 break;
811 case 0x05: /* ROTR Rn */
812 sh4r.t = RN(ir) & 0x00000001;
813 RN(ir) >>= 1;
814 RN(ir) |= (sh4r.t << 31);
815 break;
816 case 0x06: /* LDS.L [Rn++], MACH */
817 CHECKRALIGN32( RN(ir) );
818 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
819 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
820 RN(ir) += 4;
821 break;
822 case 0x07: /* LDC.L [Rn++], SR */
823 CHECKPRIV();
824 CHECKWALIGN32( RN(ir) );
825 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
826 RN(ir) +=4;
827 break;
828 case 0x08: /* SHLL2 Rn */
829 RN(ir) <<= 2;
830 break;
831 case 0x09: /* SHLR2 Rn */
832 RN(ir) >>= 2;
833 break;
834 case 0x0A: /* LDS Rn, MACH */
835 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
836 (((uint64_t)RN(ir))<<32);
837 break;
838 case 0x0B: /* JSR [Rn] */
839 CHECKDEST( RN(ir) );
840 CHECKSLOTILLEGAL();
841 sh4r.in_delay_slot = 1;
842 sh4r.pc = sh4r.new_pc;
843 sh4r.new_pc = RN(ir);
844 sh4r.pr = pc + 4;
845 TRACE_CALL( pc, sh4r.new_pc );
846 return TRUE;
847 case 0x0E: /* LDC Rn, SR */
848 CHECKPRIV();
849 sh4_load_sr( RN(ir) );
850 break;
851 case 0x10: /* DT Rn */
852 RN(ir) --;
853 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
854 break;
855 case 0x11: /* CMP/PZ Rn */
856 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
857 break;
858 case 0x12: /* STS.L MACL, [--Rn] */
859 RN(ir) -= 4;
860 CHECKWALIGN32( RN(ir) );
861 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
862 break;
863 case 0x13: /* STC.L GBR, [--Rn] */
864 RN(ir) -= 4;
865 CHECKWALIGN32( RN(ir) );
866 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
867 break;
868 case 0x15: /* CMP/PL Rn */
869 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
870 break;
871 case 0x16: /* LDS.L [Rn++], MACL */
872 CHECKRALIGN32( RN(ir) );
873 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
874 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
875 RN(ir) += 4;
876 break;
877 case 0x17: /* LDC.L [Rn++], GBR */
878 CHECKRALIGN32( RN(ir) );
879 sh4r.gbr = MEM_READ_LONG(RN(ir));
880 RN(ir) +=4;
881 break;
882 case 0x18: /* SHLL8 Rn */
883 RN(ir) <<= 8;
884 break;
885 case 0x19: /* SHLR8 Rn */
886 RN(ir) >>= 8;
887 break;
888 case 0x1A: /* LDS Rn, MACL */
889 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
890 (uint64_t)((uint32_t)(RN(ir)));
891 break;
892 case 0x1B: /* TAS.B [Rn] */
893 tmp = MEM_READ_BYTE( RN(ir) );
894 sh4r.t = ( tmp == 0 ? 1 : 0 );
895 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
896 break;
897 case 0x1E: /* LDC Rn, GBR */
898 sh4r.gbr = RN(ir);
899 break;
900 case 0x20: /* SHAL Rn */
901 sh4r.t = RN(ir) >> 31;
902 RN(ir) <<= 1;
903 break;
904 case 0x21: /* SHAR Rn */
905 sh4r.t = RN(ir) & 0x00000001;
906 RN(ir) = ((int32_t)RN(ir)) >> 1;
907 break;
908 case 0x22: /* STS.L PR, [--Rn] */
909 RN(ir) -= 4;
910 CHECKWALIGN32( RN(ir) );
911 MEM_WRITE_LONG( RN(ir), sh4r.pr );
912 break;
913 case 0x23: /* STC.L VBR, [--Rn] */
914 CHECKPRIV();
915 RN(ir) -= 4;
916 CHECKWALIGN32( RN(ir) );
917 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
918 break;
919 case 0x24: /* ROTCL Rn */
920 tmp = RN(ir) >> 31;
921 RN(ir) <<= 1;
922 RN(ir) |= sh4r.t;
923 sh4r.t = tmp;
924 break;
925 case 0x25: /* ROTCR Rn */
926 tmp = RN(ir) & 0x00000001;
927 RN(ir) >>= 1;
928 RN(ir) |= (sh4r.t << 31 );
929 sh4r.t = tmp;
930 break;
931 case 0x26: /* LDS.L [Rn++], PR */
932 CHECKRALIGN32( RN(ir) );
933 sh4r.pr = MEM_READ_LONG( RN(ir) );
934 RN(ir) += 4;
935 break;
936 case 0x27: /* LDC.L [Rn++], VBR */
937 CHECKPRIV();
938 CHECKRALIGN32( RN(ir) );
939 sh4r.vbr = MEM_READ_LONG(RN(ir));
940 RN(ir) +=4;
941 break;
942 case 0x28: /* SHLL16 Rn */
943 RN(ir) <<= 16;
944 break;
945 case 0x29: /* SHLR16 Rn */
946 RN(ir) >>= 16;
947 break;
948 case 0x2A: /* LDS Rn, PR */
949 sh4r.pr = RN(ir);
950 break;
951 case 0x2B: /* JMP [Rn] */
952 CHECKDEST( RN(ir) );
953 CHECKSLOTILLEGAL();
954 sh4r.in_delay_slot = 1;
955 sh4r.pc = sh4r.new_pc;
956 sh4r.new_pc = RN(ir);
957 return TRUE;
958 case 0x2E: /* LDC Rn, VBR */
959 CHECKPRIV();
960 sh4r.vbr = RN(ir);
961 break;
962 case 0x32: /* STC.L SGR, [--Rn] */
963 CHECKPRIV();
964 RN(ir) -= 4;
965 CHECKWALIGN32( RN(ir) );
966 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
967 break;
968 case 0x33: /* STC.L SSR, [--Rn] */
969 CHECKPRIV();
970 RN(ir) -= 4;
971 CHECKWALIGN32( RN(ir) );
972 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
973 break;
974 case 0x37: /* LDC.L [Rn++], SSR */
975 CHECKPRIV();
976 CHECKRALIGN32( RN(ir) );
977 sh4r.ssr = MEM_READ_LONG(RN(ir));
978 RN(ir) +=4;
979 break;
980 case 0x3E: /* LDC Rn, SSR */
981 CHECKPRIV();
982 sh4r.ssr = RN(ir);
983 break;
984 case 0x43: /* STC.L SPC, [--Rn] */
985 CHECKPRIV();
986 RN(ir) -= 4;
987 CHECKWALIGN32( RN(ir) );
988 MEM_WRITE_LONG( RN(ir), sh4r.spc );
989 break;
990 case 0x47: /* LDC.L [Rn++], SPC */
991 CHECKPRIV();
992 CHECKRALIGN32( RN(ir) );
993 sh4r.spc = MEM_READ_LONG(RN(ir));
994 RN(ir) +=4;
995 break;
996 case 0x4E: /* LDC Rn, SPC */
997 CHECKPRIV();
998 sh4r.spc = RN(ir);
999 break;
1000 case 0x52: /* STS.L FPUL, [--Rn] */
1001 RN(ir) -= 4;
1002 CHECKWALIGN32( RN(ir) );
1003 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
1004 break;
1005 case 0x56: /* LDS.L [Rn++], FPUL */
1006 CHECKRALIGN32( RN(ir) );
1007 sh4r.fpul = MEM_READ_LONG(RN(ir));
1008 RN(ir) +=4;
1009 break;
1010 case 0x5A: /* LDS Rn, FPUL */
1011 sh4r.fpul = RN(ir);
1012 break;
1013 case 0x62: /* STS.L FPSCR, [--Rn] */
1014 RN(ir) -= 4;
1015 CHECKWALIGN32( RN(ir) );
1016 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
1017 break;
1018 case 0x66: /* LDS.L [Rn++], FPSCR */
1019 CHECKRALIGN32( RN(ir) );
1020 sh4r.fpscr = MEM_READ_LONG(RN(ir));
1021 RN(ir) +=4;
1022 break;
1023 case 0x6A: /* LDS Rn, FPSCR */
1024 sh4r.fpscr = RN(ir);
1025 break;
1026 case 0xF2: /* STC.L DBR, [--Rn] */
1027 CHECKPRIV();
1028 RN(ir) -= 4;
1029 CHECKWALIGN32( RN(ir) );
1030 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
1031 break;
1032 case 0xF6: /* LDC.L [Rn++], DBR */
1033 CHECKPRIV();
1034 CHECKRALIGN32( RN(ir) );
1035 sh4r.dbr = MEM_READ_LONG(RN(ir));
1036 RN(ir) +=4;
1037 break;
1038 case 0xFA: /* LDC Rn, DBR */
1039 CHECKPRIV();
1040 sh4r.dbr = RN(ir);
1041 break;
1042 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
1043 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
1044 CHECKPRIV();
1045 RN(ir) -= 4;
1046 CHECKWALIGN32( RN(ir) );
1047 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
1048 break;
1049 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
1050 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
1051 CHECKPRIV();
1052 CHECKRALIGN32( RN(ir) );
1053 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
1054 RN(ir) += 4;
1055 break;
1056 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
1057 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
1058 CHECKPRIV();
1059 RN_BANK(ir) = RM(ir);
1060 break;
1061 default:
1062 if( (ir&0x000F) == 0x0F ) {
1063 /* MAC.W [Rm++], [Rn++] */
1064 CHECKRALIGN16( RN(ir) );
1065 CHECKRALIGN16( RM(ir) );
1066 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
1067 SIGNEXT16(MEM_READ_WORD(RN(ir)));
1068 if( sh4r.s ) {
1069 /* FIXME */
1070 UNIMP(ir);
1071 } else sh4r.mac += SIGNEXT32(tmp);
1072 RM(ir) += 2;
1073 RN(ir) += 2;
1074 } else if( (ir&0x000F) == 0x0C ) {
1075 /* SHAD Rm, Rn */
1076 tmp = RM(ir);
1077 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1078 else if( (tmp & 0x1F) == 0 )
1079 RN(ir) = ((int32_t)RN(ir)) >> 31;
1080 else
1081 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
1082 } else if( (ir&0x000F) == 0x0D ) {
1083 /* SHLD Rm, Rn */
1084 tmp = RM(ir);
1085 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
1086 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
1087 else RN(ir) >>= (((~tmp) & 0x1F)+1);
1088 } else UNDEF(ir);
1089 }
1090 break;
1091 case 5: /* 0101nnnnmmmmdddd */
1092 /* MOV.L [Rm + disp4*4], Rn */
1093 tmp = RM(ir) + (DISP4(ir)<<2);
1094 CHECKRALIGN32( tmp );
1095 RN(ir) = MEM_READ_LONG( tmp );
1096 break;
1097 case 6: /* 0110xxxxxxxxxxxx */
1098 switch( ir&0x000f ) {
1099 case 0: /* MOV.B [Rm], Rn */
1100 RN(ir) = MEM_READ_BYTE( RM(ir) );
1101 break;
1102 case 1: /* MOV.W [Rm], Rn */
1103 CHECKRALIGN16( RM(ir) );
1104 RN(ir) = MEM_READ_WORD( RM(ir) );
1105 break;
1106 case 2: /* MOV.L [Rm], Rn */
1107 CHECKRALIGN32( RM(ir) );
1108 RN(ir) = MEM_READ_LONG( RM(ir) );
1109 break;
1110 case 3: /* MOV Rm, Rn */
1111 RN(ir) = RM(ir);
1112 break;
1113 case 4: /* MOV.B [Rm++], Rn */
1114 RN(ir) = MEM_READ_BYTE( RM(ir) );
1115 RM(ir) ++;
1116 break;
1117 case 5: /* MOV.W [Rm++], Rn */
1118 CHECKRALIGN16( RM(ir) );
1119 RN(ir) = MEM_READ_WORD( RM(ir) );
1120 RM(ir) += 2;
1121 break;
1122 case 6: /* MOV.L [Rm++], Rn */
1123 CHECKRALIGN32( RM(ir) );
1124 RN(ir) = MEM_READ_LONG( RM(ir) );
1125 RM(ir) += 4;
1126 break;
1127 case 7: /* NOT Rm, Rn */
1128 RN(ir) = ~RM(ir);
1129 break;
1130 case 8: /* SWAP.B Rm, Rn */
1131 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
1132 ((RM(ir)&0x000000FF)<<8);
1133 break;
1134 case 9: /* SWAP.W Rm, Rn */
1135 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
1136 break;
1137 case 10:/* NEGC Rm, Rn */
1138 tmp = 0 - RM(ir);
1139 RN(ir) = tmp - sh4r.t;
1140 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
1141 break;
1142 case 11:/* NEG Rm, Rn */
1143 RN(ir) = 0 - RM(ir);
1144 break;
1145 case 12:/* EXTU.B Rm, Rn */
1146 RN(ir) = RM(ir)&0x000000FF;
1147 break;
1148 case 13:/* EXTU.W Rm, Rn */
1149 RN(ir) = RM(ir)&0x0000FFFF;
1150 break;
1151 case 14:/* EXTS.B Rm, Rn */
1152 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
1153 break;
1154 case 15:/* EXTS.W Rm, Rn */
1155 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
1156 break;
1157 }
1158 break;
1159 case 7: /* 0111nnnniiiiiiii */
1160 /* ADD imm8, Rn */
1161 RN(ir) += IMM8(ir);
1162 break;
1163 case 8: /* 1000xxxxxxxxxxxx */
1164 switch( (ir&0x0F00) >> 8 ) {
1165 case 0: /* MOV.B R0, [Rm + disp4] */
1166 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
1167 break;
1168 case 1: /* MOV.W R0, [Rm + disp4*2] */
1169 tmp = RM(ir) + (DISP4(ir)<<1);
1170 CHECKWALIGN16( tmp );
1171 MEM_WRITE_WORD( tmp, R0 );
1172 break;
1173 case 4: /* MOV.B [Rm + disp4], R0 */
1174 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
1175 break;
1176 case 5: /* MOV.W [Rm + disp4*2], R0 */
1177 tmp = RM(ir) + (DISP4(ir)<<1);
1178 CHECKRALIGN16( tmp );
1179 R0 = MEM_READ_WORD( tmp );
1180 break;
1181 case 8: /* CMP/EQ imm, R0 */
1182 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
1183 break;
1184 case 9: /* BT disp8 */
1185 CHECKSLOTILLEGAL()
1186 if( sh4r.t ) {
1187 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1188 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1189 sh4r.new_pc = sh4r.pc + 2;
1190 return TRUE;
1191 }
1192 break;
1193 case 11:/* BF disp8 */
1194 CHECKSLOTILLEGAL()
1195 if( !sh4r.t ) {
1196 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1197 sh4r.pc += (PCDISP8(ir)<<1) + 4;
1198 sh4r.new_pc = sh4r.pc + 2;
1199 return TRUE;
1200 }
1201 break;
1202 case 13:/* BT/S disp8 */
1203 CHECKSLOTILLEGAL()
1204 if( sh4r.t ) {
1205 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1206 sh4r.in_delay_slot = 1;
1207 sh4r.pc = sh4r.new_pc;
1208 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1209 sh4r.in_delay_slot = 1;
1210 return TRUE;
1211 }
1212 break;
1213 case 15:/* BF/S disp8 */
1214 CHECKSLOTILLEGAL()
1215 if( !sh4r.t ) {
1216 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
1217 sh4r.in_delay_slot = 1;
1218 sh4r.pc = sh4r.new_pc;
1219 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
1220 return TRUE;
1221 }
1222 break;
1223 default: UNDEF(ir);
1224 }
1225 break;
1226 case 9: /* 1001xxxxxxxxxxxx */
1227 /* MOV.W [disp8*2 + pc + 4], Rn */
1228 tmp = pc + 4 + (DISP8(ir)<<1);
1229 CHECKRALIGN16( tmp );
1230 RN(ir) = MEM_READ_WORD( tmp );
1231 break;
1232 case 10:/* 1010dddddddddddd */
1233 /* BRA disp12 */
1234 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1235 CHECKSLOTILLEGAL()
1236 sh4r.in_delay_slot = 1;
1237 sh4r.pc = sh4r.new_pc;
1238 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1239 return TRUE;
1240 case 11:/* 1011dddddddddddd */
1241 /* BSR disp12 */
1242 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
1243 CHECKSLOTILLEGAL()
1244 sh4r.in_delay_slot = 1;
1245 sh4r.pr = pc + 4;
1246 sh4r.pc = sh4r.new_pc;
1247 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1248 TRACE_CALL( pc, sh4r.new_pc );
1249 return TRUE;
1250 case 12:/* 1100xxxxdddddddd */
1251 switch( (ir&0x0F00)>>8 ) {
1252 case 0: /* MOV.B R0, [GBR + disp8] */
1253 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1254 break;
1255 case 1: /* MOV.W R0, [GBR + disp8*2] */
1256 tmp = sh4r.gbr + (DISP8(ir)<<1);
1257 CHECKWALIGN16( tmp );
1258 MEM_WRITE_WORD( tmp, R0 );
1259 break;
1260 case 2: /*MOV.L R0, [GBR + disp8*4] */
1261 tmp = sh4r.gbr + (DISP8(ir)<<2);
1262 CHECKWALIGN32( tmp );
1263 MEM_WRITE_LONG( tmp, R0 );
1264 break;
1265 case 3: /* TRAPA imm8 */
1266 CHECKSLOTILLEGAL()
1267 sh4r.in_delay_slot = 1;
1268 MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 );
1269 RAISE( EXC_TRAP, EXV_TRAP, 2 );
1270 break;
1271 case 4: /* MOV.B [GBR + disp8], R0 */
1272 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1273 break;
1274 case 5: /* MOV.W [GBR + disp8*2], R0 */
1275 tmp = sh4r.gbr + (DISP8(ir)<<1);
1276 CHECKRALIGN16( tmp );
1277 R0 = MEM_READ_WORD( tmp );
1278 break;
1279 case 6: /* MOV.L [GBR + disp8*4], R0 */
1280 tmp = sh4r.gbr + (DISP8(ir)<<2);
1281 CHECKRALIGN32( tmp );
1282 R0 = MEM_READ_LONG( tmp );
1283 break;
1284 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1285 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1286 break;
1287 case 8: /* TST imm8, R0 */
1288 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1289 break;
1290 case 9: /* AND imm8, R0 */
1291 R0 &= UIMM8(ir);
1292 break;
1293 case 10:/* XOR imm8, R0 */
1294 R0 ^= UIMM8(ir);
1295 break;
1296 case 11:/* OR imm8, R0 */
1297 R0 |= UIMM8(ir);
1298 break;
1299 case 12:/* TST.B imm8, [R0+GBR] */
1300 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1301 break;
1302 case 13:/* AND.B imm8, [R0+GBR] */
1303 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1304 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1305 break;
1306 case 14:/* XOR.B imm8, [R0+GBR] */
1307 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1308 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1309 break;
1310 case 15:/* OR.B imm8, [R0+GBR] */
1311 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1312 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1313 break;
1314 }
1315 break;
1316 case 13:/* 1101nnnndddddddd */
1317 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1318 tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1319 CHECKRALIGN32( tmp );
1320 RN(ir) = MEM_READ_LONG( tmp );
1321 break;
1322 case 14:/* 1110nnnniiiiiiii */
1323 /* MOV imm8, Rn */
1324 RN(ir) = IMM8(ir);
1325 break;
1326 case 15:/* 1111xxxxxxxxxxxx */
1327 CHECKFPUEN();
1328 if( IS_FPU_DOUBLEPREC() ) {
1329 switch( ir&0x000F ) {
1330 case 0: /* FADD FRm, FRn */
1331 DRN(ir) += DRM(ir);
1332 break;
1333 case 1: /* FSUB FRm, FRn */
1334 DRN(ir) -= DRM(ir);
1335 break;
1336 case 2: /* FMUL FRm, FRn */
1337 DRN(ir) = DRN(ir) * DRM(ir);
1338 break;
1339 case 3: /* FDIV FRm, FRn */
1340 DRN(ir) = DRN(ir) / DRM(ir);
1341 break;
1342 case 4: /* FCMP/EQ FRm, FRn */
1343 sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 );
1344 break;
1345 case 5: /* FCMP/GT FRm, FRn */
1346 sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 );
1347 break;
1348 case 6: /* FMOV.S [Rm+R0], FRn */
1349 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1350 break;
1351 case 7: /* FMOV.S FRm, [Rn+R0] */
1352 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1353 break;
1354 case 8: /* FMOV.S [Rm], FRn */
1355 MEM_FP_READ( RM(ir), FRNn(ir) );
1356 break;
1357 case 9: /* FMOV.S [Rm++], FRn */
1358 MEM_FP_READ( RM(ir), FRNn(ir) );
1359 RM(ir) += FP_WIDTH;
1360 break;
1361 case 10:/* FMOV.S FRm, [Rn] */
1362 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1363 break;
1364 case 11:/* FMOV.S FRm, [--Rn] */
1365 RN(ir) -= FP_WIDTH;
1366 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1367 break;
1368 case 12:/* FMOV FRm, FRn */
1369 if( IS_FPU_DOUBLESIZE() )
1370 DRN(ir) = DRM(ir);
1371 else
1372 FRN(ir) = FRM(ir);
1373 break;
1374 case 13:
1375 switch( (ir&0x00F0) >> 4 ) {
1376 case 0: /* FSTS FPUL, FRn */
1377 FRN(ir) = FPULf;
1378 break;
1379 case 1: /* FLDS FRn,FPUL */
1380 FPULf = FRN(ir);
1381 break;
1382 case 2: /* FLOAT FPUL, FRn */
1383 DRN(ir) = (float)FPULi;
1384 break;
1385 case 3: /* FTRC FRn, FPUL */
1386 dtmp = DRN(ir);
1387 if( dtmp >= MAX_INTF )
1388 FPULi = MAX_INT;
1389 else if( dtmp <= MIN_INTF )
1390 FPULi = MIN_INT;
1391 else
1392 FPULi = (int32_t)dtmp;
1393 break;
1394 case 4: /* FNEG FRn */
1395 DRN(ir) = -DRN(ir);
1396 break;
1397 case 5: /* FABS FRn */
1398 DRN(ir) = fabs(DRN(ir));
1399 break;
1400 case 6: /* FSQRT FRn */
1401 DRN(ir) = sqrt(DRN(ir));
1402 break;
1403 case 7: /* FSRRA FRn */
1404 /* NO-OP when PR=1 */
1405 break;
1406 case 8: /* FLDI0 FRn */
1407 DRN(ir) = 0.0;
1408 break;
1409 case 9: /* FLDI1 FRn */
1410 DRN(ir) = 1.0;
1411 break;
1412 case 10: /* FCNVSD FPUL, DRn */
1413 if( ! IS_FPU_DOUBLESIZE() )
1414 DRN(ir) = (double)FPULf;
1415 break;
1416 case 11: /* FCNVDS DRn, FPUL */
1417 if( ! IS_FPU_DOUBLESIZE() )
1418 FPULf = (float)DRN(ir);
1419 break;
1420 case 14:/* FIPR FVm, FVn */
1421 /* NO-OP when PR=1 */
1422 break;
1423 case 15:
1424 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1425 /* NO-OP when PR=1 */
1426 break;
1427 }
1428 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1429 /* NO-OP when PR=1 */
1430 break;
1431 }
1432 else if( ir == 0xFBFD ) {
1433 /* FRCHG */
1434 sh4r.fpscr ^= FPSCR_FR;
1435 break;
1436 }
1437 else if( ir == 0xF3FD ) {
1438 /* FSCHG */
1439 sh4r.fpscr ^= FPSCR_SZ;
1440 break;
1441 }
1442 default: UNDEF(ir);
1443 }
1444 break;
1445 case 14:/* FMAC FR0, FRm, FRn */
1446 DRN(ir) += DRM(ir)*DR0;
1447 break;
1448 default: UNDEF(ir);
1449 }
1450 } else { /* Single precision */
1451 switch( ir&0x000F ) {
1452 case 0: /* FADD FRm, FRn */
1453 FRN(ir) += FRM(ir);
1454 break;
1455 case 1: /* FSUB FRm, FRn */
1456 FRN(ir) -= FRM(ir);
1457 break;
1458 case 2: /* FMUL FRm, FRn */
1459 FRN(ir) = FRN(ir) * FRM(ir);
1460 break;
1461 case 3: /* FDIV FRm, FRn */
1462 FRN(ir) = FRN(ir) / FRM(ir);
1463 break;
1464 case 4: /* FCMP/EQ FRm, FRn */
1465 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1466 break;
1467 case 5: /* FCMP/GT FRm, FRn */
1468 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1469 break;
1470 case 6: /* FMOV.S [Rm+R0], FRn */
1471 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1472 break;
1473 case 7: /* FMOV.S FRm, [Rn+R0] */
1474 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1475 break;
1476 case 8: /* FMOV.S [Rm], FRn */
1477 MEM_FP_READ( RM(ir), FRNn(ir) );
1478 break;
1479 case 9: /* FMOV.S [Rm++], FRn */
1480 MEM_FP_READ( RM(ir), FRNn(ir) );
1481 RM(ir) += FP_WIDTH;
1482 break;
1483 case 10:/* FMOV.S FRm, [Rn] */
1484 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1485 break;
1486 case 11:/* FMOV.S FRm, [--Rn] */
1487 RN(ir) -= FP_WIDTH;
1488 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1489 break;
1490 case 12:/* FMOV FRm, FRn */
1491 if( IS_FPU_DOUBLESIZE() )
1492 DRN(ir) = DRM(ir);
1493 else
1494 FRN(ir) = FRM(ir);
1495 break;
1496 case 13:
1497 switch( (ir&0x00F0) >> 4 ) {
1498 case 0: /* FSTS FPUL, FRn */
1499 FRN(ir) = FPULf;
1500 break;
1501 case 1: /* FLDS FRn,FPUL */
1502 FPULf = FRN(ir);
1503 break;
1504 case 2: /* FLOAT FPUL, FRn */
1505 FRN(ir) = (float)FPULi;
1506 break;
1507 case 3: /* FTRC FRn, FPUL */
1508 ftmp = FRN(ir);
1509 if( ftmp >= MAX_INTF )
1510 FPULi = MAX_INT;
1511 else if( ftmp <= MIN_INTF )
1512 FPULi = MIN_INT;
1513 else
1514 FPULi = (int32_t)ftmp;
1515 break;
1516 case 4: /* FNEG FRn */
1517 FRN(ir) = -FRN(ir);
1518 break;
1519 case 5: /* FABS FRn */
1520 FRN(ir) = fabsf(FRN(ir));
1521 break;
1522 case 6: /* FSQRT FRn */
1523 FRN(ir) = sqrtf(FRN(ir));
1524 break;
1525 case 7: /* FSRRA FRn */
1526 FRN(ir) = 1.0/sqrtf(FRN(ir));
1527 break;
1528 case 8: /* FLDI0 FRn */
1529 FRN(ir) = 0.0;
1530 break;
1531 case 9: /* FLDI1 FRn */
1532 FRN(ir) = 1.0;
1533 break;
1534 case 10: /* FCNVSD FPUL, DRn */
1535 break;
1536 case 11: /* FCNVDS DRn, FPUL */
1537 break;
1538 case 14:/* FIPR FVm, FVn */
1539 /* FIXME: This is not going to be entirely accurate
1540 * as the SH4 instruction is less precise. Also
1541 * need to check for 0s and infinities.
1542 */
1543 {
1544 int tmp2 = FVN(ir);
1545 tmp = FVM(ir);
1546 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1547 FR(tmp+1)*FR(tmp2+1) +
1548 FR(tmp+2)*FR(tmp2+2) +
1549 FR(tmp+3)*FR(tmp2+3);
1550 break;
1551 }
1552 case 15:
1553 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1554 tmp = FVN(ir);
1555 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1556 FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] +
1557 XF(8)*fv[2] + XF(12)*fv[3];
1558 FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] +
1559 XF(9)*fv[2] + XF(13)*fv[3];
1560 FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] +
1561 XF(10)*fv[2] + XF(14)*fv[3];
1562 FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] +
1563 XF(11)*fv[2] + XF(15)*fv[3];
1564 break;
1565 }
1566 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1567 float angle = (((float)(short)(FPULi>>16)) +
1568 (((float)(FPULi&0xFFFF))/65536.0)) *
1569 2 * M_PI;
1570 int reg = FRNn(ir);
1571 FR(reg) = sinf(angle);
1572 FR(reg+1) = cosf(angle);
1573 break;
1574 }
1575 else if( ir == 0xFBFD ) {
1576 /* FRCHG */
1577 sh4r.fpscr ^= FPSCR_FR;
1578 break;
1579 }
1580 else if( ir == 0xF3FD ) {
1581 /* FSCHG */
1582 sh4r.fpscr ^= FPSCR_SZ;
1583 break;
1584 }
1585 default: UNDEF(ir);
1586 }
1587 break;
1588 case 14:/* FMAC FR0, FRm, FRn */
1589 FRN(ir) += FRM(ir)*FR0;
1590 break;
1591 default: UNDEF(ir);
1592 }
1593 }
1594 break;
1595 }
1596 sh4r.pc = sh4r.new_pc;
1597 sh4r.new_pc += 2;
1598 sh4r.in_delay_slot = 0;
1599 }
.