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lxdream.org :: lxdream/src/sh4/sh4core.h
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.h
changeset 53:f2981805b929
prev43:0cf3e339cc59
next54:d8b73031289c
author nkeynes
date Thu Dec 29 12:52:29 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Rewrite timer to be more accurate, also support cycle precision in the future
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     1 /**
     2  * $Id: sh4core.h,v 1.9 2005-12-29 12:52:29 nkeynes Exp $
     3  * 
     4  * This file defines the public functions exported by the SH4 core, except
     5  * for disassembly functions defined in sh4dasm.h
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #ifndef sh4core_H
    21 #define sh4core_H 1
    23 #include <glib/gtypes.h>
    24 #include <stdint.h>
    25 #include <stdio.h>
    27 #ifdef __cplusplus
    28 extern "C" {
    29 #if 0
    30 }
    31 #endif
    32 #endif
    35 /**
    36  * SH4 is running normally 
    37  */
    38 #define SH4_STATE_RUNNING 1
    39 /**
    40  * SH4 is not executing instructions but all peripheral modules are still
    41  * running
    42  */
    43 #define SH4_STATE_SLEEP 2
    44 /**
    45  * SH4 is not executing instructions, DMAC is halted, but all other peripheral
    46  * modules are still running
    47  */
    48 #define SH4_STATE_DEEP_SLEEP 3
    49 /**
    50  * SH4 is not executing instructions and all peripheral modules are also
    51  * stopped. As close as you can get to powered-off without actually being
    52  * off.
    53  */
    54 #define SH4_STATE_STANDBY 4
    57 struct sh4_registers {
    58     uint32_t r[16];
    59     uint32_t r_bank[8]; /* hidden banked registers */
    60     uint32_t sr, gbr, ssr, spc, sgr, dbr, vbr;
    61     uint32_t pr, pc, fpul, fpscr;
    62     uint64_t mac;
    63     uint32_t m, q, s, t; /* really boolean - 0 or 1 */
    64     float fr[2][16];
    66     int32_t store_queue[16]; /* technically 2 banks of 32 bytes */
    68     uint32_t new_pc; /* Not a real register, but used to handle delay slots */
    69     uint32_t icount; /* Also not a real register, instruction counter */
    70     uint32_t int_pending; /* flag set by the INTC = pending priority level */
    71     int in_delay_slot; /* flag to indicate the current instruction is in
    72                              * a delay slot (certain rules apply) */
    73     uint32_t slice_cycle; /* Current cycle within the timeslice */
    74     int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */
    75 };
    77 extern struct sh4_registers sh4r;
    79 /* Public functions */
    81 void sh4_init( void );
    82 void sh4_reset( void );
    83 void sh4_run( void );
    84 void sh4_runto( uint32_t pc, uint32_t count );
    85 void sh4_runfor( uint32_t count );
    86 int sh4_isrunning( void );
    87 void sh4_stop( void );
    88 void sh4_set_pc( int );
    89 gboolean sh4_execute_instruction( void );
    90 void sh4_raise_exception( int, int );
    91 void sh4_set_breakpoint( uint32_t pc, int type );
    92 gboolean sh4_clear_breakpoint( uint32_t pc, int type );
    93 int sh4_get_breakpoint( uint32_t pc );
    95 #define BREAK_ONESHOT 1
    96 #define BREAK_PERM 2
    98 /* SH4 Memory */
    99 int32_t sh4_read_long( uint32_t addr );
   100 int32_t sh4_read_word( uint32_t addr );
   101 int32_t sh4_read_byte( uint32_t addr );
   102 void sh4_write_long( uint32_t addr, uint32_t val );
   103 void sh4_write_word( uint32_t addr, uint32_t val );
   104 void sh4_write_byte( uint32_t addr, uint32_t val );
   105 int32_t sh4_read_phys_word( uint32_t addr );
   107 /* Peripheral functions */
   108 void DMAC_run_slice( uint32_t );
   109 void TMU_run_slice( uint32_t );
   110 void TMU_update_clocks( void );
   111 void TMU_reset( void );
   112 void TMU_save_state( FILE * );
   113 int TMU_load_state( FILE * );
   114 void SCIF_reset( void );
   115 void SCIF_run_slice( uint32_t );
   116 void SCIF_save_state( FILE *f );
   117 int SCIF_load_state( FILE *f );
   119 #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
   120 #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
   121 #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
   122 #define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
   123 #define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
   124 #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
   126 /* Status Register (SR) bits */
   127 #define SR_MD    0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ 
   128 #define SR_RB    0x20000000 /* Register bank (priviledged mode only) */
   129 #define SR_BL    0x10000000 /* Exception/interupt block (1 = masked) */
   130 #define SR_FD    0x00008000 /* FPU disable */
   131 #define SR_M     0x00000200
   132 #define SR_Q     0x00000100
   133 #define SR_IMASK 0x000000F0 /* Interrupt mask level */
   134 #define SR_S     0x00000002 /* Saturation operation for MAC instructions */
   135 #define SR_T     0x00000001 /* True/false or carry/borrow */
   136 #define SR_MASK  0x700083F3
   137 #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */
   139 #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD)
   140 #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4)
   141 #define SH4_INT_PENDING() (sh4r.int_pending && !sh4r.in_delay_slot)
   143 #define FPSCR_FR     0x00200000 /* FPU register bank */
   144 #define FPSCR_SZ     0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */
   145 #define FPSCR_PR     0x00080000 /* Precision (0=32 bites, 1=64 bits) */
   146 #define FPSCR_DN     0x00040000 /* Denormalization mode (1 = treat as 0) */
   147 #define FPSCR_CAUSE  0x0003F000
   148 #define FPSCR_ENABLE 0x00000F80
   149 #define FPSCR_FLAG   0x0000007C
   150 #define FPSCR_RM     0x00000003 /* Rounding mode (0=nearest, 1=to zero) */
   152 #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR)
   153 #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ)
   154 #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0)
   156 #define FR sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21]
   157 #define XF sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]
   159 /* Exceptions (for use with sh4_raise_exception) */
   161 #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100
   162 #define EX_SLOT_ILLEGAL        0x1A0, 0x100
   163 #define EX_TLB_MISS_READ       0x040, 0x400
   164 #define EX_TLB_MISS_WRITE      0x060, 0x400
   165 #define EX_INIT_PAGE_WRITE     0x080, 0x100
   166 #define EX_TLB_PROT_READ       0x0A0, 0x100
   167 #define EX_TLB_PROT_WRITE      0x0C0, 0x100
   168 #define EX_DATA_ADDR_READ      0x0E0, 0x100
   169 #define EX_DATA_ADDR_WRITE     0x100, 0x100
   170 #define EX_FPU_EXCEPTION       0x120, 0x100
   171 #define EX_TRAPA               0x160, 0x100
   172 #define EX_BREAKPOINT          0x1E0, 0x100
   173 #define EX_FPU_DISABLED        0x800, 0x100
   174 #define EX_SLOT_FPU_DISABLED   0x820, 0x100
   176 #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val;
   178 #ifdef __cplusplus
   179 }
   180 #endif
   181 #endif
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