9 void sh4_save( FILE *f );
10 void sh4_load( FILE *f );
12 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset,
16 struct sh4_registers sh4r;
17 static int running = 0;
21 register_io_regions( mmio_list_sh4mmio );
28 sh4r.new_pc= 0xA0000002;
29 sh4r.vbr = 0x00000000;
30 sh4r.fpscr = 0x00040001;
33 /* Everything else is undefined anyway, so don't bother setting it */
37 void sh4_set_pc( int pc )
48 void sh4_save( FILE *f )
50 fwrite( &sh4r, sizeof(sh4r), 1, f );
51 /* Save all additional on-board MMIO state */
54 void sh4_load( FILE * f )
63 sh4_execute_instruction();
67 void sh4_runfor(uint32_t count)
70 while( running && count--) {
72 sh4_execute_instruction();
74 if( sh4r.pc == 0x8C0C1636 ||
75 sh4r.pc == 0x8C0C1634 ) {
76 WARN( "Branching to %08X from %08X", sh4r.pc, pc );
82 int sh4_isrunning(void)
87 void sh4_runto( uint32_t target_pc, uint32_t count )
90 while( running && count--) {
91 sh4_execute_instruction();
92 if( sh4r.pc == target_pc ) {
99 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
100 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); return; }while(0)
102 #define RAISE( x, v ) do{ \
103 if( sh4r.vbr == 0 ) { \
104 ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
107 sh4r.spc = sh4r.pc + 2; \
108 sh4r.ssr = sh4_read_sr(); \
109 sh4r.sgr = sh4r.r[15]; \
110 MMIO_WRITE(MMU,EXPEVT,x); \
111 sh4r.pc = sh4r.vbr + v; \
112 sh4r.new_pc = sh4r.pc + 2; \
113 sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
117 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
118 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
119 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
120 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
121 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
122 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
124 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
125 ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
126 ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
127 } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
129 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
130 sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
131 sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
132 } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
134 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
136 #define EXC_POWER_RESET 0x000 /* vector special */
137 #define EXC_MANUAL_RESET 0x020
138 #define EXC_SLOT_ILLEGAL 0x1A0
139 #define EXC_ILLEGAL 0x180
140 #define EXV_ILLEGAL 0x100
141 #define EXC_TRAP 0x160
142 #define EXV_TRAP 0x100
143 #define EXC_FPDISABLE 0x800
144 #define EXV_FPDISABLE 0x100
146 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
147 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
148 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
149 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
150 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
152 static void sh4_switch_banks( )
156 memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
157 memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
158 memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
161 static void sh4_load_sr( uint32_t newval )
163 if( (newval ^ sh4r.sr) & SR_RB )
166 sh4r.t = (newval&SR_T) ? 1 : 0;
167 sh4r.s = (newval&SR_S) ? 1 : 0;
168 sh4r.m = (newval&SR_M) ? 1 : 0;
169 sh4r.q = (newval&SR_Q) ? 1 : 0;
173 static uint32_t sh4_read_sr( void )
175 /* synchronize sh4r.sr with the various bitflags */
176 sh4r.sr &= SR_MQSTMASK;
177 if( sh4r.t ) sh4r.sr |= SR_T;
178 if( sh4r.s ) sh4r.sr |= SR_S;
179 if( sh4r.m ) sh4r.sr |= SR_M;
180 if( sh4r.q ) sh4r.sr |= SR_Q;
183 /* function for external use */
184 void sh4_raise_exception( int code, int vector )
189 static void sh4_accept_interrupt( void )
191 uint32_t code = intc_accept_interrupt();
192 sh4r.ssr = sh4_read_sr();
194 sh4r.sgr = sh4r.r[15];
195 sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
196 MMIO_WRITE( MMU, INTEVT, code );
197 sh4r.pc = sh4r.vbr + 0x600;
198 sh4r.new_pc = sh4r.pc + 2;
199 WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
202 void sh4_execute_instruction( void )
211 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
212 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
213 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
214 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
215 #define DISP8(ir) (ir&0x00FF)
216 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
217 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
218 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
219 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
220 #define FVN(ir) ((ir&0x0C00)>>8)
221 #define FVM(ir) ((ir&0x0300)>>6)
222 #define FRN(ir) (FR[(ir&0x0F00)>>8])
223 #define FRM(ir) (FR[(ir&0x00F0)>>4])
224 #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
225 #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
226 #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
227 #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
228 #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
229 #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
230 #define FRNn(ir) ((ir&0x0F00)>>8)
231 #define FRMn(ir) ((ir&0x00F0)>>4)
232 #define FPULf *((float *)&sh4r.fpul)
233 #define FPULi (sh4r.fpul)
235 if( SH4_INT_PENDING() )
236 sh4_accept_interrupt();
239 ir = MEM_READ_WORD(pc);
242 switch( (ir&0xF000)>>12 ) {
243 case 0: /* 0000nnnnmmmmxxxx */
244 switch( ir&0x000F ) {
246 switch( (ir&0x00F0)>>4 ) {
247 case 0: /* STC SR, Rn */
249 RN(ir) = sh4_read_sr();
251 case 1: /* STC GBR, Rn */
254 case 2: /* STC VBR, Rn */
258 case 3: /* STC SSR, Rn */
262 case 4: /* STC SPC, Rn */
266 case 8: case 9: case 10: case 11: case 12: case 13:
267 case 14: case 15:/* STC Rm_bank, Rn */
269 RN(ir) = RN_BANK(ir);
275 switch( (ir&0x00F0)>>4 ) {
276 case 0: /* BSRF Rn */
277 CHECKDEST( pc + 4 + RN(ir) );
279 sh4r.in_delay_slot = 1;
280 sh4r.pr = sh4r.pc + 4;
281 sh4r.pc = sh4r.new_pc;
282 sh4r.new_pc = pc + 4 + RN(ir);
284 case 2: /* BRAF Rn */
285 CHECKDEST( pc + 4 + RN(ir) );
287 sh4r.in_delay_slot = 1;
288 sh4r.pc = sh4r.new_pc;
289 sh4r.new_pc = pc + 4 + RN(ir);
291 case 8: /* PREF [Rn] */
293 if( (tmp & 0xFC000000) == 0xE0000000 ) {
294 /* Store queue operation */
295 int queue = (tmp&0x20)>>2;
296 int32_t *src = &sh4r.store_queue[queue];
297 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
298 uint32_t target = tmp&0x03FFFFE0 | hi;
299 mem_copy_to_sh4( target, src, 32 );
300 WARN( "Executed SQ%c => %08X",
301 (queue == 0 ? '0' : '1'), target );
304 case 9: /* OCBI [Rn] */
305 case 10:/* OCBP [Rn] */
306 case 11:/* OCBWB [Rn] */
309 case 12:/* MOVCA.L R0, [Rn] */
314 case 4: /* MOV.B Rm, [R0 + Rn] */
315 MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
317 case 5: /* MOV.W Rm, [R0 + Rn] */
318 MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
320 case 6: /* MOV.L Rm, [R0 + Rn] */
321 MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
323 case 7: /* MUL.L Rm, Rn */
324 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
328 switch( (ir&0x0FF0)>>4 ) {
350 if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */
352 else if( ir == 0x0019 ) /* DIV0U */
353 sh4r.m = sh4r.q = sh4r.t = 0;
354 else if( ir == 0x0009 )
359 switch( (ir&0x00F0) >> 4 ) {
360 case 0: /* STS MACH, Rn */
361 RN(ir) = sh4r.mac >> 32;
363 case 1: /* STS MACL, Rn */
364 RN(ir) = (uint32_t)sh4r.mac;
366 case 2: /* STS PR, Rn */
369 case 3: /* STC SGR, Rn */
373 case 5:/* STS FPUL, Rn */
376 case 6: /* STS FPSCR, Rn */
379 case 15:/* STC DBR, Rn */
387 switch( (ir&0x0FF0)>>4 ) {
389 CHECKDEST( sh4r.pr );
391 sh4r.in_delay_slot = 1;
392 sh4r.pc = sh4r.new_pc;
393 sh4r.new_pc = sh4r.pr;
400 CHECKDEST( sh4r.spc );
402 sh4r.in_delay_slot = 1;
403 sh4r.pc = sh4r.new_pc;
404 sh4r.new_pc = sh4r.spc;
405 sh4_load_sr( sh4r.ssr );
406 WARN( "RTE => %08X", sh4r.new_pc );
411 case 12:/* MOV.B [R0+R%d], R%d */
412 RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
414 case 13:/* MOV.W [R0+R%d], R%d */
415 RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
417 case 14:/* MOV.L [R0+R%d], R%d */
418 RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
420 case 15:/* MAC.L [Rm++], [Rn++] */
421 tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
422 SIGNEXT32(MEM_READ_LONG(RN(ir))) );
424 /* 48-bit Saturation. Yuch */
425 tmpl += SIGNEXT48(sh4r.mac);
426 if( tmpl < 0xFFFF800000000000LL )
427 tmpl = 0xFFFF800000000000LL;
428 else if( tmpl > 0x00007FFFFFFFFFFFLL )
429 tmpl = 0x00007FFFFFFFFFFFLL;
430 sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
431 (tmpl&0x0000FFFFFFFFFFFFLL);
432 } else sh4r.mac = tmpl;
441 case 1: /* 0001nnnnmmmmdddd */
442 /* MOV.L Rm, [Rn + disp4*4] */
443 MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
445 case 2: /* 0010nnnnmmmmxxxx */
446 switch( ir&0x000F ) {
447 case 0: /* MOV.B Rm, [Rn] */
448 MEM_WRITE_BYTE( RN(ir), RM(ir) );
450 case 1: /* MOV.W Rm, [Rn] */
451 MEM_WRITE_WORD( RN(ir), RM(ir) );
453 case 2: /* MOV.L Rm, [Rn] */
454 MEM_WRITE_LONG( RN(ir), RM(ir) );
458 case 4: /* MOV.B Rm, [--Rn] */
460 MEM_WRITE_BYTE( RN(ir), RM(ir) );
462 case 5: /* MOV.W Rm, [--Rn] */
464 MEM_WRITE_WORD( RN(ir), RM(ir) );
466 case 6: /* MOV.L Rm, [--Rn] */
468 MEM_WRITE_LONG( RN(ir), RM(ir) );
470 case 7: /* DIV0S Rm, Rn */
473 sh4r.t = sh4r.q ^ sh4r.m;
475 case 8: /* TST Rm, Rn */
476 sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
478 case 9: /* AND Rm, Rn */
481 case 10:/* XOR Rm, Rn */
484 case 11:/* OR Rm, Rn */
487 case 12:/* CMP/STR Rm, Rn */
488 /* set T = 1 if any byte in RM & RN is the same */
489 tmp = RM(ir) ^ RN(ir);
490 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
491 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
493 case 13:/* XTRCT Rm, Rn */
494 RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
496 case 14:/* MULU.W Rm, Rn */
497 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
498 (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
500 case 15:/* MULS.W Rm, Rn */
501 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
502 (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
506 case 3: /* 0011nnnnmmmmxxxx */
507 switch( ir&0x000F ) {
508 case 0: /* CMP/EQ Rm, Rn */
509 sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
511 case 2: /* CMP/HS Rm, Rn */
512 sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
514 case 3: /* CMP/GE Rm, Rn */
515 sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
517 case 4: { /* DIV1 Rm, Rn */
518 /* This is just from the sh4p manual with some
519 * simplifications (someone want to check it's correct? :)
520 * Why they couldn't just provide a real DIV instruction...
521 * Please oh please let the translator batch these things
522 * up into a single DIV... */
523 uint32_t tmp0, tmp1, tmp2, dir;
525 dir = sh4r.q ^ sh4r.m;
526 sh4r.q = (RN(ir) >> 31);
528 RN(ir) = (RN(ir) << 1) | sh4r.t;
532 tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
535 tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
537 sh4r.q ^= sh4r.m ^ tmp1;
538 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
540 case 5: /* DMULU.L Rm, Rn */
541 sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
543 case 6: /* CMP/HI Rm, Rn */
544 sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
546 case 7: /* CMP/GT Rm, Rn */
547 sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
549 case 8: /* SUB Rm, Rn */
552 case 10:/* SUBC Rm, Rn */
554 RN(ir) = RN(ir) - RM(ir) - sh4r.t;
555 sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
557 case 11:/* SUBV Rm, Rn */
560 case 12:/* ADD Rm, Rn */
563 case 13:/* DMULS.L Rm, Rn */
564 sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
566 case 14:/* ADDC Rm, Rn */
568 RN(ir) += RM(ir) + sh4r.t;
569 sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
571 case 15:/* ADDV Rm, Rn */
577 case 4: /* 0100nnnnxxxxxxxx */
578 switch( ir&0x00FF ) {
579 case 0x00: /* SHLL Rn */
580 sh4r.t = RN(ir) >> 31;
583 case 0x01: /* SHLR Rn */
584 sh4r.t = RN(ir) & 0x00000001;
587 case 0x02: /* STS.L MACH, [--Rn] */
589 MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
591 case 0x03: /* STC.L SR, [--Rn] */
594 MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
596 case 0x04: /* ROTL Rn */
597 sh4r.t = RN(ir) >> 31;
601 case 0x05: /* ROTR Rn */
602 sh4r.t = RN(ir) & 0x00000001;
604 RN(ir) |= (sh4r.t << 31);
606 case 0x06: /* LDS.L [Rn++], MACH */
607 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
608 (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
611 case 0x07: /* LDC.L [Rn++], SR */
613 sh4_load_sr( MEM_READ_LONG(RN(ir)) );
616 case 0x08: /* SHLL2 Rn */
619 case 0x09: /* SHLR2 Rn */
622 case 0x0A: /* LDS Rn, MACH */
623 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
624 (((uint64_t)RN(ir))<<32);
626 case 0x0B: /* JSR [Rn] */
629 sh4r.in_delay_slot = 1;
630 sh4r.pc = sh4r.new_pc;
631 sh4r.new_pc = RN(ir);
634 case 0x0E: /* LDC Rn, SR */
636 sh4_load_sr( RN(ir) );
638 case 0x10: /* DT Rn */
640 sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
642 case 0x11: /* CMP/PZ Rn */
643 sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
645 case 0x12: /* STS.L MACL, [--Rn] */
647 MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
649 case 0x13: /* STC.L GBR, [--Rn] */
651 MEM_WRITE_LONG( RN(ir), sh4r.gbr );
653 case 0x15: /* CMP/PL Rn */
654 sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
656 case 0x16: /* LDS.L [Rn++], MACL */
657 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
658 (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
661 case 0x17: /* LDC.L [Rn++], GBR */
662 sh4r.gbr = MEM_READ_LONG(RN(ir));
665 case 0x18: /* SHLL8 Rn */
668 case 0x19: /* SHLR8 Rn */
671 case 0x1A: /* LDS Rn, MACL */
672 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
673 (uint64_t)((uint32_t)(RN(ir)));
675 case 0x1B: /* TAS.B [Rn] */
676 tmp = MEM_READ_BYTE( RN(ir) );
677 sh4r.t = ( tmp == 0 ? 1 : 0 );
678 MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
680 case 0x1E: /* LDC Rn, GBR */
683 case 0x20: /* SHAL Rn */
684 sh4r.t = RN(ir) >> 31;
687 case 0x21: /* SHAR Rn */
688 sh4r.t = RN(ir) & 0x00000001;
689 RN(ir) = ((int32_t)RN(ir)) >> 1;
691 case 0x22: /* STS.L PR, [--Rn] */
693 MEM_WRITE_LONG( RN(ir), sh4r.pr );
695 case 0x23: /* STC.L VBR, [--Rn] */
698 MEM_WRITE_LONG( RN(ir), sh4r.vbr );
700 case 0x24: /* ROTCL Rn */
706 case 0x25: /* ROTCR Rn */
707 tmp = RN(ir) & 0x00000001;
709 RN(ir) |= (sh4r.t << 31 );
712 case 0x26: /* LDS.L [Rn++], PR */
713 sh4r.pr = MEM_READ_LONG( RN(ir) );
716 case 0x27: /* LDC.L [Rn++], VBR */
718 sh4r.vbr = MEM_READ_LONG(RN(ir));
721 case 0x28: /* SHLL16 Rn */
724 case 0x29: /* SHLR16 Rn */
727 case 0x2A: /* LDS Rn, PR */
730 case 0x2B: /* JMP [Rn] */
733 sh4r.in_delay_slot = 1;
734 sh4r.pc = sh4r.new_pc;
735 sh4r.new_pc = RN(ir);
737 case 0x2E: /* LDC Rn, VBR */
741 case 0x32: /* STC.L SGR, [--Rn] */
744 MEM_WRITE_LONG( RN(ir), sh4r.sgr );
746 case 0x33: /* STC.L SSR, [--Rn] */
749 MEM_WRITE_LONG( RN(ir), sh4r.ssr );
751 case 0x37: /* LDC.L [Rn++], SSR */
753 sh4r.ssr = MEM_READ_LONG(RN(ir));
756 case 0x3E: /* LDC Rn, SSR */
760 case 0x43: /* STC.L SPC, [--Rn] */
763 MEM_WRITE_LONG( RN(ir), sh4r.spc );
765 case 0x47: /* LDC.L [Rn++], SPC */
767 sh4r.spc = MEM_READ_LONG(RN(ir));
770 case 0x4E: /* LDC Rn, SPC */
774 case 0x52: /* STS.L FPUL, [--Rn] */
776 MEM_WRITE_LONG( RN(ir), sh4r.fpul );
778 case 0x56: /* LDS.L [Rn++], FPUL */
779 sh4r.fpul = MEM_READ_LONG(RN(ir));
782 case 0x5A: /* LDS Rn, FPUL */
785 case 0x62: /* STS.L FPSCR, [--Rn] */
787 MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
789 case 0x66: /* LDS.L [Rn++], FPSCR */
790 sh4r.fpscr = MEM_READ_LONG(RN(ir));
793 case 0x6A: /* LDS Rn, FPSCR */
796 case 0xF2: /* STC.L DBR, [--Rn] */
799 MEM_WRITE_LONG( RN(ir), sh4r.dbr );
801 case 0xF6: /* LDC.L [Rn++], DBR */
803 sh4r.dbr = MEM_READ_LONG(RN(ir));
806 case 0xFA: /* LDC Rn, DBR */
810 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
811 case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */
814 MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
816 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
817 case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */
819 RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
822 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
823 case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */
825 RN_BANK(ir) = RM(ir);
828 if( (ir&0x000F) == 0x0F ) {
829 /* MAC.W [Rm++], [Rn++] */
830 tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
831 SIGNEXT16(MEM_READ_WORD(RN(ir)));
835 } else sh4r.mac += SIGNEXT32(tmp);
838 } else if( (ir&0x000F) == 0x0C ) {
841 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
842 else if( (tmp & 0x1F) == 0 )
843 RN(ir) = ((int32_t)RN(ir)) >> 31;
845 RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
846 } else if( (ir&0x000F) == 0x0D ) {
849 if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
850 else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
851 else RN(ir) >>= (((~tmp) & 0x1F)+1);
855 case 5: /* 0101nnnnmmmmdddd */
856 /* MOV.L [Rm + disp4*4], Rn */
857 RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
859 case 6: /* 0110xxxxxxxxxxxx */
860 switch( ir&0x000f ) {
861 case 0: /* MOV.B [Rm], Rn */
862 RN(ir) = MEM_READ_BYTE( RM(ir) );
864 case 1: /* MOV.W [Rm], Rn */
865 RN(ir) = MEM_READ_WORD( RM(ir) );
867 case 2: /* MOV.L [Rm], Rn */
868 RN(ir) = MEM_READ_LONG( RM(ir) );
870 case 3: /* MOV Rm, Rn */
873 case 4: /* MOV.B [Rm++], Rn */
874 RN(ir) = MEM_READ_BYTE( RM(ir) );
877 case 5: /* MOV.W [Rm++], Rn */
878 RN(ir) = MEM_READ_WORD( RM(ir) );
881 case 6: /* MOV.L [Rm++], Rn */
882 RN(ir) = MEM_READ_LONG( RM(ir) );
885 case 7: /* NOT Rm, Rn */
888 case 8: /* SWAP.B Rm, Rn */
889 RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
890 ((RM(ir)&0x000000FF)<<8);
892 case 9: /* SWAP.W Rm, Rn */
893 RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
895 case 10:/* NEGC Rm, Rn */
897 RN(ir) = tmp - sh4r.t;
898 sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
900 case 11:/* NEG Rm, Rn */
903 case 12:/* EXTU.B Rm, Rn */
904 RN(ir) = RM(ir)&0x000000FF;
906 case 13:/* EXTU.W Rm, Rn */
907 RN(ir) = RM(ir)&0x0000FFFF;
909 case 14:/* EXTS.B Rm, Rn */
910 RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
912 case 15:/* EXTS.W Rm, Rn */
913 RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
917 case 7: /* 0111nnnniiiiiiii */
921 case 8: /* 1000xxxxxxxxxxxx */
922 switch( (ir&0x0F00) >> 8 ) {
923 case 0: /* MOV.B R0, [Rm + disp4] */
924 MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
926 case 1: /* MOV.W R0, [Rm + disp4*2] */
927 MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
929 case 4: /* MOV.B [Rm + disp4], R0 */
930 R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
932 case 5: /* MOV.W [Rm + disp4*2], R0 */
933 R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
935 case 8: /* CMP/EQ imm, R0 */
936 sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
938 case 9: /* BT disp8 */
941 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
942 sh4r.pc += (PCDISP8(ir)<<1) + 4;
943 sh4r.new_pc = sh4r.pc + 2;
947 case 11:/* BF disp8 */
950 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
951 sh4r.pc += (PCDISP8(ir)<<1) + 4;
952 sh4r.new_pc = sh4r.pc + 2;
956 case 13:/* BT/S disp8 */
959 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
960 sh4r.in_delay_slot = 1;
961 sh4r.pc = sh4r.new_pc;
962 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
963 sh4r.in_delay_slot = 1;
967 case 15:/* BF/S disp8 */
970 CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
971 sh4r.in_delay_slot = 1;
972 sh4r.pc = sh4r.new_pc;
973 sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
980 case 9: /* 1001xxxxxxxxxxxx */
981 /* MOV.W [disp8*2 + pc + 4], Rn */
982 RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
984 case 10:/* 1010dddddddddddd */
986 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
988 sh4r.in_delay_slot = 1;
989 sh4r.pc = sh4r.new_pc;
990 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
992 case 11:/* 1011dddddddddddd */
994 CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
996 sh4r.in_delay_slot = 1;
998 sh4r.pc = sh4r.new_pc;
999 sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
1001 case 12:/* 1100xxxxdddddddd */
1002 switch( (ir&0x0F00)>>8 ) {
1003 case 0: /* MOV.B R0, [GBR + disp8] */
1004 MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
1006 case 1: /* MOV.W R0, [GBR + disp8*2] */
1007 MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
1009 case 2: /*MOV.L R0, [GBR + disp8*4] */
1010 MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
1012 case 3: /* TRAPA imm8 */
1014 sh4r.in_delay_slot = 1;
1015 MMIO_WRITE( MMU, TRA, UIMM8(ir) );
1016 sh4r.pc = sh4r.new_pc; /* RAISE ends the instruction */
1018 RAISE( EXC_TRAP, EXV_TRAP );
1020 case 4: /* MOV.B [GBR + disp8], R0 */
1021 R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
1023 case 5: /* MOV.W [GBR + disp8*2], R0 */
1024 R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
1026 case 6: /* MOV.L [GBR + disp8*4], R0 */
1027 R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
1029 case 7: /* MOVA disp8 + pc&~3 + 4, R0 */
1030 R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
1032 case 8: /* TST imm8, R0 */
1033 sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
1035 case 9: /* AND imm8, R0 */
1038 case 10:/* XOR imm8, R0 */
1041 case 11:/* OR imm8, R0 */
1044 case 12:/* TST.B imm8, [R0+GBR] */
1045 sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
1047 case 13:/* AND.B imm8, [R0+GBR] */
1048 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1049 UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
1051 case 14:/* XOR.B imm8, [R0+GBR] */
1052 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1053 UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
1055 case 15:/* OR.B imm8, [R0+GBR] */
1056 MEM_WRITE_BYTE( R0 + sh4r.gbr,
1057 UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
1061 case 13:/* 1101nnnndddddddd */
1062 /* MOV.L [disp8*4 + pc&~3 + 4], Rn */
1063 RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
1065 case 14:/* 1110nnnniiiiiiii */
1069 case 15:/* 1111xxxxxxxxxxxx */
1071 switch( ir&0x000F ) {
1072 case 0: /* FADD FRm, FRn */
1075 case 1: /* FSUB FRm, FRn */
1078 case 2: /* FMUL FRm, FRn */
1079 FRN(ir) = FRN(ir) * FRM(ir);
1081 case 3: /* FDIV FRm, FRn */
1082 FRN(ir) = FRN(ir) / FRM(ir);
1084 case 4: /* FCMP/EQ FRm, FRn */
1085 sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
1087 case 5: /* FCMP/GT FRm, FRn */
1088 sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
1090 case 6: /* FMOV.S [Rm+R0], FRn */
1091 MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
1093 case 7: /* FMOV.S FRm, [Rn+R0] */
1094 MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
1096 case 8: /* FMOV.S [Rm], FRn */
1097 MEM_FP_READ( RM(ir), FRNn(ir) );
1099 case 9: /* FMOV.S [Rm++], FRn */
1100 MEM_FP_READ( RM(ir), FRNn(ir) );
1103 case 10:/* FMOV.S FRm, [Rn] */
1104 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1106 case 11:/* FMOV.S FRm, [--Rn] */
1108 MEM_FP_WRITE( RN(ir), FRMn(ir) );
1110 case 12:/* FMOV FRm, FRn */
1111 if( IS_FPU_DOUBLESIZE() ) {
1118 switch( (ir&0x00F0) >> 4 ) {
1119 case 0: /* FSTS FPUL, FRn */
1122 case 1: /* FLDS FRn, FPUL */
1125 case 2: /* FLOAT FPUL, FRn */
1126 FRN(ir) = (float)FPULi;
1128 case 3: /* FTRC FRn, FPUL */
1129 FPULi = (uint32_t)FRN(ir);
1130 /* FIXME: is this sufficient? */
1132 case 4: /* FNEG FRn */
1135 case 5: /* FABS FRn */
1136 FRN(ir) = fabsf(FRN(ir));
1138 case 6: /* FSQRT FRn */
1139 FRN(ir) = sqrtf(FRN(ir));
1141 case 7: /* FSRRA FRn */
1142 FRN(ir) = 1.0/sqrtf(FRN(ir));
1144 case 8: /* FLDI0 FRn */
1147 case 9: /* FLDI1 FRn */
1150 case 10: /* FCNVSD FPUL, DRn */
1151 if( IS_FPU_DOUBLEPREC() )
1152 DRN(ir) = (double)FPULf;
1155 case 11: /* FCNVDS DRn, FPUL */
1156 if( IS_FPU_DOUBLEPREC() )
1157 FPULf = (float)DRN(ir);
1160 case 14:/* FIPR FVm, FVn */
1161 /* FIXME: This is not going to be entirely accurate
1162 * as the SH4 instruction is less precise. Also
1163 * need to check for 0s and infinities.
1166 float *fr_bank = FR;
1169 fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
1170 fr_bank[tmp+1]*fr_bank[tmp2+1] +
1171 fr_bank[tmp+2]*fr_bank[tmp2+2] +
1172 fr_bank[tmp+3]*fr_bank[tmp2+3];
1176 if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */
1177 float *fvout = FR+FVN(ir);
1179 float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
1180 fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
1181 xm[8]*fv[2] + xm[12]*fv[3];
1182 fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
1183 xm[9]*fv[2] + xm[13]*fv[3];
1184 fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
1185 xm[10]*fv[2] + xm[14]*fv[3];
1186 fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
1187 xm[11]*fv[2] + xm[15]*fv[3];
1190 else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */
1191 float angle = (((float)(short)(FPULi>>16)) +
1192 ((float)(FPULi&16)/65536.0)) *
1195 FR[reg] = sinf(angle);
1196 FR[reg+1] = cosf(angle);
1199 else if( ir == 0xFBFD ) {
1201 sh4r.fpscr ^= FPSCR_FR;
1204 else if( ir == 0xF3FD ) {
1206 sh4r.fpscr ^= FPSCR_SZ;
1212 case 14:/* FMAC FR0, FRm, FRn */
1213 FRN(ir) += FRM(ir)*FR0;
1219 sh4r.pc = sh4r.new_pc;
1221 sh4r.in_delay_slot = 0;
.