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lxdream.org :: lxdream/src/sh4/sh4core.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4core.c
changeset 16:f383e7640da4
prev15:5194dd0fdb60
next18:9a1b5d75703f
author nkeynes
date Tue Dec 13 12:17:26 2005 +0000 (14 years ago)
permissions -rw-r--r--
last change Cleanup init config => dreamcast_config
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     1 #include <math.h>
     2 #include "dream.h"
     3 #include "modules.h"
     4 #include "sh4core.h"
     5 #include "sh4mmio.h"
     6 #include "mem.h"
     7 #include "intc.h"
     9 void sh4_save( FILE *f );
    10 void sh4_load( FILE *f );
    12 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    13 				       NULL, sh4_stop,
    14 				       sh4_save, sh4_load };
    16 struct sh4_registers sh4r;
    17 static int running = 0;
    19 void sh4_init(void)
    20 {
    21     register_io_regions( mmio_list_sh4mmio );
    22     mmu_init();
    23 }
    25 void sh4_reset(void)
    26 {
    27     sh4r.pc    = 0xA0000000;
    28     sh4r.new_pc= 0xA0000002;
    29     sh4r.vbr   = 0x00000000;
    30     sh4r.fpscr = 0x00040001;
    31     sh4r.sr    = 0x700000F0;
    32     sh4r.icount= 0;
    33     /* Everything else is undefined anyway, so don't bother setting it */
    34     intc_reset();
    35 }
    37 void sh4_set_pc( int pc )
    38 {
    39     sh4r.pc = pc;
    40     sh4r.new_pc = pc+2;
    41 }
    43 void sh4_stop(void)
    44 {
    45     running = 0;
    46 }
    48 void sh4_save( FILE *f )
    49 {
    50     fwrite( &sh4r, sizeof(sh4r), 1, f );
    51     /* Save all additional on-board MMIO state */
    52 }
    54 void sh4_load( FILE * f )
    55 {
    57 }
    59 void sh4_run(void)
    60 {
    61     running = 1;
    62     while( running ) {
    63         sh4_execute_instruction();
    64     }
    65 }
    67 void sh4_runfor(uint32_t count)
    68 {
    69     running = 1;
    70     while( running && count--) {
    71         int pc = sh4r.pc;
    72         sh4_execute_instruction();
    73         /*
    74         if( sh4r.pc == 0x8C0C1636 ||
    75             sh4r.pc == 0x8C0C1634 ) {
    76             WARN( "Branching to %08X from %08X", sh4r.pc, pc );
    77             sh4_stop();
    78             }*/
    79     }
    80 }
    82 int sh4_isrunning(void)
    83 {
    84     return running;
    85 }
    87 void sh4_runto( uint32_t target_pc, uint32_t count )
    88 {
    89     running = 1;
    90     while( running && count--) {
    91         sh4_execute_instruction();
    92         if( sh4r.pc == target_pc ) {
    93             running = 0;
    94             break;
    95         }
    96     }
    97 }
    99 #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0)
   100 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); sh4_stop(); return; }while(0)
   102 #define RAISE( x, v ) do{ \
   103     if( sh4r.vbr == 0 ) { \
   104         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   105         sh4_stop(); \
   106     } else { \
   107         sh4r.spc = sh4r.pc + 2; \
   108         sh4r.ssr = sh4_read_sr(); \
   109         sh4r.sgr = sh4r.r[15]; \
   110         MMIO_WRITE(MMU,EXPEVT,x); \
   111         sh4r.pc = sh4r.vbr + v; \
   112         sh4r.new_pc = sh4r.pc + 2; \
   113         sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   114     } \
   115     return; } while(0)
   117 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
   118 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
   119 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
   120 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
   121 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
   122 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
   124 #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   125     ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \
   126     ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \
   127 } else ((uint32_t *)FR)[reg] = sh4_read_long(addr)
   129 #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \
   130     sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \
   131     sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \
   132 } else sh4_write_long( addr, ((uint32_t *)FR)[reg] )
   134 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
   136 #define EXC_POWER_RESET  0x000 /* vector special */
   137 #define EXC_MANUAL_RESET 0x020
   138 #define EXC_SLOT_ILLEGAL 0x1A0
   139 #define EXC_ILLEGAL      0x180
   140 #define EXV_ILLEGAL      0x100
   141 #define EXC_TRAP         0x160
   142 #define EXV_TRAP         0x100
   143 #define EXC_FPDISABLE    0x800
   144 #define EXV_FPDISABLE    0x100
   146 #define CHECK( x, c, v ) if( !x ) RAISE( c, v )
   147 #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL )
   148 #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE )
   149 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; }
   150 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); }
   152 static void sh4_switch_banks( )
   153 {
   154     uint32_t tmp[8];
   156     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   157     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   158     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   159 }
   161 static void sh4_load_sr( uint32_t newval )
   162 {
   163     if( (newval ^ sh4r.sr) & SR_RB )
   164         sh4_switch_banks();
   165     sh4r.sr = newval;
   166     sh4r.t = (newval&SR_T) ? 1 : 0;
   167     sh4r.s = (newval&SR_S) ? 1 : 0;
   168     sh4r.m = (newval&SR_M) ? 1 : 0;
   169     sh4r.q = (newval&SR_Q) ? 1 : 0;
   170     intc_mask_changed();
   171 }
   173 static uint32_t sh4_read_sr( void )
   174 {
   175     /* synchronize sh4r.sr with the various bitflags */
   176     sh4r.sr &= SR_MQSTMASK;
   177     if( sh4r.t ) sh4r.sr |= SR_T;
   178     if( sh4r.s ) sh4r.sr |= SR_S;
   179     if( sh4r.m ) sh4r.sr |= SR_M;
   180     if( sh4r.q ) sh4r.sr |= SR_Q;
   181     return sh4r.sr;
   182 }
   183 /* function for external use */
   184 void sh4_raise_exception( int code, int vector )
   185 {
   186     RAISE(code, vector);
   187 }
   189 static void sh4_accept_interrupt( void )
   190 {
   191     uint32_t code = intc_accept_interrupt();
   192     sh4r.ssr = sh4_read_sr();
   193     sh4r.spc = sh4r.pc;
   194     sh4r.sgr = sh4r.r[15];
   195     sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   196     MMIO_WRITE( MMU, INTEVT, code );
   197     sh4r.pc = sh4r.vbr + 0x600;
   198     sh4r.new_pc = sh4r.pc + 2;
   199     WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   200 }
   202 void sh4_execute_instruction( void )
   203 {
   204     int pc;
   205     unsigned short ir;
   206     uint32_t tmp;
   207     uint64_t tmpl;
   209 #define R0 sh4r.r[0]
   210 #define FR0 (FR[0])
   211 #define RN(ir) sh4r.r[(ir&0x0F00)>>8]
   212 #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4]
   213 #define RM(ir) sh4r.r[(ir&0x00F0)>>4]
   214 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */
   215 #define DISP8(ir) (ir&0x00FF)
   216 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
   217 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
   218 #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */
   219 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
   220 #define FVN(ir) ((ir&0x0C00)>>8)
   221 #define FVM(ir) ((ir&0x0300)>>6)
   222 #define FRN(ir) (FR[(ir&0x0F00)>>8])
   223 #define FRM(ir) (FR[(ir&0x00F0)>>4])
   224 #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8])
   225 #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4])
   226 #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9])
   227 #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5])
   228 #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9])
   229 #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5])
   230 #define FRNn(ir) ((ir&0x0F00)>>8)
   231 #define FRMn(ir) ((ir&0x00F0)>>4)
   232 #define FPULf   *((float *)&sh4r.fpul)
   233 #define FPULi    (sh4r.fpul)
   235     if( SH4_INT_PENDING() ) 
   236         sh4_accept_interrupt();
   238     pc = sh4r.pc;
   239     ir = MEM_READ_WORD(pc);
   240     sh4r.icount++;
   242     switch( (ir&0xF000)>>12 ) {
   243         case 0: /* 0000nnnnmmmmxxxx */
   244             switch( ir&0x000F ) {
   245                 case 2:
   246                     switch( (ir&0x00F0)>>4 ) {
   247                         case 0: /* STC     SR, Rn */
   248                             CHECKPRIV();
   249                             RN(ir) = sh4_read_sr();
   250                             break;
   251                         case 1: /* STC     GBR, Rn */
   252                             RN(ir) = sh4r.gbr;
   253                             break;
   254                         case 2: /* STC     VBR, Rn */
   255                             CHECKPRIV();
   256                             RN(ir) = sh4r.vbr;
   257                             break;
   258                         case 3: /* STC     SSR, Rn */
   259                             CHECKPRIV();
   260                             RN(ir) = sh4r.ssr;
   261                             break;
   262                         case 4: /* STC     SPC, Rn */
   263                             CHECKPRIV();
   264                             RN(ir) = sh4r.spc;
   265                             break;
   266                         case 8: case 9: case 10: case 11: case 12: case 13:
   267                         case 14: case 15:/* STC     Rm_bank, Rn */
   268                             CHECKPRIV();
   269                             RN(ir) = RN_BANK(ir);
   270                             break;
   271                         default: UNDEF(ir);
   272                     }
   273                     break;
   274                 case 3:
   275                     switch( (ir&0x00F0)>>4 ) {
   276                         case 0: /* BSRF    Rn */
   277                             CHECKDEST( pc + 4 + RN(ir) );
   278                             CHECKSLOTILLEGAL();
   279                             sh4r.in_delay_slot = 1;
   280                             sh4r.pr = sh4r.pc + 4;
   281                             sh4r.pc = sh4r.new_pc;
   282                             sh4r.new_pc = pc + 4 + RN(ir);
   283                             return;
   284                         case 2: /* BRAF    Rn */
   285                             CHECKDEST( pc + 4 + RN(ir) );
   286                             CHECKSLOTILLEGAL();
   287                             sh4r.in_delay_slot = 1;
   288                             sh4r.pc = sh4r.new_pc;
   289                             sh4r.new_pc = pc + 4 + RN(ir);
   290                             return;
   291                         case 8: /* PREF    [Rn] */
   292                             tmp = RN(ir);
   293                             if( (tmp & 0xFC000000) == 0xE0000000 ) {
   294                                 /* Store queue operation */
   295                                 int queue = (tmp&0x20)>>2;
   296                                 int32_t *src = &sh4r.store_queue[queue];
   297                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
   298                                 uint32_t target = tmp&0x03FFFFE0 | hi;
   299                                 mem_copy_to_sh4( target, src, 32 );
   300                                 WARN( "Executed SQ%c => %08X",
   301                                       (queue == 0 ? '0' : '1'), target );
   302                             }
   303                             break;
   304                         case 9: /* OCBI    [Rn] */
   305                         case 10:/* OCBP    [Rn] */
   306                         case 11:/* OCBWB   [Rn] */
   307                             /* anything? */
   308                             break;
   309                         case 12:/* MOVCA.L R0, [Rn] */
   310                             UNIMP(ir);
   311                         default: UNDEF(ir);
   312                     }
   313                     break;
   314                 case 4: /* MOV.B   Rm, [R0 + Rn] */
   315                     MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) );
   316                     break;
   317                 case 5: /* MOV.W   Rm, [R0 + Rn] */
   318                     MEM_WRITE_WORD( R0 + RN(ir), RM(ir) );
   319                     break;
   320                 case 6: /* MOV.L   Rm, [R0 + Rn] */
   321                     MEM_WRITE_LONG( R0 + RN(ir), RM(ir) );
   322                     break;
   323                 case 7: /* MUL.L   Rm, Rn */
   324                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   325                         (RM(ir) * RN(ir));
   326                     break;
   327                 case 8: 
   328                     switch( (ir&0x0FF0)>>4 ) {
   329                         case 0: /* CLRT    */
   330                             sh4r.t = 0;
   331                             break;
   332                         case 1: /* SETT    */
   333                             sh4r.t = 1;
   334                             break;
   335                         case 2: /* CLRMAC  */
   336                             sh4r.mac = 0;
   337                             break;
   338                         case 3: /* LDTLB   */
   339                             break;
   340                         case 4: /* CLRS    */
   341                             sh4r.s = 0;
   342                             break;
   343                         case 5: /* SETS    */
   344                             sh4r.s = 1;
   345                             break;
   346                         default: UNDEF(ir);
   347                     }
   348                     break;
   349                 case 9: 
   350                     if( (ir&0x00F0) == 0x20 ) /* MOVT    Rn */
   351                         RN(ir) = sh4r.t;
   352                     else if( ir == 0x0019 ) /* DIV0U   */
   353                         sh4r.m = sh4r.q = sh4r.t = 0;
   354                     else if( ir == 0x0009 )
   355                         /* NOP     */;
   356                     else UNDEF(ir);
   357                     break;
   358                 case 10:
   359                     switch( (ir&0x00F0) >> 4 ) {
   360                         case 0: /* STS     MACH, Rn */
   361                             RN(ir) = sh4r.mac >> 32;
   362                             break;
   363                         case 1: /* STS     MACL, Rn */
   364                             RN(ir) = (uint32_t)sh4r.mac;
   365                             break;
   366                         case 2: /* STS     PR, Rn */
   367                             RN(ir) = sh4r.pr;
   368                             break;
   369                         case 3: /* STC     SGR, Rn */
   370                             CHECKPRIV();
   371                             RN(ir) = sh4r.sgr;
   372                             break;
   373                         case 5:/* STS      FPUL, Rn */
   374                             RN(ir) = sh4r.fpul;
   375                             break;
   376                         case 6: /* STS     FPSCR, Rn */
   377                             RN(ir) = sh4r.fpscr;
   378                             break;
   379                         case 15:/* STC     DBR, Rn */
   380                             CHECKPRIV();
   381                             RN(ir) = sh4r.dbr;
   382                             break;
   383                         default: UNDEF(ir);
   384                     }
   385                     break;
   386                 case 11:
   387                     switch( (ir&0x0FF0)>>4 ) {
   388                         case 0: /* RTS     */
   389                             CHECKDEST( sh4r.pr );
   390                             CHECKSLOTILLEGAL();
   391                             sh4r.in_delay_slot = 1;
   392                             sh4r.pc = sh4r.new_pc;
   393                             sh4r.new_pc = sh4r.pr;
   394                             return;
   395                         case 1: /* SLEEP   */
   396                             running = 0;
   397                             break;
   398                         case 2: /* RTE     */
   399                             CHECKPRIV();
   400                             CHECKDEST( sh4r.spc );
   401                             CHECKSLOTILLEGAL();
   402                             sh4r.in_delay_slot = 1;
   403                             sh4r.pc = sh4r.new_pc;
   404                             sh4r.new_pc = sh4r.spc;
   405                             sh4_load_sr( sh4r.ssr );
   406                             WARN( "RTE => %08X", sh4r.new_pc );
   407                             return;
   408                         default:UNDEF(ir);
   409                     }
   410                     break;
   411                 case 12:/* MOV.B   [R0+R%d], R%d */
   412                     RN(ir) = MEM_READ_BYTE( R0 + RM(ir) );
   413                     break;
   414                 case 13:/* MOV.W   [R0+R%d], R%d */
   415                     RN(ir) = MEM_READ_WORD( R0 + RM(ir) );
   416                     break;
   417                 case 14:/* MOV.L   [R0+R%d], R%d */
   418                     RN(ir) = MEM_READ_LONG( R0 + RM(ir) );
   419                     break;
   420                 case 15:/* MAC.L   [Rm++], [Rn++] */
   421                     tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) *
   422                                   SIGNEXT32(MEM_READ_LONG(RN(ir))) );
   423                     if( sh4r.s ) {
   424                         /* 48-bit Saturation. Yuch */
   425                         tmpl += SIGNEXT48(sh4r.mac);
   426                         if( tmpl < 0xFFFF800000000000LL )
   427                             tmpl = 0xFFFF800000000000LL;
   428                         else if( tmpl > 0x00007FFFFFFFFFFFLL )
   429                             tmpl = 0x00007FFFFFFFFFFFLL;
   430                         sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) |
   431                             (tmpl&0x0000FFFFFFFFFFFFLL);
   432                     } else sh4r.mac = tmpl;
   434                     RM(ir) += 4;
   435                     RN(ir) += 4;
   437                     break;
   438                 default: UNDEF(ir);
   439             }
   440             break;
   441         case 1: /* 0001nnnnmmmmdddd */
   442             /* MOV.L   Rm, [Rn + disp4*4] */
   443             MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) );
   444             break;
   445         case 2: /* 0010nnnnmmmmxxxx */
   446             switch( ir&0x000F ) {
   447                 case 0: /* MOV.B   Rm, [Rn] */
   448                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   449                     break;
   450                 case 1: /* MOV.W   Rm, [Rn] */
   451                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   452                     break;
   453                 case 2: /* MOV.L   Rm, [Rn] */
   454                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   455                     break;
   456                 case 3: UNDEF(ir);
   457                     break;
   458                 case 4: /* MOV.B   Rm, [--Rn] */
   459                     RN(ir) --;
   460                     MEM_WRITE_BYTE( RN(ir), RM(ir) );
   461                     break;
   462                 case 5: /* MOV.W   Rm, [--Rn] */
   463                     RN(ir) -= 2;
   464                     MEM_WRITE_WORD( RN(ir), RM(ir) );
   465                     break;
   466                 case 6: /* MOV.L   Rm, [--Rn] */
   467                     RN(ir) -= 4;
   468                     MEM_WRITE_LONG( RN(ir), RM(ir) );
   469                     break;
   470                 case 7: /* DIV0S   Rm, Rn */
   471                     sh4r.q = RN(ir)>>31;
   472                     sh4r.m = RM(ir)>>31;
   473                     sh4r.t = sh4r.q ^ sh4r.m;
   474                     break;
   475                 case 8: /* TST     Rm, Rn */
   476                     sh4r.t = (RN(ir)&RM(ir) ? 0 : 1);
   477                     break;
   478                 case 9: /* AND     Rm, Rn */
   479                     RN(ir) &= RM(ir);
   480                     break;
   481                 case 10:/* XOR     Rm, Rn */
   482                     RN(ir) ^= RM(ir);
   483                     break;
   484                 case 11:/* OR      Rm, Rn */
   485                     RN(ir) |= RM(ir);
   486                     break;
   487                 case 12:/* CMP/STR Rm, Rn */
   488                     /* set T = 1 if any byte in RM & RN is the same */
   489                     tmp = RM(ir) ^ RN(ir);
   490                     sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
   491                               (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
   492                     break;
   493                 case 13:/* XTRCT   Rm, Rn */
   494                     RN(ir) = (RN(ir)>>16) | (RM(ir)<<16);
   495                     break;
   496                 case 14:/* MULU.W  Rm, Rn */
   497                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   498                         (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF));
   499                     break;
   500                 case 15:/* MULS.W  Rm, Rn */
   501                     sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
   502                         (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF));
   503                     break;
   504             }
   505             break;
   506         case 3: /* 0011nnnnmmmmxxxx */
   507             switch( ir&0x000F ) {
   508                 case 0: /* CMP/EQ  Rm, Rn */
   509                     sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 );
   510                     break;
   511                 case 2: /* CMP/HS  Rm, Rn */
   512                     sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 );
   513                     break;
   514                 case 3: /* CMP/GE  Rm, Rn */
   515                     sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 );
   516                     break;
   517                 case 4: { /* DIV1    Rm, Rn */
   518                     /* This is just from the sh4p manual with some
   519                      * simplifications (someone want to check it's correct? :)
   520                      * Why they couldn't just provide a real DIV instruction...
   521                      * Please oh please let the translator batch these things
   522                      * up into a single DIV... */
   523                     uint32_t tmp0, tmp1, tmp2, dir;
   525                     dir = sh4r.q ^ sh4r.m;
   526                     sh4r.q = (RN(ir) >> 31);
   527                     tmp2 = RM(ir);
   528                     RN(ir) = (RN(ir) << 1) | sh4r.t;
   529                     tmp0 = RN(ir);
   530                     if( dir ) {
   531                         RN(ir) += tmp2;
   532                         tmp1 = (RN(ir)<tmp0 ? 1 : 0 );
   533                     } else {
   534                         RN(ir) -= tmp2;
   535                         tmp1 = (RN(ir)>tmp0 ? 1 : 0 );
   536                     }
   537                     sh4r.q ^= sh4r.m ^ tmp1;
   538                     sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
   539                     break; }
   540                 case 5: /* DMULU.L Rm, Rn */
   541                     sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir));
   542                     break;
   543                 case 6: /* CMP/HI  Rm, Rn */
   544                     sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 );
   545                     break;
   546                 case 7: /* CMP/GT  Rm, Rn */
   547                     sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 );
   548                     break;
   549                 case 8: /* SUB     Rm, Rn */
   550                     RN(ir) -= RM(ir);
   551                     break;
   552                 case 10:/* SUBC    Rm, Rn */
   553                     tmp = RN(ir);
   554                     RN(ir) = RN(ir) - RM(ir) - sh4r.t;
   555                     sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1));
   556                     break;
   557                 case 11:/* SUBV    Rm, Rn */
   558                     UNIMP(ir);
   559                     break;
   560                 case 12:/* ADD     Rm, Rn */
   561                     RN(ir) += RM(ir);
   562                     break;
   563                 case 13:/* DMULS.L Rm, Rn */
   564                     sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir));
   565                     break;
   566                 case 14:/* ADDC    Rm, Rn */
   567                     tmp = RN(ir);
   568                     RN(ir) += RM(ir) + sh4r.t;
   569                     sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 );
   570                     break;
   571                 case 15:/* ADDV    Rm, Rn */
   572                     UNIMP(ir);
   573                     break;
   574                 default: UNDEF(ir);
   575             }
   576             break;
   577         case 4: /* 0100nnnnxxxxxxxx */
   578             switch( ir&0x00FF ) {
   579                 case 0x00: /* SHLL    Rn */
   580                     sh4r.t = RN(ir) >> 31;
   581                     RN(ir) <<= 1;
   582                     break;
   583                 case 0x01: /* SHLR    Rn */
   584                     sh4r.t = RN(ir) & 0x00000001;
   585                     RN(ir) >>= 1;
   586                     break;
   587                 case 0x02: /* STS.L   MACH, [--Rn] */
   588                     RN(ir) -= 4;
   589                     MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) );
   590                     break;
   591                 case 0x03: /* STC.L   SR, [--Rn] */
   592                     CHECKPRIV();
   593                     RN(ir) -= 4;
   594                     MEM_WRITE_LONG( RN(ir), sh4_read_sr() );
   595                     break;
   596                 case 0x04: /* ROTL    Rn */
   597                     sh4r.t = RN(ir) >> 31;
   598                     RN(ir) <<= 1;
   599                     RN(ir) |= sh4r.t;
   600                     break;
   601                 case 0x05: /* ROTR    Rn */
   602                     sh4r.t = RN(ir) & 0x00000001;
   603                     RN(ir) >>= 1;
   604                     RN(ir) |= (sh4r.t << 31);
   605                     break;
   606                 case 0x06: /* LDS.L   [Rn++], MACH */
   607                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   608                         (((uint64_t)MEM_READ_LONG(RN(ir)))<<32);
   609                     RN(ir) += 4;
   610                     break;
   611                 case 0x07: /* LDC.L   [Rn++], SR */
   612                     CHECKPRIV();
   613                     sh4_load_sr( MEM_READ_LONG(RN(ir)) );
   614                     RN(ir) +=4;
   615                     break;
   616                 case 0x08: /* SHLL2   Rn */
   617                     RN(ir) <<= 2;
   618                     break;
   619                 case 0x09: /* SHLR2   Rn */
   620                     RN(ir) >>= 2;
   621                     break;
   622                 case 0x0A: /* LDS     Rn, MACH */
   623                     sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
   624                         (((uint64_t)RN(ir))<<32);
   625                     break;
   626                 case 0x0B: /* JSR     [Rn] */
   627                     CHECKDEST( RN(ir) );
   628                     CHECKSLOTILLEGAL();
   629                     sh4r.in_delay_slot = 1;
   630                     sh4r.pc = sh4r.new_pc;
   631                     sh4r.new_pc = RN(ir);
   632                     sh4r.pr = pc + 4;
   633                     return;
   634                 case 0x0E: /* LDC     Rn, SR */
   635                     CHECKPRIV();
   636                     sh4_load_sr( RN(ir) );
   637                     break;
   638                 case 0x10: /* DT      Rn */
   639                     RN(ir) --;
   640                     sh4r.t = ( RN(ir) == 0 ? 1 : 0 );
   641                     break;
   642                 case 0x11: /* CMP/PZ  Rn */
   643                     sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 );
   644                     break;
   645                 case 0x12: /* STS.L   MACL, [--Rn] */
   646                     RN(ir) -= 4;
   647                     MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac );
   648                     break;
   649                 case 0x13: /* STC.L   GBR, [--Rn] */
   650                     RN(ir) -= 4;
   651                     MEM_WRITE_LONG( RN(ir), sh4r.gbr );
   652                     break;
   653                 case 0x15: /* CMP/PL  Rn */
   654                     sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 );
   655                     break;
   656                 case 0x16: /* LDS.L   [Rn++], MACL */
   657                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   658                         (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir)));
   659                     RN(ir) += 4;
   660                     break;
   661                 case 0x17: /* LDC.L   [Rn++], GBR */
   662                     sh4r.gbr = MEM_READ_LONG(RN(ir));
   663                     RN(ir) +=4;
   664                     break;
   665                 case 0x18: /* SHLL8   Rn */
   666                     RN(ir) <<= 8;
   667                     break;
   668                 case 0x19: /* SHLR8   Rn */
   669                     RN(ir) >>= 8;
   670                     break;
   671                 case 0x1A: /* LDS     Rn, MACL */
   672                     sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
   673                         (uint64_t)((uint32_t)(RN(ir)));
   674                     break;
   675                 case 0x1B: /* TAS.B   [Rn] */
   676                     tmp = MEM_READ_BYTE( RN(ir) );
   677                     sh4r.t = ( tmp == 0 ? 1 : 0 );
   678                     MEM_WRITE_BYTE( RN(ir), tmp | 0x80 );
   679                     break;
   680                 case 0x1E: /* LDC     Rn, GBR */
   681                     sh4r.gbr = RN(ir);
   682                     break;
   683                 case 0x20: /* SHAL    Rn */
   684                     sh4r.t = RN(ir) >> 31;
   685                     RN(ir) <<= 1;
   686                     break;
   687                 case 0x21: /* SHAR    Rn */
   688                     sh4r.t = RN(ir) & 0x00000001;
   689                     RN(ir) = ((int32_t)RN(ir)) >> 1;
   690                     break;
   691                 case 0x22: /* STS.L   PR, [--Rn] */
   692                     RN(ir) -= 4;
   693                     MEM_WRITE_LONG( RN(ir), sh4r.pr );
   694                     break;
   695                 case 0x23: /* STC.L   VBR, [--Rn] */
   696                     CHECKPRIV();
   697                     RN(ir) -= 4;
   698                     MEM_WRITE_LONG( RN(ir), sh4r.vbr );
   699                     break;
   700                 case 0x24: /* ROTCL   Rn */
   701                     tmp = RN(ir) >> 31;
   702                     RN(ir) <<= 1;
   703                     RN(ir) |= sh4r.t;
   704                     sh4r.t = tmp;
   705                     break;
   706                 case 0x25: /* ROTCR   Rn */
   707                     tmp = RN(ir) & 0x00000001;
   708                     RN(ir) >>= 1;
   709                     RN(ir) |= (sh4r.t << 31 );
   710                     sh4r.t = tmp;
   711                     break;
   712                 case 0x26: /* LDS.L   [Rn++], PR */
   713                     sh4r.pr = MEM_READ_LONG( RN(ir) );
   714                     RN(ir) += 4;
   715                     break;
   716                 case 0x27: /* LDC.L   [Rn++], VBR */
   717                     CHECKPRIV();
   718                     sh4r.vbr = MEM_READ_LONG(RN(ir));
   719                     RN(ir) +=4;
   720                     break;
   721                 case 0x28: /* SHLL16  Rn */
   722                     RN(ir) <<= 16;
   723                     break;
   724                 case 0x29: /* SHLR16  Rn */
   725                     RN(ir) >>= 16;
   726                     break;
   727                 case 0x2A: /* LDS     Rn, PR */
   728                     sh4r.pr = RN(ir);
   729                     break;
   730                 case 0x2B: /* JMP     [Rn] */
   731                     CHECKDEST( RN(ir) );
   732                     CHECKSLOTILLEGAL();
   733                     sh4r.in_delay_slot = 1;
   734                     sh4r.pc = sh4r.new_pc;
   735                     sh4r.new_pc = RN(ir);
   736                     return;
   737                 case 0x2E: /* LDC     Rn, VBR */
   738                     CHECKPRIV();
   739                     sh4r.vbr = RN(ir);
   740                     break;
   741                 case 0x32: /* STC.L   SGR, [--Rn] */
   742                     CHECKPRIV();
   743                     RN(ir) -= 4;
   744                     MEM_WRITE_LONG( RN(ir), sh4r.sgr );
   745                     break;
   746                 case 0x33: /* STC.L   SSR, [--Rn] */
   747                     CHECKPRIV();
   748                     RN(ir) -= 4;
   749                     MEM_WRITE_LONG( RN(ir), sh4r.ssr );
   750                     break;
   751                 case 0x37: /* LDC.L   [Rn++], SSR */
   752                     CHECKPRIV();
   753                     sh4r.ssr = MEM_READ_LONG(RN(ir));
   754                     RN(ir) +=4;
   755                     break;
   756                 case 0x3E: /* LDC     Rn, SSR */
   757                     CHECKPRIV();
   758                     sh4r.ssr = RN(ir);
   759                     break;
   760                 case 0x43: /* STC.L   SPC, [--Rn] */
   761                     CHECKPRIV();
   762                     RN(ir) -= 4;
   763                     MEM_WRITE_LONG( RN(ir), sh4r.spc );
   764                     break;
   765                 case 0x47: /* LDC.L   [Rn++], SPC */
   766                     CHECKPRIV();
   767                     sh4r.spc = MEM_READ_LONG(RN(ir));
   768                     RN(ir) +=4;
   769                     break;
   770                 case 0x4E: /* LDC     Rn, SPC */
   771                     CHECKPRIV();
   772                     sh4r.spc = RN(ir);
   773                     break;
   774                 case 0x52: /* STS.L   FPUL, [--Rn] */
   775                     RN(ir) -= 4;
   776                     MEM_WRITE_LONG( RN(ir), sh4r.fpul );
   777                     break;
   778                 case 0x56: /* LDS.L   [Rn++], FPUL */
   779                     sh4r.fpul = MEM_READ_LONG(RN(ir));
   780                     RN(ir) +=4;
   781                     break;
   782                 case 0x5A: /* LDS     Rn, FPUL */
   783                     sh4r.fpul = RN(ir);
   784                     break;
   785                 case 0x62: /* STS.L   FPSCR, [--Rn] */
   786                     RN(ir) -= 4;
   787                     MEM_WRITE_LONG( RN(ir), sh4r.fpscr );
   788                     break;
   789                 case 0x66: /* LDS.L   [Rn++], FPSCR */
   790                     sh4r.fpscr = MEM_READ_LONG(RN(ir));
   791                     RN(ir) +=4;
   792                     break;
   793                 case 0x6A: /* LDS     Rn, FPSCR */
   794                     sh4r.fpscr = RN(ir);
   795                     break;
   796                 case 0xF2: /* STC.L   DBR, [--Rn] */
   797                     CHECKPRIV();
   798                     RN(ir) -= 4;
   799                     MEM_WRITE_LONG( RN(ir), sh4r.dbr );
   800                     break;
   801                 case 0xF6: /* LDC.L   [Rn++], DBR */
   802                     CHECKPRIV();
   803                     sh4r.dbr = MEM_READ_LONG(RN(ir));
   804                     RN(ir) +=4;
   805                     break;
   806                 case 0xFA: /* LDC     Rn, DBR */
   807                     CHECKPRIV();
   808                     sh4r.dbr = RN(ir);
   809                     break;
   810                 case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3:
   811                 case 0xD3: case 0xE3: case 0xF3: /* STC.L   Rn_BANK, [--Rn] */
   812                     CHECKPRIV();
   813                     RN(ir) -= 4;
   814                     MEM_WRITE_LONG( RN(ir), RN_BANK(ir) );
   815                     break;
   816                 case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7:
   817                 case 0xD7: case 0xE7: case 0xF7: /* LDC.L   [Rn++], Rn_BANK */
   818                     CHECKPRIV();
   819                     RN_BANK(ir) = MEM_READ_LONG( RN(ir) );
   820                     RN(ir) += 4;
   821                     break;
   822                 case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE:
   823                 case 0xDE: case 0xEE: case 0xFE: /* LDC     Rm, Rn_BANK */
   824                     CHECKPRIV();
   825                     RN_BANK(ir) = RM(ir);
   826                     break;
   827                 default:
   828                     if( (ir&0x000F) == 0x0F ) {
   829                         /* MAC.W   [Rm++], [Rn++] */
   830                         tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) *
   831                             SIGNEXT16(MEM_READ_WORD(RN(ir)));
   832                         if( sh4r.s ) {
   833                             /* FIXME */
   834                             UNIMP(ir);
   835                         } else sh4r.mac += SIGNEXT32(tmp);
   836                         RM(ir) += 2;
   837                         RN(ir) += 2;
   838                     } else if( (ir&0x000F) == 0x0C ) {
   839                         /* SHAD    Rm, Rn */
   840                         tmp = RM(ir);
   841                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   842                         else if( (tmp & 0x1F) == 0 )  
   843 			  RN(ir) = ((int32_t)RN(ir)) >> 31;
   844                         else 
   845 			  RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1);
   846                     } else if( (ir&0x000F) == 0x0D ) {
   847                         /* SHLD    Rm, Rn */
   848                         tmp = RM(ir);
   849                         if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f);
   850                         else if( (tmp & 0x1F) == 0 ) RN(ir) = 0;
   851                         else RN(ir) >>= (((~tmp) & 0x1F)+1);
   852                     } else UNDEF(ir);
   853             }
   854             break;
   855         case 5: /* 0101nnnnmmmmdddd */
   856             /* MOV.L   [Rm + disp4*4], Rn */
   857             RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) );
   858             break;
   859         case 6: /* 0110xxxxxxxxxxxx */
   860             switch( ir&0x000f ) {
   861                 case 0: /* MOV.B   [Rm], Rn */
   862                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   863                     break;
   864                 case 1: /* MOV.W   [Rm], Rn */
   865                     RN(ir) = MEM_READ_WORD( RM(ir) );
   866                     break;
   867                 case 2: /* MOV.L   [Rm], Rn */
   868                     RN(ir) = MEM_READ_LONG( RM(ir) );
   869                     break;
   870                 case 3: /* MOV     Rm, Rn */
   871                     RN(ir) = RM(ir);
   872                     break;
   873                 case 4: /* MOV.B   [Rm++], Rn */
   874                     RN(ir) = MEM_READ_BYTE( RM(ir) );
   875                     RM(ir) ++;
   876                     break;
   877                 case 5: /* MOV.W   [Rm++], Rn */
   878                     RN(ir) = MEM_READ_WORD( RM(ir) );
   879                     RM(ir) += 2;
   880                     break;
   881                 case 6: /* MOV.L   [Rm++], Rn */
   882                     RN(ir) = MEM_READ_LONG( RM(ir) );
   883                     RM(ir) += 4;
   884                     break;
   885                 case 7: /* NOT     Rm, Rn */
   886                     RN(ir) = ~RM(ir);
   887                     break;
   888                 case 8: /* SWAP.B  Rm, Rn */
   889                     RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) |
   890                         ((RM(ir)&0x000000FF)<<8);
   891                     break;
   892                 case 9: /* SWAP.W  Rm, Rn */
   893                     RN(ir) = (RM(ir)>>16) | (RM(ir)<<16);
   894                     break;
   895                 case 10:/* NEGC    Rm, Rn */
   896                     tmp = 0 - RM(ir);
   897                     RN(ir) = tmp - sh4r.t;
   898                     sh4r.t = ( 0<tmp || tmp<RN(ir) ? 1 : 0 );
   899                     break;
   900                 case 11:/* NEG     Rm, Rn */
   901                     RN(ir) = 0 - RM(ir);
   902                     break;
   903                 case 12:/* EXTU.B  Rm, Rn */
   904                     RN(ir) = RM(ir)&0x000000FF;
   905                     break;
   906                 case 13:/* EXTU.W  Rm, Rn */
   907                     RN(ir) = RM(ir)&0x0000FFFF;
   908                     break;
   909                 case 14:/* EXTS.B  Rm, Rn */
   910                     RN(ir) = SIGNEXT8( RM(ir)&0x000000FF );
   911                     break;
   912                 case 15:/* EXTS.W  Rm, Rn */
   913                     RN(ir) = SIGNEXT16( RM(ir)&0x0000FFFF );
   914                     break;
   915             }
   916             break;
   917         case 7: /* 0111nnnniiiiiiii */
   918             /* ADD    imm8, Rn */
   919             RN(ir) += IMM8(ir);
   920             break;
   921         case 8: /* 1000xxxxxxxxxxxx */
   922             switch( (ir&0x0F00) >> 8 ) {
   923                 case 0: /* MOV.B   R0, [Rm + disp4] */
   924                     MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 );
   925                     break;
   926                 case 1: /* MOV.W   R0, [Rm + disp4*2] */
   927                     MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 );
   928                     break;
   929                 case 4: /* MOV.B   [Rm + disp4], R0 */
   930                     R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) );
   931                     break;
   932                 case 5: /* MOV.W   [Rm + disp4*2], R0 */
   933                     R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) );
   934                     break;
   935                 case 8: /* CMP/EQ  imm, R0 */
   936                     sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 );
   937                     break;
   938                 case 9: /* BT      disp8 */
   939                     CHECKSLOTILLEGAL()
   940                     if( sh4r.t ) {
   941                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   942                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
   943                         sh4r.new_pc = sh4r.pc + 2;
   944                         return;
   945                     }
   946                     break;
   947                 case 11:/* BF      disp8 */
   948                     CHECKSLOTILLEGAL()
   949                     if( !sh4r.t ) {
   950                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   951                         sh4r.pc += (PCDISP8(ir)<<1) + 4;
   952                         sh4r.new_pc = sh4r.pc + 2;
   953                         return;
   954                     }
   955                     break;
   956                 case 13:/* BT/S    disp8 */
   957                     CHECKSLOTILLEGAL()
   958                     if( sh4r.t ) {
   959                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   960                         sh4r.in_delay_slot = 1;
   961                         sh4r.pc = sh4r.new_pc;
   962                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
   963                         sh4r.in_delay_slot = 1;
   964                         return;
   965                     }
   966                     break;
   967                 case 15:/* BF/S    disp8 */
   968                     CHECKSLOTILLEGAL()
   969                     if( !sh4r.t ) {
   970                         CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 )
   971                         sh4r.in_delay_slot = 1;
   972                         sh4r.pc = sh4r.new_pc;
   973                         sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4;
   974                         return;
   975                     }
   976                     break;
   977                 default: UNDEF(ir);
   978             }
   979             break;
   980         case 9: /* 1001xxxxxxxxxxxx */
   981             /* MOV.W   [disp8*2 + pc + 4], Rn */
   982             RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) );
   983             break;
   984         case 10:/* 1010dddddddddddd */
   985             /* BRA     disp12 */
   986             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
   987             CHECKSLOTILLEGAL()
   988             sh4r.in_delay_slot = 1;
   989             sh4r.pc = sh4r.new_pc;
   990             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
   991             return;
   992         case 11:/* 1011dddddddddddd */
   993             /* BSR     disp12 */
   994             CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 )
   995             CHECKSLOTILLEGAL()
   996             sh4r.in_delay_slot = 1;
   997             sh4r.pr = pc + 4;
   998             sh4r.pc = sh4r.new_pc;
   999             sh4r.new_pc = pc + 4 + (DISP12(ir)<<1);
  1000             return;
  1001         case 12:/* 1100xxxxdddddddd */
  1002         switch( (ir&0x0F00)>>8 ) {
  1003                 case 0: /* MOV.B  R0, [GBR + disp8] */
  1004                     MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 );
  1005                     break;
  1006                 case 1: /* MOV.W  R0, [GBR + disp8*2] */
  1007                     MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 );
  1008                     break;
  1009                 case  2: /*MOV.L   R0, [GBR + disp8*4] */
  1010                     MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 );
  1011                     break;
  1012                 case 3: /* TRAPA   imm8 */
  1013                     CHECKSLOTILLEGAL()
  1014                     sh4r.in_delay_slot = 1;
  1015                     MMIO_WRITE( MMU, TRA, UIMM8(ir) );
  1016                     sh4r.pc = sh4r.new_pc;  /* RAISE ends the instruction */
  1017                     sh4r.new_pc += 2;
  1018                     RAISE( EXC_TRAP, EXV_TRAP );
  1019                     break;
  1020                 case 4: /* MOV.B   [GBR + disp8], R0 */
  1021                     R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) );
  1022                     break;
  1023                 case 5: /* MOV.W   [GBR + disp8*2], R0 */
  1024                     R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) );
  1025                     break;
  1026                 case 6: /* MOV.L   [GBR + disp8*4], R0 */
  1027                     R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) );
  1028                     break;
  1029                 case 7: /* MOVA    disp8 + pc&~3 + 4, R0 */
  1030                     R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4;
  1031                     break;
  1032                 case 8: /* TST     imm8, R0 */
  1033                     sh4r.t = (R0 & UIMM8(ir) ? 0 : 1);
  1034                     break;
  1035                 case 9: /* AND     imm8, R0 */
  1036                     R0 &= UIMM8(ir);
  1037                     break;
  1038                 case 10:/* XOR     imm8, R0 */
  1039                     R0 ^= UIMM8(ir);
  1040                     break;
  1041                 case 11:/* OR      imm8, R0 */
  1042                     R0 |= UIMM8(ir);
  1043                     break;
  1044                 case 12:/* TST.B   imm8, [R0+GBR] */
  1045                     sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 );
  1046                     break;
  1047                 case 13:/* AND.B   imm8, [R0+GBR] */
  1048                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1049                                     UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) );
  1050                     break;
  1051                 case 14:/* XOR.B   imm8, [R0+GBR] */
  1052                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1053                                     UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) );
  1054                     break;
  1055                 case 15:/* OR.B    imm8, [R0+GBR] */
  1056                     MEM_WRITE_BYTE( R0 + sh4r.gbr,
  1057                                     UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) );
  1058                     break;
  1060             break;
  1061         case 13:/* 1101nnnndddddddd */
  1062             /* MOV.L   [disp8*4 + pc&~3 + 4], Rn */
  1063             RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 );
  1064             break;
  1065         case 14:/* 1110nnnniiiiiiii */
  1066             /* MOV     imm8, Rn */
  1067             RN(ir) = IMM8(ir);
  1068             break;
  1069         case 15:/* 1111xxxxxxxxxxxx */
  1070             CHECKFPUEN();
  1071             switch( ir&0x000F ) {
  1072                 case 0: /* FADD    FRm, FRn */
  1073                     FRN(ir) += FRM(ir);
  1074                     break;
  1075                 case 1: /* FSUB    FRm, FRn */
  1076                     FRN(ir) -= FRM(ir);
  1077                     break;
  1078                 case 2: /* FMUL    FRm, FRn */
  1079                     FRN(ir) = FRN(ir) * FRM(ir);
  1080                     break;
  1081                 case 3: /* FDIV    FRm, FRn */
  1082                     FRN(ir) = FRN(ir) / FRM(ir);
  1083                     break;
  1084                 case 4: /* FCMP/EQ FRm, FRn */
  1085                     sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 );
  1086                     break;
  1087                 case 5: /* FCMP/GT FRm, FRn */
  1088                     sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 );
  1089                     break;
  1090                 case 6: /* FMOV.S  [Rm+R0], FRn */
  1091                     MEM_FP_READ( RM(ir) + R0, FRNn(ir) );
  1092                     break;
  1093                 case 7: /* FMOV.S  FRm, [Rn+R0] */
  1094                     MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) );
  1095                     break;
  1096                 case 8: /* FMOV.S  [Rm], FRn */
  1097                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1098                     break;
  1099                 case 9: /* FMOV.S  [Rm++], FRn */
  1100                     MEM_FP_READ( RM(ir), FRNn(ir) );
  1101                     RM(ir) += FP_WIDTH;
  1102                     break;
  1103                 case 10:/* FMOV.S  FRm, [Rn] */
  1104                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1105                     break;
  1106                 case 11:/* FMOV.S  FRm, [--Rn] */
  1107                     RN(ir) -= FP_WIDTH;
  1108                     MEM_FP_WRITE( RN(ir), FRMn(ir) );
  1109                     break;
  1110                 case 12:/* FMOV    FRm, FRn */
  1111                     if( IS_FPU_DOUBLESIZE() ) {
  1112                         DRN(ir) = DRM(ir);
  1113                     } else {
  1114                         FRN(ir) = FRM(ir);
  1116                     break;
  1117                 case 13:
  1118                     switch( (ir&0x00F0) >> 4 ) {
  1119                         case 0: /* FSTS    FPUL, FRn */
  1120                             FRN(ir) = FPULf;
  1121                             break;
  1122                         case 1: /* FLDS    FRn, FPUL */
  1123                             FPULf = FRN(ir);
  1124                             break;
  1125                         case 2: /* FLOAT   FPUL, FRn */
  1126                             FRN(ir) = (float)FPULi;
  1127                             break;
  1128                         case 3: /* FTRC    FRn, FPUL */
  1129                             FPULi = (uint32_t)FRN(ir);
  1130                             /* FIXME: is this sufficient? */
  1131                             break;
  1132                         case 4: /* FNEG    FRn */
  1133                             FRN(ir) = -FRN(ir);
  1134                             break;
  1135                         case 5: /* FABS    FRn */
  1136                             FRN(ir) = fabsf(FRN(ir));
  1137                             break;
  1138                         case 6: /* FSQRT   FRn */
  1139                             FRN(ir) = sqrtf(FRN(ir));
  1140                             break;
  1141                         case 7: /* FSRRA FRn */
  1142                             FRN(ir) = 1.0/sqrtf(FRN(ir));
  1143                             break;
  1144                         case 8: /* FLDI0   FRn */
  1145                             FRN(ir) = 0.0;
  1146                             break;
  1147                         case 9: /* FLDI1   FRn */
  1148                             FRN(ir) = 1.0;
  1149                             break;
  1150                         case 10: /* FCNVSD FPUL, DRn */
  1151                             if( IS_FPU_DOUBLEPREC() )
  1152                                 DRN(ir) = (double)FPULf;
  1153                             else UNDEF(ir);
  1154                             break;
  1155                         case 11: /* FCNVDS DRn, FPUL */
  1156                             if( IS_FPU_DOUBLEPREC() ) 
  1157                                 FPULf = (float)DRN(ir);
  1158                             else UNDEF(ir);
  1159                             break;
  1160                         case 14:/* FIPR    FVm, FVn */
  1161                             /* FIXME: This is not going to be entirely accurate
  1162                              * as the SH4 instruction is less precise. Also
  1163                              * need to check for 0s and infinities.
  1164                              */
  1166                             float *fr_bank = FR;
  1167                             int tmp2 = FVN(ir);
  1168                             tmp = FVM(ir);
  1169                             fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] +
  1170                                 fr_bank[tmp+1]*fr_bank[tmp2+1] +
  1171                                 fr_bank[tmp+2]*fr_bank[tmp2+2] +
  1172                                 fr_bank[tmp+3]*fr_bank[tmp2+3];
  1173                             break;
  1175                         case 15:
  1176                             if( (ir&0x0300) == 0x0100 ) { /* FTRV    XMTRX,FVn */
  1177                                 float *fvout = FR+FVN(ir);
  1178                                 float *xm = XF;
  1179                                 float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] };
  1180                                 fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] +
  1181                                     xm[8]*fv[2] + xm[12]*fv[3];
  1182                                 fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] +
  1183                                     xm[9]*fv[2] + xm[13]*fv[3];
  1184                                 fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] +
  1185                                     xm[10]*fv[2] + xm[14]*fv[3];
  1186                                 fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] +
  1187                                     xm[11]*fv[2] + xm[15]*fv[3];
  1188                                 break;
  1190                             else if( (ir&0x0100) == 0 ) { /* FSCA    FPUL, DRn */
  1191                                 float angle = (((float)(short)(FPULi>>16)) +
  1192                                                ((float)(FPULi&16)/65536.0)) *
  1193                                     2 * M_PI;
  1194                                 int reg = FRNn(ir);
  1195                                 FR[reg] = sinf(angle);
  1196                                 FR[reg+1] = cosf(angle);
  1197                                 break;
  1199                             else if( ir == 0xFBFD ) {
  1200                                 /* FRCHG   */
  1201                                 sh4r.fpscr ^= FPSCR_FR;
  1202                                 break;
  1204                             else if( ir == 0xF3FD ) {
  1205                                 /* FSCHG   */
  1206                                 sh4r.fpscr ^= FPSCR_SZ;
  1207                                 break;
  1209                         default: UNDEF(ir);
  1211                     break;
  1212                 case 14:/* FMAC    FR0, FRm, FRn */
  1213                     FRN(ir) += FRM(ir)*FR0;
  1214                     break;
  1215                 default: UNDEF(ir);
  1217             break;
  1219     sh4r.pc = sh4r.new_pc;
  1220     sh4r.new_pc += 2;
  1221     sh4r.in_delay_slot = 0;
.