lxdream 0.9.1| filename | src/asic.h |
| changeset | 855:b937948d79d9 |
| prev | 753:1fe39c3a9bbc |
| next | 1100:50e702af9373 |
| author | nkeynes |
| date | Sat Dec 27 02:59:35 2008 +0000 (15 years ago) |
| branch | lxdream-mem |
| permissions | -rw-r--r-- |
| last change | Replace fpscr_mask/fpscr flags in xlat_cache_block with a single xlat_sh4_mode, which tracks the field of the same name in sh4r - actually a little faster this way. Now depends on SR.MD, FPSCR.PR and FPSCR.SZ (although it doesn't benefit from the SR flag yet). Also fixed the failure to check the flags in the common case (code address returned by previous block) which took away the performance benefits, but oh well. |
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1 /**
2 * $Id$
3 *
4 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
5 * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions,
6 * although some functions (maple, ide) are implemented elsewhere.
7 *
8 * Copyright (c) 2005 Nathan Keynes.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
21 #include "mmio.h"
23 /**
24 * ASIC interrupts are mappable to any (or all of) 3 actual CPU IRQ lines.
25 * events selected for IRQA trigger IRQ 13, IRQB => 11 and IRQC => 9.
26 */
28 MMIO_REGION_BEGIN( 0x005F6000, ASIC, "System ASIC" )
29 LONG_PORT( 0x800, PVRDMADEST, PORT_MRW, 0, "PVR DMA Dest Address" )
30 LONG_PORT( 0x804, PVRDMACNT, PORT_MRW, 0, "PVR DMA Byte Count" )
31 LONG_PORT( 0x808, PVRDMACTL, PORT_MRW, 0, "PVR DMA Control" )
32 LONG_PORT( 0x810, SORTDMATBL, PORT_MRW, 0, "Sort DMA Table address" )
33 LONG_PORT( 0x814, SORTDMADATA, PORT_MRW, 0, "Sort DMA Data base address" )
34 LONG_PORT( 0x818, SORTDMATSIZ, PORT_MRW, 0, "Sort DMA Table entry size" )
35 LONG_PORT( 0x81C, SORTDMAASIZ, PORT_MRW, 0, "Sort DMA Table address size" )
36 LONG_PORT( 0x820, SORTDMACTL, PORT_MRW, 0, "Sort DMA Control" )
37 LONG_PORT( 0x840, ASICUNK5, PORT_MRW, 0, "ASIC <unknown5>" )
38 LONG_PORT( 0x844, ASICUNK6, PORT_MRW, 0, "ASIC <unknown6>" )
39 LONG_PORT( 0x848, ASICUNK7, PORT_MRW, 0, "ASIC <unknown7>" )
40 LONG_PORT( 0x84C, ASICUNK8, PORT_MRW, 0, "ASIC <unknown8>" )
41 LONG_PORT( 0x860, SORTDMACNT, PORT_MR, 0, "Sort DMA Transfer count" )
42 LONG_PORT( 0x884, PVRDMARGN1, PORT_MRW, 0, "PVR DMA Dest region 1" )
43 LONG_PORT( 0x888, PVRDMARGN2, PORT_MRW, 0, "PVR DMA Dest region 2" )
44 LONG_PORT( 0x88C, G2STATUS, PORT_MR|PORT_NOTRACE, 0x0E, "G2 Fifo status" )
45 LONG_PORT( 0x890, SYSRESET, PORT_W, 0, "System reset port" )
46 LONG_PORT( 0x89C, ASICUNKB, PORT_MRW, 0xB, "Unknown, always 0xB?" )
47 LONG_PORT( 0x8A0, ASICUNKC, PORT_MRW, 0, "ASIC <unknownC>" )
48 LONG_PORT( 0x8A4, ASICUNKD, PORT_MRW, 0, "ASIC <unknownD>" )
49 LONG_PORT( 0x8AC, ASICUNKE, PORT_MRW, 0, "ASIC <unknownE>" )
50 LONG_PORT( 0x900, PIRQ0, PORT_MRW|PORT_NOTRACE, 0, "Pending interrupts 0" )
51 LONG_PORT( 0x904, PIRQ1, PORT_MRW, 0, "Pending interrupts 1" )
52 LONG_PORT( 0x908, PIRQ2, PORT_MRW, 0, "Pending interrupts 2" )
53 LONG_PORT( 0x910, IRQA0, PORT_MRW, 0, "IRQ A event map 0" )
54 LONG_PORT( 0x914, IRQA1, PORT_MRW, 0, "IRQ A event map 1" )
55 LONG_PORT( 0x918, IRQA2, PORT_MRW, 0, "IRQ A event map 2" )
56 LONG_PORT( 0x920, IRQB0, PORT_MRW, 0, "IRQ B event map 0" )
57 LONG_PORT( 0x924, IRQB1, PORT_MRW, 0, "IRQ B event map 1" )
58 LONG_PORT( 0x928, IRQB2, PORT_MRW, 0, "IRQ B event map 2" )
59 LONG_PORT( 0x930, IRQC0, PORT_MRW, 0, "IRQ C event map 0" )
60 LONG_PORT( 0x934, IRQC1, PORT_MRW, 0, "IRQ C event map 1" )
61 LONG_PORT( 0x938, IRQC2, PORT_MRW, 0, "IRQ C event map 2" )
62 LONG_PORT( 0x940, ASIC9UNK1, PORT_MRW, 0, "Unknown 1" )
63 LONG_PORT( 0x944, ASIC9UNK2, PORT_MRW, 0, "Unknown 2" )
64 LONG_PORT( 0x950, ASIC9UNK3, PORT_MRW, 0, "Unknown 3" )
65 LONG_PORT( 0x954, ASIC9UNK4, PORT_MRW, 0, "Unknown 4" )
66 /* ASIC events repeats at 0x980..0x9FF, then the whole region 800..9ff
67 * repeats at 000..1ff, 200..3ff, 400..5ff, 600..7ff, a00..bff.
68 * The whole region 800..8ff is long-readable, but since I so far have no idea
69 * what any of it means (nor have I seen any of it accessed), they're not
70 * listed above.
71 */
74 LONG_PORT( 0xC04, MAPLE_DMA, PORT_MRW, UNDEFINED, "Maple DMA Address" )
75 LONG_PORT( 0xC10, MAPLE_RESET2, PORT_MRW, UNDEFINED, "Maple Reset 2" )
76 LONG_PORT( 0xC14, MAPLE_ENABLE, PORT_MRW, UNDEFINED, "Maple Enable" )
77 LONG_PORT( 0xC18, MAPLE_STATE, PORT_MRW, 0, "Maple State" )
78 LONG_PORT( 0xC70, MAPLE_UNK1, PORT_MRW, 0, "Maple unknown 1" )
79 LONG_PORT( 0xC74, MAPLE_UNK2, PORT_MRW, 0, "Maple unknown 2" )
80 LONG_PORT( 0xC78, MAPLE_UNK3, PORT_MRW, 0, "Maple unknown 3" )
81 LONG_PORT( 0xC7C, MAPLE_UNK4, PORT_MRW, 0, "Maple unknown 4" )
82 LONG_PORT( 0xC80, MAPLE_SPEED, PORT_MRW, UNDEFINED, "Maple Speed" )
83 LONG_PORT( 0xC84, MAPLE_UNK5, PORT_MRW, 0, "Maple unknown 5" )
84 LONG_PORT( 0xC8C, MAPLE_RESET1, PORT_MRW, UNDEFINED, "Maple Reset 1" )
85 LONG_PORT( 0xCE8, MAPLE_UNK6, PORT_MRW, 0, "Maple unknown 6" )
86 LONG_PORT( 0xCF4, MAPLE_SRC, PORT_MRW, 0, "Maple current source" )
87 LONG_PORT( 0xCF8, MAPLE_DEST1, PORT_MRW, 0, "Maple current destination" )
88 LONG_PORT( 0xCFC, MAPLE_DEST2, PORT_MRW, 0, "Maple current destination 2?" )
89 /* Note: Maple registers repeat at 0xD00..0xDFF,
90 * 0xE00..0xEFF and 0xF00..0xFFF */
91 MMIO_REGION_END
93 MMIO_REGION_BEGIN( 0x005F7000, EXTDMA, "ASIC External DMA" )
94 BYTE_PORT( 0x018, IDEALTSTATUS, PORT_RW, 0, "IDE Device Control / Alt-status" ) /* 10110 */
95 BYTE_PORT( 0x01C, IDEUNK1, PORT_MRW, 0, "IDE Unknown" )
96 WORD_PORT( 0x080, IDEDATA, PORT_RW, 0, "IDE Data" )
97 BYTE_PORT( 0x084, IDEFEAT, PORT_RW, 0, "IDE Feature / Error" )
98 BYTE_PORT( 0x088, IDECOUNT, PORT_RW, 0, "IDE Sector Count" )
99 BYTE_PORT( 0x08C, IDELBA0, PORT_RW, 0, "IDE LBA lo" ) /* AKA sector */
100 BYTE_PORT( 0x090, IDELBA1, PORT_RW, 0, "IDE LBA mid" ) /* AKA Cyl lo */
101 BYTE_PORT( 0x094, IDELBA2, PORT_RW, 0, "IDE LBA hi" ) /* AKA Cyl hi */
102 BYTE_PORT( 0x098, IDEDEV, PORT_RW, 0, "IDE Device" )
103 BYTE_PORT( 0x09C, IDECMD, PORT_RW, 0, "IDE Command/Status" )
104 LONG_PORT( 0x404, IDEDMASH4, PORT_MRW, 0, "IDE DMA SH4 address" )
105 LONG_PORT( 0x408, IDEDMASIZ, PORT_MRW, 0, "IDE DMA Size" )
106 LONG_PORT( 0x40C, IDEDMADIR, PORT_MRW, 0, "IDE DMA Direction" )
107 LONG_PORT( 0x414, IDEDMACTL1, PORT_MRW, 0, "IDE DMA Control 1" )
108 LONG_PORT( 0x418, IDEDMACTL2, PORT_MRW, 0, "IDE DMA Control 2" )
109 WORD_PORT( 0x480, EXTDMAUNK0, PORT_MRW, 0, "Ext DMA <unknown0>" )
110 LONG_PORT( 0x484, EXTDMAUNK1, PORT_MRW, 0, "Ext DMA <unknown1>" )
111 LONG_PORT( 0x488, EXTDMAUNK2, PORT_MRW, 0, "Ext DMA <unknown2>" )
112 LONG_PORT( 0x48C, EXTDMAUNK3, PORT_MRW, 0, "Ext DMA <unknown3>" )
113 LONG_PORT( 0x490, EXTDMAUNK4, PORT_MRW, 0, "Ext DMA <unknown4>" )
114 LONG_PORT( 0x494, EXTDMAUNK5, PORT_MRW, 0, "Ext DMA <unknown5>" )
115 LONG_PORT( 0x4A0, EXTDMAUNK6, PORT_MRW, 0, "Ext DMA <unknown6>" )
116 LONG_PORT( 0x4A4, EXTDMAUNK7, PORT_MRW, 0, "Ext DMA <unknown7>" )
117 LONG_PORT( 0x4B4, EXTDMAUNK8, PORT_MRW, 0, "Ext DMA <unknown8>" )
118 LONG_PORT( 0x4B8, IDEDMACFG, PORT_MRW, 0, "IDE DMA Config" ) /* 88437F00 */
119 LONG_PORT( 0x4E4, IDEACTIVATE, PORT_MRW, 0, "IDE activate" )
120 LONG_PORT( 0x4F8, IDEDMATXSIZ, PORT_MRW, 0, "IDE DMA transfered size" )
121 LONG_PORT( 0x800, G2DMA0EXT, PORT_MRW, 0, "G2 DMA0 External address" )
122 LONG_PORT( 0x804, G2DMA0SH4, PORT_MRW, 0, "G2 DMA0 SH4-based address" )
123 LONG_PORT( 0x808, G2DMA0SIZ, PORT_MRW, 0, "G2 DMA0 Size" )
124 LONG_PORT( 0x80C, G2DMA0DIR, PORT_MRW, 0, "G2 DMA0 Direction" )
125 LONG_PORT( 0x810, G2DMA0MOD, PORT_MRW, 0, "G2 DMA0 Mode" )
126 LONG_PORT( 0x814, G2DMA0CTL1, PORT_MRW, 0, "G2 DMA0 Control 1" )
127 LONG_PORT( 0x818, G2DMA0CTL2, PORT_MRW, 0, "G2 DMA0 Control 2" )
128 LONG_PORT( 0x81C, G2DMA0STOP, PORT_MRW, 0x20, "G2 DMA0 Stop" )
129 LONG_PORT( 0x820, G2DMA1EXT, PORT_MRW, 0, "G2 DMA1 External address" )
130 LONG_PORT( 0x824, G2DMA1SH4, PORT_MRW, 0, "G2 DMA1 SH4-based address" )
131 LONG_PORT( 0x828, G2DMA1SIZ, PORT_MRW, 0, "G2 DMA1 Size" )
132 LONG_PORT( 0x82C, G2DMA1DIR, PORT_MRW, 0, "G2 DMA1 Direction" )
133 LONG_PORT( 0x830, G2DMA1MOD, PORT_MRW, 0, "G2 DMA1 Mode" )
134 LONG_PORT( 0x834, G2DMA1CTL1, PORT_MRW, 0, "G2 DMA1 Control 1" )
135 LONG_PORT( 0x838, G2DMA1CTL2, PORT_MRW, 0, "G2 DMA1 Control 2" )
136 LONG_PORT( 0x83C, G2DMA1STOP, PORT_MRW, 0, "G2 DMA1 Stop" )
137 LONG_PORT( 0x840, G2DMA2EXT, PORT_MRW, 0, "G2 DMA2 External address" )
138 LONG_PORT( 0x844, G2DMA2SH4, PORT_MRW, 0, "G2 DMA2 SH4-based address" )
139 LONG_PORT( 0x848, G2DMA2SIZ, PORT_MRW, 0, "G2 DMA2 Size" )
140 LONG_PORT( 0x84C, G2DMA2DIR, PORT_MRW, 0, "G2 DMA2 Direction" )
141 LONG_PORT( 0x850, G2DMA2MOD, PORT_MRW, 0, "G2 DMA2 Mode" )
142 LONG_PORT( 0x854, G2DMA2CTL1, PORT_MRW, 0, "G2 DMA2 Control 1" )
143 LONG_PORT( 0x858, G2DMA2CTL2, PORT_MRW, 0, "G2 DMA2 Control 2" )
144 LONG_PORT( 0x85C, G2DMA2STOP, PORT_MRW, 0, "G2 DMA2 Stop" )
145 LONG_PORT( 0x860, G2DMA3EXT, PORT_MRW, 0, "G2 DMA3 External address" )
146 LONG_PORT( 0x864, G2DMA3SH4, PORT_MRW, 0, "G2 DMA3 SH4-based address" )
147 LONG_PORT( 0x868, G2DMA3SIZ, PORT_MRW, 0, "G2 DMA3 Size" )
148 LONG_PORT( 0x86C, G2DMA3DIR, PORT_MRW, 0, "G2 DMA3 Direction" )
149 LONG_PORT( 0x870, G2DMA3MOD, PORT_MRW, 0, "G2 DMA3 Mode" )
150 LONG_PORT( 0x874, G2DMA3CTL1, PORT_MRW, 0, "G2 DMA3 Control 1" )
151 LONG_PORT( 0x878, G2DMA3CTL2, PORT_MRW, 0, "G2 DMA3 Control 2" )
152 LONG_PORT( 0x87C, G2DMA3STOP, PORT_MRW, 0, "G2 DMA3 Stop" )
153 LONG_PORT( 0x890, G2DMAWAIT, PORT_MRW, 0, "G2 DMA wait states (?)" )
154 LONG_PORT( 0x894, G2DMAUN1, PORT_MRW, 0, "G2 DMA <unknown1>" )
155 LONG_PORT( 0x898, G2DMAUN2, PORT_MRW, 0, "G2 DMA <unknown2>" )
156 LONG_PORT( 0x89C, G2DMAUN3, PORT_MRW, 0, "G2 DMA <unknown3>" )
157 LONG_PORT( 0x8A0, G2DMAUN4, PORT_MRW, 0, "G2 DMA <unknown4>" )
158 LONG_PORT( 0x8A4, G2DMAUN5, PORT_MRW, 0, "G2 DMA <unknown5>" )
159 LONG_PORT( 0x8A8, G2DMAUN6, PORT_MRW, 0, "G2 DMA <unknown6>" )
160 LONG_PORT( 0x8AC, G2DMAUN7, PORT_MRW, 0, "G2 DMA <unknown7>" )
161 LONG_PORT( 0x8B0, G2DMAUN8, PORT_MRW, 0, "G2 DMA <unknown8>" )
162 LONG_PORT( 0x8B4, G2DMAUN9, PORT_MRW, 0, "G2 DMA <unknown9>" )
163 LONG_PORT( 0x8B8, G2DMAUN10, PORT_MRW, 0, "G2 DMA <unknown10>" )
164 LONG_PORT( 0x8BC, G2DMACFG, PORT_MRW, 0, "G2 DMA Config" ) /* 46597F00 */
165 LONG_PORT( 0xC00, PVRDMA2EXT, PORT_MRW, 0, "PVR DMA External address" )
166 LONG_PORT( 0xC04, PVRDMA2SH4, PORT_MRW, 0, "PVR DMA SH4 address" )
167 LONG_PORT( 0xC08, PVRDMA2SIZ, PORT_MRW, 0, "PVR DMA Size" )
168 LONG_PORT( 0xC0C, PVRDMA2DIR, PORT_MRW, 0, "PVR DMA Direction" )
169 LONG_PORT( 0xC10, PVRDMA2MOD, PORT_MRW, 0, "PVR DMA Mode" )
170 LONG_PORT( 0xC14, PVRDMA2CTL1, PORT_MRW, 0, "PVR DMA Control 1" )
171 LONG_PORT( 0xC18, PVRDMA2CTL2, PORT_MRW, 0, "PVR DMA Control 2" )
172 LONG_PORT( 0xC80, PVRDMA2CFG, PORT_MRW, 0, "PVR DMA Config" ) /* 67027F00 */
174 MMIO_REGION_END
176 #define EVENT_PVR_RENDER_DONE 2
177 #define EVENT_SCANLINE2 3
178 #define EVENT_SCANLINE1 4
179 #define EVENT_HPOS 5
180 #define EVENT_PVR_YUV_DONE 6
181 #define EVENT_PVR_OPAQUE_DONE 7
182 #define EVENT_PVR_OPAQUEMOD_DONE 8
183 #define EVENT_PVR_TRANS_DONE 9
184 #define EVENT_PVR_TRANSMOD_DONE 10
185 #define EVENT_PVR_DMA2 11
186 #define EVENT_MAPLE_DMA 12
187 #define EVENT_MAPLE_ERR 13 /* ??? */
188 #define EVENT_IDE_DMA 14
189 #define EVENT_G2_DMA0 15
190 #define EVENT_G2_DMA1 16
191 #define EVENT_G2_DMA2 17
192 #define EVENT_G2_DMA3 18
193 #define EVENT_PVR_DMA 19
194 #define EVENT_SORT_DMA 20
195 #define EVENT_PVR_PUNCHOUT_DONE 21
196 #define EVENT_CASCADE1 30 /* Set if something in the second word is active */
197 #define EVENT_CASCADE2 31 /* Set if something in the third word is active */
199 #define EVENT_IDE 32
200 #define EVENT_AICA 33
202 #define EVENT_PVR_PRIM_ALLOC_FAIL 66
203 #define EVENT_PVR_MATRIX_ALLOC_FAIL 67
204 #define EVENT_PVR_BAD_INPUT 68
205 #define EVENT_SORT_DMA_ERR 92
207 #define IS_IDE_REGISTER(x) ( (x) <= IDEDMACTL2 )
209 /**
210 * Raise an ASIC event
211 */
212 void asic_event( int event );
214 /**
215 * Clear an ASIC event. Currently only the IDE controller is known to use
216 * this functionality.
217 */
218 void asic_clear_event( int event );
220 void asic_g2_write_word( );
.