filename | test/testregs.c |
changeset | 826:69f2c9f1e608 |
prev | 818:2e08d8237d33 |
author | nkeynes |
date | Sat Dec 27 02:59:35 2008 +0000 (15 years ago) |
branch | lxdream-mem |
permissions | -rw-r--r-- |
last change | Replace fpscr_mask/fpscr flags in xlat_cache_block with a single xlat_sh4_mode, which tracks the field of the same name in sh4r - actually a little faster this way. Now depends on SR.MD, FPSCR.PR and FPSCR.SZ (although it doesn't benefit from the SR flag yet). Also fixed the failure to check the flags in the common case (code address returned by previous block) which took away the performance benefits, but oh well. |
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1 /**
2 * $Id$
3 *
4 * Register mask tests. These are simple "write value to register and check
5 * that we read back what we expect" tests.
6 *
7 * Copyright (c) 2006 Nathan Keynes.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
20 #include "lib.h"
21 #include <stdio.h>
23 /**
24 * Constant to mean "same as previous value". Can't be used otherwise.
25 */
26 #define UNCHANGED 0xDEADBEEF
28 struct test {
29 unsigned int reg;
30 unsigned int write;
31 unsigned int expect;
32 };
36 struct test test_cases[] = {
37 { 0xA05F6800, 0xFFFFFFFF, 0x13FFFFE0 },
38 { 0xA05F6800, 0x00000000, 0x10000000 },
39 { 0xA05F6804, 0xFFFFFFFF, 0x00FFFFE0 },
40 // { 0xA05F6808, 0xFFFFFFFF, 0x00000001 },
41 // { 0xA05F6808, 0x00000000, 0x00000000 }, // DMA start
42 // { 0xA05F680C, 0xFFFFFFFF, 0x00000000 }, // Not a register afaik
43 { 0xA05F6810, 0x00000000, 0x08000000 },
44 { 0xA05F6810, 0xFFFFFFFF, 0x0FFFFFE0 },
45 { 0xA05F6814, 0x00000000, 0x08000000 },
46 { 0xA05F6814, 0xFFFFFFFF, 0x0FFFFFE0 },
47 { 0xA05F6818, 0xFFFFFFFF, 0x00000001 },
48 { 0xA05F681C, 0xFFFFFFFF, 0x00000001 },
49 // { 0xA05F7400, 0xFFFFFFFF, 0x00000000 }, // Not a register
50 { 0xA05F7404, 0xFFFFFFFF, 0x1FFFFFE0 },
51 { 0xA05F7404, 0x00000000, 0x00000000 },
52 { 0xA05F7408, 0xFFFFFFFF, 0x01FFFFFE },
53 { 0xA05F740C, 0xFFFFFFFF, 0x00000001 },
54 // { 0xA05F7410, 0xFFFFFFFF, 0x00000000 }, // Not a register
55 { 0xA05F7414, 0xFFFFFFFF, 0x00000001 },
56 // { 0xA05F7418, 0xFFFFFFFF, 0x00000001 }, // DMA start
57 // { 0xA05F741C, 0xFFFFFFFF, 0x00000000 }, // Not a register
58 { 0xA05F7800, 0xFFFFFFFF, 0x9FFFFFE0 },
59 { 0xA05F7800, 0x00000000, 0x00000000 },
60 { 0xA05F7804, 0xFFFFFFFF, 0x9FFFFFE0 },
61 { 0xA05F7808, 0xFFFFFFFF, 0x9FFFFFE0 },
62 { 0xA05F780C, 0xFFFFFFFF, 0x00000001 },
63 { 0xA05F7810, 0xFFFFFFFF, 0x00000007 },
64 { 0xA05F7814, 0xFFFFFFFF, 0x00000001 },
65 // { 0xA05F7818, 0xFFFFFFFF, 0x00000000 }, // DMA start
66 { 0xA05F781C, 0xFFFFFFFF, 0x00000037 },
67 { 0xA05F8000, 0xFFFFFFFF, 0x17FD11DB }, /* PVRID read-only */
68 { 0xA05F8004, 0xFFFFFFFF, 0x00000011 }, /* PVRVER read-only */
69 { 0xA05F8008, 0xFFFFFFFF, 0x00000007 }, /* Reset */
70 { 0xA05F8010, 0xFFFFFFFF, 0 },
71 // { 0xA05F8014, 0xFFFFFFFF, 0x00000000 }, /* Render start */
72 { 0xA05F8018, 0xFFFFFFFF, 0x000007FF }, /* ??? */
73 { 0xA05F801C, 0xFFFFFFFF, 0x00000000 }, /* ??? */
74 { 0xA05F8020, 0xFFFFFFFF, 0x00F00000 }, /* Render poly buffer address ??? */
75 { 0xA05F8024, 0xFFFFFFFF, 0x00000000 }, /* ??? */
76 { 0xA05F8028, 0xFFFFFFFF, 0x00000000 }, /* ??? */
77 { 0xA05F802C, 0xFFFFFFFF, 0x00FFFFFC }, /* Render Tile buffer address */
78 { 0xA05F8030, 0xFFFFFFFF, 0x00010101 }, /* Render TSP cache? */
79 { 0xA05F8034, 0xFFFFFFFF, 0 },
80 { 0xA05F8038, 0xFFFFFFFF, 0 },
81 { 0xA05F803C, 0xFFFFFFFF, 0 },
82 { 0xA05F8040, 0xFFFFFFFF, 0x01FFFFFF }, /* Display border colour */
83 { 0xA05F8044, 0xFFFFFFFF, 0x00FFFF7F }, /* Display config */
84 { 0xA05F8048, 0xFFFFFFFF, 0x00FFFF0F }, /* Render config */
85 { 0xA05F804C, 0xFFFFFFFF, 0x000001FF }, /* Render size */
86 { 0xA05F8050, 0xFFFFFFFF, 0x00FFFFFC }, /* Display address 1 */
87 { 0xA05F8054, 0xFFFFFFFF, 0x00FFFFFC }, /* Display address 2 */
88 { 0xA05F8058, 0xFFFFFFFF, 0x00000000 }, /* ??? */
89 { 0xA05F805C, 0xFFFFFFFF, 0x3FFFFFFF }, /* Display size */
90 { 0xA05F8060, 0xFFFFFFFF, 0x01FFFFFC }, /* Render address 1 */
91 { 0xA05F8064, 0xFFFFFFFF, 0x01FFFFFC }, /* Render address 2 */
92 { 0xA05F8068, 0xFFFFFFFF, 0x07FF07FF }, /* Render horizontal clip */
93 { 0xA05F806C, 0xFFFFFFFF, 0x03FF03FF }, /* Render vertical clip */
94 { 0xA05F8070, 0xFFFFFFFF, 0 },
95 { 0xA05F8074, 0xFFFFFFFF, 0x000001FF }, /* Render shadow mode */
96 { 0xA05F8078, 0xFFFFFFFF, 0x7FFFFFFF }, /* Near z clip */
97 { 0xA05F807C, 0xFFFFFFFF, 0x003FFFFF }, /* Render object config */
98 { 0xA05F8080, 0xFFFFFFFF, 0x00000007 }, /* ??? */
99 { 0xA05F8084, 0xFFFFFFFF, 0x7FFFFFFF }, /* Render tsp clip */
100 { 0xA05F8088, 0xFFFFFFFF, 0xFFFFFFF0 }, /* Far z clip */
101 { 0xA05F808C, 0xFFFFFFFF, 0x1FFFFFFF }, /* Render background plane config */
102 { 0xA05F8090, 0xFFFFFFFF, 0 },
103 { 0xA05F8094, 0xFFFFFFFF, 0 },
104 { 0xA05F8098, 0xFFFFFFFF, 0x00FFFFF9 }, /* ISP config? */
105 { 0xA05F809C, 0xFFFFFFFF, 0 },
106 { 0xA05F80A0, 0xFFFFFFFF, 0x000000FF }, /* Vram cfg1? */
107 { 0xA05F80A4, 0xFFFFFFFF, 0x003FFFFF },
108 { 0xA05F80A8, 0xFFFFFFFF, 0x1FFFFFFF },
109 { 0xA05F80AC, 0xFFFFFFFF, 0 },
110 { 0xA05F80B0, 0xFFFFFFFF, 0x00FFFFFF },
111 { 0xA05F80B4, 0xFFFFFFFF, 0x00FFFFFF },
112 { 0xA05F80B8, 0xFFFFFFFF, 0x0000FFFF },
113 { 0xA05F80BC, 0xFFFFFFFF, 0xFFFFFFFF },
114 { 0xA05F80C0, 0xFFFFFFFF, 0xFFFFFFFF },
115 { 0xA05F80C4, 0xFFFFFFFF, UNCHANGED }, /* Gun pos */
116 { 0xA05F80C8, 0xFFFFFFFF, 0x03FF33FF }, /* Horizontal scanline irq */
117 { 0xA05F80CC, 0xFFFFFFFF, 0x03FF03FF }, /* Vertical scanline irq */
118 { 0xA05F80D0, 0xFFFFFFFF, 0x000003FF },
119 { 0xA05F80D4, 0xFFFFFFFF, 0x03FF03FF },
120 { 0xA05F80D8, 0xFFFFFFFF, 0x03FF03FF },
121 { 0xA05F80DC, 0xFFFFFFFF, 0x03FF03FF },
122 { 0xA05F80E0, 0xFFFFFFFF, 0xFFFFFF7F },
123 { 0xA05F80E4, 0xFFFFFFFF, 0x00031F1F },
124 { 0xA05F80E8, 0xFFFFFFFF, 0x003F01FF },
125 { 0xA05F80EC, 0xFFFFFFFF, 0x000003FF },
126 { 0xA05F80F0, 0xFFFFFFFF, 0x03FF03FF },
127 { 0xA05F80F4, 0xFFFFFFFF, 0x0007FFFF },
128 { 0xA05F80F8, 0xFFFFFFFF, 0 },
129 { 0xA05F80FC, 0xFFFFFFFF, 0 },
130 { 0xA05F8100, 0xFFFFFFFF, 0 },
131 { 0xA05F8104, 0xFFFFFFFF, 0 },
132 { 0xA05F8108, 0xFFFFFFFF, 0x00000003 },
133 { 0xA05F810C, 0xFFFFFFFF, UNCHANGED },
134 { 0xA05F8110, 0xFFFFFFFF, 0x000FFF3F },
135 { 0xA05F8114, 0xFFFFFFFF, UNCHANGED },
136 { 0xA05F8118, 0xFFFFFFFF, 0x0000FFFF },
137 { 0xA05F811C, 0xFFFFFFFF, 0x000000FF },
138 { 0xA05F8120, 0xFFFFFFFF, 0 },
139 { 0xA05F8124, 0xFFFFFFFF, 0x00FFFFE0 }, /* TA Tile matrix base */
140 { 0xA05F8128, 0xFFFFFFFF, 0x00FFFFFC }, /* TA Polygon base */
141 { 0xA05F812C, 0xFFFFFFFF, 0x00FFFFE0 }, /* TA Tile matrix end */
142 { 0xA05F8130, 0xFFFFFFFF, 0x00FFFFFC }, /* TA Polygon end */
143 { 0xA05F8134, 0xFFFFFFFF, UNCHANGED }, /* TA Tilelist posn */
144 { 0xA05F8138, 0xFFFFFFFF, UNCHANGED }, /* TA polygon posn */
145 { 0xA05F813C, 0xFFFFFFFF, 0x000F003F }, /* TA tile matrix size */
146 { 0xA05F8140, 0xFFFFFFFF, 0x00133333 }, /* TA object config */
147 { 0xA05F8144, 0xFFFFFFFF, 0x00000000 }, /* TA initialize */
148 { 0xA05F8148, 0xFFFFFFFF, 0x00FFFFF8 },
149 { 0xA05F814C, 0xFFFFFFFF, 0x01013F3F },
150 { 0xA05F8150, 0xFFFFFFFF, 0 },
151 { 0xA05F8154, 0xFFFFFFFF, 0 },
152 { 0xA05F8158, 0xFFFFFFFF, 0 },
153 { 0xA05F815C, 0xFFFFFFFF, 0 },
154 { 0xA05F8160, 0xFFFFFFFF, 0 },
155 { 0xA05F8164, 0xFFFFFFFF, 0x00FFFFE0 }, /* TA Tile list start */
156 { 0xA05F8168, 0xFFFFFFFF, 0 },
157 { 0xA05F816C, 0xFFFFFFFF, 0 },
158 { 0xA05F8170, 0xFFFFFFFF, 0 },
159 { 0xA05F8174, 0xFFFFFFFF, 0 },
160 { 0xA05F8178, 0xFFFFFFFF, 0 },
161 { 0xA05F817C, 0xFFFFFFFF, 0 },
162 { 0xA05F8180, 0xFFFFFFFF, 0 },
163 { 0xA05F8184, 0xFFFFFFFF, 0 },
164 { 0xA05F8188, 0xFFFFFFFF, 0 },
165 { 0xA05F818C, 0xFFFFFFFF, 0 },
166 { 0xA05F8190, 0xFFFFFFFF, 0 },
167 { 0xA05F8194, 0xFFFFFFFF, 0 },
168 { 0xA05F8198, 0xFFFFFFFF, 0 },
169 { 0xA05F819C, 0xFFFFFFFF, 0 },
170 { 0xA05F81A0, 0xFFFFFFFF, 0 },
171 { 0xA05F81A4, 0xFFFFFFFF, 0 },
172 { 0xA05F81A8, 0xFFFFFFFF, 0x00000001 },
173 { 0xA05F81A8, 0x00000000, 0x00000000 },
174 { 0xA05F81AC, 0xFFFFFFFF, 0x0300FFFF },
175 { 0xA05F81B0, 0xFFFFFFFF, 0 },
176 { 0xA05F81B4, 0xFFFFFFFF, 0 },
177 { 0xA05F81B8, 0xFFFFFFFF, 0 },
178 { 0xA05F81BC, 0xFFFFFFFF, 0 },
179 { 0xA05F81C0, 0xFFFFFFFF, 0 },
180 { 0xA05F81C4, 0xFFFFFFFF, 0 },
181 { 0xA05F81C8, 0xFFFFFFFF, 0 },
182 { 0xA05F81CC, 0xFFFFFFFF, 0 },
183 { 0xA05F81D0, 0xFFFFFFFF, 0 },
184 { 0xA05F81D4, 0xFFFFFFFF, 0 },
185 { 0xA05F81D8, 0xFFFFFFFF, 0 },
186 { 0xA05F81DC, 0xFFFFFFFF, 0 },
187 { 0xA05F81E0, 0xFFFFFFFF, 0 },
188 { 0xA05F81E4, 0xFFFFFFFF, 0 },
189 { 0xA05F81E8, 0xFFFFFFFF, 0 },
190 { 0xA05F81EC, 0xFFFFFFFF, 0 },
191 { 0xA05F81F0, 0xFFFFFFFF, 0 },
192 { 0xA05F81F4, 0xFFFFFFFF, 0 },
193 { 0xA05F81F8, 0xFFFFFFFF, 0 },
194 { 0xA05F81FC, 0xFFFFFFFF, 0 },
195 /* SH4 control regs */
196 { 0xFF000000, 0xFFFFFFFF, 0xFFFFFCFF },
197 { 0xFF000004, 0xFFFFFFFF, 0x1FFFFDFF },
198 { 0xFF000008, 0xFFFFFFFF, 0xFFFFFFFF },
199 { 0xFF00000C, 0xFFFFFFFF, 0xFFFFFFFF },
200 { 0xFF000010, 0xFFFFFFFF, 0xFCFCFF01 },
201 { 0xFF000010, 0, 0 },
202 { 0xFF00001C, 0xFFFFFFFF, 0x000081A7 },
203 { 0xFF000020, 0xFFFFFFFF, 0x000003FC },
204 { 0xFF000024, 0xFFFFFFFF, 0x00000FFF },
205 { 0xFF000028, 0xFFFFFFFF, 0x00000FFF },
206 { 0xFF00002C, 0x7FFFFFFF, 0x00010007 },
207 { 0xFF000030, 0xFFFFFFFF, 0x040205C1 },
208 { 0xFF000030, 0, 0x040205C1 },
209 { 0xFF000034, 0xFFFFFFFF, 0x0000000F },
210 { 0xFF000038, 0xFFFFFFFF, 0x0000001C },
211 { 0xFF00003C, 0xFFFFFFFF, 0x0000001C },
212 { 0, 0, 0 } };
214 int main( int argc, char *argv[] )
215 {
216 int i;
217 int failures = 0;
218 int tests = 0;
220 ide_init();
222 for( i=0; test_cases[i].reg != 0; i++ ) {
223 unsigned int oldval = long_read( test_cases[i].reg );
224 unsigned int newval;
225 long_write( test_cases[i].reg, test_cases[i].write );
226 newval = long_read( test_cases[i].reg );
227 if( test_cases[i].expect == UNCHANGED ) {
228 if( newval != oldval ) {
229 fprintf( stderr, "Test %d (%08X) failed. Expected %08X but was %08X\n",
230 i+1, test_cases[i].reg, oldval, newval );
231 failures++;
232 }
233 } else {
234 if( newval != test_cases[i].expect ) {
235 fprintf( stderr, "Test %d (%08X) failed. Expected %08X but was %08X\n",
236 i+1, test_cases[i].reg, test_cases[i].expect, newval );
237 failures++;
238 }
239 }
240 long_write( test_cases[i].reg, oldval );
241 tests++;
242 }
244 fprintf( stdout, "%d/%d test cases passed successfully\n", (tests-failures), tests );
245 return failures;
246 }
.