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lxdream.org :: lxdream/src/sh4/sh4dasm.in
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4dasm.in
changeset 939:6f2302afeb89
prev873:cb3a8c502727
next963:1c3a0f67c603
author nkeynes
date Tue Jan 13 11:56:28 2009 +0000 (11 years ago)
permissions -rw-r--r--
last change Merge lxdream-mem branch back to trunk
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 CPU definition and disassembly functions
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    19 #include "sh4/sh4core.h"
    20 #include "sh4/sh4dasm.h"
    21 #include "mem.h"
    23 #define UNIMP(ir) snprintf( buf, len, "???     " )
    26 const struct reg_desc_struct sh4_reg_map[] = 
    27   { {"R0", REG_INT, &sh4r.r[0]}, {"R1", REG_INT, &sh4r.r[1]},
    28     {"R2", REG_INT, &sh4r.r[2]}, {"R3", REG_INT, &sh4r.r[3]},
    29     {"R4", REG_INT, &sh4r.r[4]}, {"R5", REG_INT, &sh4r.r[5]},
    30     {"R6", REG_INT, &sh4r.r[6]}, {"R7", REG_INT, &sh4r.r[7]},
    31     {"R8", REG_INT, &sh4r.r[8]}, {"R9", REG_INT, &sh4r.r[9]},
    32     {"R10",REG_INT, &sh4r.r[10]}, {"R11",REG_INT, &sh4r.r[11]},
    33     {"R12",REG_INT, &sh4r.r[12]}, {"R13",REG_INT, &sh4r.r[13]},
    34     {"R14",REG_INT, &sh4r.r[14]}, {"R15",REG_INT, &sh4r.r[15]},
    35     {"SR", REG_INT, &sh4r.sr}, {"GBR", REG_INT, &sh4r.gbr},
    36     {"SSR",REG_INT, &sh4r.ssr}, {"SPC", REG_INT, &sh4r.spc},
    37     {"SGR",REG_INT, &sh4r.sgr}, {"DBR", REG_INT, &sh4r.dbr},
    38     {"VBR",REG_INT, &sh4r.vbr},
    39     {"PC", REG_INT, &sh4r.pc}, {"PR", REG_INT, &sh4r.pr},
    40     {"MACL",REG_INT, &sh4r.mac},{"MACH",REG_INT, ((uint32_t *)&sh4r.mac)+1},
    41     {"FPUL", REG_INT, &sh4r.fpul.i}, {"FPSCR", REG_INT, &sh4r.fpscr},
    42     {NULL, 0, NULL} };
    45 const struct cpu_desc_struct sh4_cpu_desc = 
    46     { "SH4", sh4_disasm_instruction, sh4_execute_instruction, sh4_has_page, 
    47       sh4_set_breakpoint, sh4_clear_breakpoint, sh4_get_breakpoint, 2,
    48       (char *)&sh4r, sizeof(sh4r), sh4_reg_map,
    49       &sh4r.pc };
    51 uint32_t sh4_disasm_instruction( sh4vma_t pc, char *buf, int len, char *opcode )
    52 {
    53     sh4addr_t addr = mmu_vma_to_phys_disasm(pc);
    54     uint32_t tmp;
    55     uint16_t ir = ext_address_space[addr>>12]->read_word(addr);
    57 #define UNDEF(ir) snprintf( buf, len, "????    " );
    58 #define RN(ir) ((ir&0x0F00)>>8)
    59 #define RN_BANK(ir) ((ir&0x0070)>>4)
    60 #define RM(ir) ((ir&0x00F0)>>4)
    61 #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *not* sign extended */
    62 #define DISP8(ir) (ir&0x00FF)
    63 #define PCDISP8(ir) SIGNEXT8(ir&0x00FF)
    64 #define UIMM8(ir) (ir&0x00FF)
    65 #define IMM8(ir) SIGNEXT8(ir&0x00FF)
    66 #define DISP12(ir) SIGNEXT12(ir&0x0FFF)
    67 #define FVN(ir) ((ir&0x0C00)>>10)
    68 #define FVM(ir) ((ir&0x0300)>>8)
    70     sprintf( opcode, "%02X %02X", ir&0xFF, ir>>8 );
    72 %%
    73 ADD Rm, Rn       {: snprintf( buf, len, "ADD     R%d, R%d", Rm, Rn ); :}
    74 ADD #imm, Rn     {: snprintf( buf, len, "ADD     #%d, R%d", imm, Rn ); :}
    75 ADDC Rm, Rn      {: snprintf( buf, len, "ADDC    R%d, R%d", Rm, Rn ); :}
    76 ADDV Rm, Rn      {: snprintf( buf, len, "ADDV    R%d, R%d", Rm, Rn ); :}
    77 AND Rm, Rn       {: snprintf( buf, len, "AND     R%d, R%d", Rm, Rn ); :}
    78 AND #imm, R0     {: snprintf( buf, len, "AND     #%d, R0", imm ); :}
    79 AND.B #imm, @(R0, GBR) {: snprintf( buf, len, "AND.B   #%d, @(R0, GBR)", imm ); :}
    80 BF disp          {: snprintf( buf, len, "BF      $%xh", disp+pc+4 ); :}
    81 BF/S disp        {: snprintf( buf, len, "BF/S    $%xh", disp+pc+4 ); :}
    82 BRA disp         {: snprintf( buf, len, "BRA     $%xh", disp+pc+4 ); :}
    83 BRAF Rn          {: snprintf( buf, len, "BRAF    R%d", Rn ); :}
    84 BSR disp         {: snprintf( buf, len, "BSR     $%xh", disp+pc+4 ); :}
    85 BSRF Rn          {: snprintf( buf, len, "BSRF    R%d", Rn ); :}
    86 BT disp          {: snprintf( buf, len, "BT      $%xh", disp+pc+4 ); :}
    87 BT/S disp        {: snprintf( buf, len, "BT/S    $%xh", disp+pc+4 ); :}
    88 CLRMAC           {: snprintf( buf, len, "CLRMAC  " ); :}
    89 CLRS             {: snprintf( buf, len, "CLRS    " ); :}
    90 CLRT             {: snprintf( buf, len, "CLRT    " ); :}
    91 CMP/EQ Rm, Rn    {: snprintf( buf, len, "CMP/EQ  R%d, R%d", Rm, Rn ); :}
    92 CMP/EQ #imm, R0  {: snprintf( buf, len, "CMP/EQ  #%d, R0", imm ); :}
    93 CMP/GE Rm, Rn    {: snprintf( buf, len, "CMP/GE  R%d, R%d", Rm, Rn ); :}
    94 CMP/GT Rm, Rn    {: snprintf( buf, len, "CMP/GT  R%d, R%d", Rm, Rn ); :}
    95 CMP/HI Rm, Rn    {: snprintf( buf, len, "CMP/HI  R%d, R%d", Rm, Rn ); :}
    96 CMP/HS Rm, Rn    {: snprintf( buf, len, "CMP/HS  R%d, R%d", Rm, Rn ); :}
    97 CMP/PL Rn        {: snprintf( buf, len, "CMP/PL  R%d", Rn ); :}
    98 CMP/PZ Rn        {: snprintf( buf, len, "CMP/PZ  R%d", Rn ); :}
    99 CMP/STR Rm, Rn   {: snprintf( buf, len, "CMP/STR R%d, R%d", Rm, Rn ); :}
   100 DIV0S Rm, Rn     {: snprintf( buf, len, "DIV0S   R%d, R%d", Rm, Rn ); :}
   101 DIV0U            {: snprintf( buf, len, "DIV0U   " ); :}
   102 DIV1 Rm, Rn      {: snprintf( buf, len, "DIV1    R%d, R%d", Rm, Rn ); :}
   103 DMULS.L Rm, Rn   {: snprintf( buf, len, "DMULS.L R%d, R%d", Rm, Rn ); :}
   104 DMULU.L RM, Rn   {: snprintf( buf, len, "DMULU.L R%d, R%d", Rm, Rn ); :}
   105 DT Rn            {: snprintf( buf, len, "DT      R%d", Rn ); :}
   106 EXTS.B Rm, Rn    {: snprintf( buf, len, "EXTS.B  R%d, R%d", Rm, Rn ); :}
   107 EXTS.W Rm, Rn    {: snprintf( buf, len, "EXTS.W  R%d, R%d", Rm, Rn ); :}
   108 EXTU.B Rm, Rn    {: snprintf( buf, len, "EXTU.B  R%d, R%d", Rm, Rn ); :}
   109 EXTU.W Rm, Rn    {: snprintf( buf, len, "EXTU.W  R%d, R%d", Rm, Rn ); :}
   110 FABS FRn         {: snprintf( buf, len, "FABS    FR%d", FRn ); :}
   111 FADD FRm, FRn    {: snprintf( buf, len, "FADD    FR%d, FR%d", FRm, FRn ); :}
   112 FCMP/EQ FRm, FRn {: snprintf( buf, len, "FCMP/EQ FR%d, FR%d", FRm, FRn ); :}
   113 FCMP/GT FRm, FRn {: snprintf( buf, len, "FCMP/GT FR%d, FR%d", FRm, FRn ); :}
   114 FCNVDS FRm, FPUL {: snprintf( buf, len, "FCNVDS  FR%d, FPUL", FRm ); :}
   115 FCNVSD FPUL, FRn {: snprintf( buf, len, "FCNVSD  FPUL, FR%d", FRn ); :}
   116 FDIV FRm, FRn    {: snprintf( buf, len, "FDIV    FR%d, FR%d", FRm, FRn ); :}
   117 FIPR FVm, FVn    {: snprintf( buf, len, "FIPR    FV%d, FV%d", FVm, FVn ); :}
   118 FLDS FRm, FPUL   {: snprintf( buf, len, "FLDS    FR%d, FPUL", FRm ); :}
   119 FLDI0 FRn        {: snprintf( buf, len, "FLDI0   FR%d", FRn ); :}
   120 FLDI1 FRn        {: snprintf( buf, len, "FLDI1   FR%d", FRn ); :}
   121 FLOAT FPUL, FRn  {: snprintf( buf, len, "FLOAT   FPUL, FR%d", FRn ); :}
   122 FMAC FR0, FRm, FRn {: snprintf( buf, len, "FMAC    FR0, FR%d, FR%d", FRm, FRn ); :}
   123 FMOV FRm, FRn    {: snprintf( buf, len, "FMOV    FR%d, FR%d", FRm, FRn ); :}
   124 FMOV FRm, @Rn    {: snprintf( buf, len, "FMOV    FR%d, @R%d", FRm, Rn ); :}
   125 FMOV FRm, @-Rn   {: snprintf( buf, len, "FMOV    FR%d, @-R%d", FRm, Rn ); :}
   126 FMOV FRm, @(R0, Rn) {: snprintf( buf, len, "FMOV    FR%d, @(R0, R%d)", FRm, Rn ); :}
   127 FMOV @Rm, FRn    {: snprintf( buf, len, "FMOV    @R%d, FR%d", Rm, FRn ); :}
   128 FMOV @Rm+, FRn   {: snprintf( buf, len, "FMOV    @R%d+, FR%d", Rm, FRn ); :}
   129 FMOV @(R0, Rm), FRn {: snprintf( buf, len, "FMOV    @(R0, R%d), FR%d", Rm, FRn ); :}
   130 FMUL FRm, FRn    {: snprintf( buf, len, "FMUL    FR%d, FR%d", FRm, FRn ); :}
   131 FNEG FRn         {: snprintf( buf, len, "FNEG    FR%d", FRn ); :}
   132 FRCHG            {: snprintf( buf, len, "FRCHG   " ); :}
   133 FSCA FPUL, FRn   {: snprintf( buf, len, "FSCA    FPUL, FR%d", FRn ); :}
   134 FSCHG            {: snprintf( buf, len, "FSCHG   " ); :}
   135 FSQRT FRn        {: snprintf( buf, len, "FSQRT   FR%d", FRn ); :}
   136 FSRRA FRn        {: snprintf( buf, len, "FSRRA   FR%d", FRn ); :}
   137 FSTS FPUL, FRn   {: snprintf( buf, len, "FSTS    FPUL, FR%d", FRn ); :}
   138 FSUB FRm, FRn    {: snprintf( buf, len, "FSUB    FR%d, FR%d", FRm, FRn ); :}
   139 FTRC FRm, FPUL   {: snprintf( buf, len, "FTRC    FR%d, FPUL", FRm ); :}
   140 FTRV XMTRX, FVn  {: snprintf( buf, len, "FTRV    XMTRX, FV%d", FVn ); :}
   141 JMP @Rn          {: snprintf( buf, len, "JMP     @R%d", Rn ); :}
   142 JSR @Rn          {: snprintf( buf, len, "JSR     @R%d", Rn ); :}
   143 LDC Rm, GBR      {: snprintf( buf, len, "LDC     R%d, GBR", Rm ); :}
   144 LDC Rm, SR       {: snprintf( buf, len, "LDC     R%d, SR", Rm ); :}
   145 LDC Rm, VBR      {: snprintf( buf, len, "LDC     R%d, VBR", Rm ); :}
   146 LDC Rm, SSR      {: snprintf( buf, len, "LDC     R%d, SSR", Rm ); :}
   147 LDC Rm, SGR      {: snprintf( buf, len, "LDC     R%d, SGR", Rm ); :}
   148 LDC Rm, SPC      {: snprintf( buf, len, "LDC     R%d, SPC", Rm ); :}
   149 LDC Rm, DBR      {: snprintf( buf, len, "LDC     R%d, DBR", Rm ); :}
   150 LDC Rm, Rn_BANK  {: snprintf( buf, len, "LDC     R%d, R%d_BANK", Rm, Rn_BANK ); :}
   151 LDS Rm, FPSCR    {: snprintf( buf, len, "LDS     R%d, FPSCR", Rm ); :}
   152 LDS Rm, FPUL     {: snprintf( buf, len, "LDS     R%d, FPUL", Rm ); :}
   153 LDS Rm, MACH     {: snprintf( buf, len, "LDS     R%d, MACH", Rm ); :}
   154 LDS Rm, MACL     {: snprintf( buf, len, "LDS     R%d, MACL", Rm ); :}
   155 LDS Rm, PR       {: snprintf( buf, len, "LDS     R%d, PR", Rm ); :}
   156 LDC.L @Rm+, GBR  {: snprintf( buf, len, "LDC.L   @R%d+, GBR", Rm ); :}
   157 LDC.L @Rm+, SR   {: snprintf( buf, len, "LDC.L   @R%d+, SR", Rm ); :}
   158 LDC.L @Rm+, VBR  {: snprintf( buf, len, "LDC.L   @R%d+, VBR", Rm ); :}
   159 LDC.L @Rm+, SSR  {: snprintf( buf, len, "LDC.L   @R%d+, SSR", Rm ); :}
   160 LDC.L @Rm+, SGR  {: snprintf( buf, len, "LDC.L   @R%d+, SGR", Rm ); :}
   161 LDC.L @Rm+, SPC  {: snprintf( buf, len, "LDC.L   @R%d+, SPC", Rm ); :}
   162 LDC.L @Rm+, DBR  {: snprintf( buf, len, "LDC.L   @R%d+, DBR", Rm ); :}
   163 LDC.L @Rm+, Rn_BANK{: snprintf( buf, len, "LDC.L   @R%d+, @R%d+_BANK", Rm, Rn_BANK ); :}
   164 LDS.L @Rm+, FPSCR{: snprintf( buf, len, "LDS.L   @R%d+, FPSCR", Rm ); :}
   165 LDS.L @Rm+, FPUL {: snprintf( buf, len, "LDS.L   @R%d+, FPUL", Rm ); :}
   166 LDS.L @Rm+, MACH {: snprintf( buf, len, "LDS.L   @R%d+, MACH", Rm ); :}
   167 LDS.L @Rm+, MACL {: snprintf( buf, len, "LDS.L   @R%d+, MACL", Rm ); :}
   168 LDS.L @Rm+, PR   {: snprintf( buf, len, "LDS.L   @R%d+, PR", Rm ); :}
   169 LDTLB            {: snprintf( buf, len, "LDTLB   " ); :}
   170 MAC.L @Rm+, @Rn+ {: snprintf( buf, len, "MAC.L   @R%d+, @R%d+", Rm, Rn ); :}
   171 MAC.W @Rm+, @Rn+ {: snprintf( buf, len, "MAC.W   @R%d+, @R%d+", Rm, Rn ); :}
   172 MOV Rm, Rn       {: snprintf( buf, len, "MOV     R%d, R%d", Rm, Rn ); :}
   173 MOV #imm, Rn     {: snprintf( buf, len, "MOV     #%d, R%d", imm, Rn ); :}
   174 MOV.B Rm, @Rn    {: snprintf( buf, len, "MOV.B   R%d, @R%d", Rm, Rn ); :}
   175 MOV.B Rm, @-Rn   {: snprintf( buf, len, "MOV.B   R%d, @-R%d", Rm, Rn ); :}
   176 MOV.B Rm, @(R0, Rn) {: snprintf( buf, len, "MOV.B   R%d, @(R0, R%d)", Rm, Rn ); :}
   177 MOV.B R0, @(disp, GBR) {: snprintf( buf, len, "MOV.B   R0, @(%d, GBR)", disp ); :}
   178 MOV.B R0, @(disp, Rn)  {: snprintf( buf, len, "MOV.B   R0, @(%d, R%d)", disp, Rn ); :}
   179 MOV.B @Rm, Rn    {: snprintf( buf, len, "MOV.B   @R%d, R%d", Rm, Rn ); :}
   180 MOV.B @Rm+, Rn   {: snprintf( buf, len, "MOV.B   @R%d+, R%d", Rm, Rn ); :}
   181 MOV.B @(R0, Rm), Rn {: snprintf( buf, len, "MOV.B   @(R0, R%d), R%d", Rm, Rn ); :}
   182 MOV.B @(disp, GBR), R0{: snprintf( buf, len, "MOV.B   @(%d, GBR), R0", disp ); :}
   183 MOV.B @(disp, Rm), R0 {: snprintf( buf, len, "MOV.B   @(%d, R%d), R0", disp, Rm ); :}
   184 MOV.L Rm, @Rn    {: snprintf( buf, len, "MOV.L   R%d, @R%d", Rm, Rn ); :}
   185 MOV.L Rm, @-Rn   {: snprintf( buf, len, "MOV.L   R%d, @-R%d", Rm, Rn ); :}
   186 MOV.L Rm, @(R0, Rn) {: snprintf( buf, len, "MOV.L   R%d, @(R0, R%d)", Rm, Rn ); :}
   187 MOV.L R0, @(disp, GBR) {: snprintf( buf, len, "MOV.L   R0, @(%d, GBR)", disp ); :}
   188 MOV.L Rm, @(disp, Rn) {: snprintf( buf, len, "MOV.L   R%d, @(%d, R%d)", Rm, disp, Rn ); :}
   189 MOV.L @Rm, Rn    {: snprintf( buf, len, "MOV.L   @R%d, R%d", Rm, Rn ); :}
   190 MOV.L @Rm+, Rn   {: snprintf( buf, len, "MOV.L   @R%d+, R%d", Rm, Rn ); :}
   191 MOV.L @(R0, Rm), Rn {: snprintf( buf, len, "MOV.L   @(R0, R%d), R%d", Rm, Rn ); :}
   192 MOV.L @(disp, GBR), R0 {: snprintf( buf, len, "MOV.L   @(%d, GBR), R0",disp ); :}
   193 MOV.L @(disp, PC), Rn  {:
   194     tmp = mmu_vma_to_phys_disasm(disp + (pc&0xFFFFFFFC) + 4); 
   195     snprintf( buf, len, "MOV.L   @($%xh), R%d ; <- #%08x", disp + (pc&0xFFFFFFFC)+4, Rn, ext_address_space[tmp>>12]->read_long(tmp) );
   196 :}
   197 MOV.L @(disp, Rm), Rn  {: snprintf( buf, len, "MOV.L   @(%d, R%d), R%d", disp, Rm, Rn ); :}
   198 MOV.W Rm, @Rn    {: snprintf( buf, len, "MOV.W   R%d, @R%d", Rm, Rn ); :}
   199 MOV.W Rm, @-Rn   {: snprintf( buf, len, "MOV.W   R%d, @-R%d", Rm, Rn ); :}
   200 MOV.W Rm, @(R0, Rn) {: snprintf( buf, len, "MOV.W   R%d, @(R0, R%d)", Rm, Rn ); :}
   201 MOV.W R0, @(disp, GBR) {: snprintf( buf, len, "MOV.W   R0, @(%d, GBR)", disp); :}
   202 MOV.W R0, @(disp, Rn)  {: snprintf( buf, len, "MOV.W   R0, @(%d, R%d)", disp, Rn ); :}
   203 MOV.W @Rm, Rn    {: snprintf( buf, len, "MOV.W   @R%d, R%d", Rm, Rn ); :}
   204 MOV.W @Rm+, Rn   {: snprintf( buf, len, "MOV.W   @R%d+, R%d", Rm, Rn ); :}
   205 MOV.W @(R0, Rm), Rn {: snprintf( buf, len, "MOV.W   @(R0, R%d), R%d", Rm, Rn ); :}
   206 MOV.W @(disp, GBR), R0 {: snprintf( buf, len, "MOV.W   @(%d, GBR), R0", disp ); :}
   207 MOV.W @(disp, PC), Rn  {:
   208     tmp = mmu_vma_to_phys_disasm(disp+pc+4);
   209     snprintf( buf, len, "MOV.W   @($%xh), R%d ; <- #%08x", disp+pc+4, Rn, ext_address_space[tmp>>12]->read_word(tmp) );
   210 :}
   211 MOV.W @(disp, Rm), R0  {: snprintf( buf, len, "MOV.W   @(%d, R%d), R0", disp, Rm ); :}
   212 MOVA @(disp, PC), R0   {: snprintf( buf, len, "MOVA    @($%xh), R0", disp + (pc&0xFFFFFFFC) + 4 ); :}
   213 MOVCA.L R0, @Rn  {: snprintf( buf, len, "MOVCA.L R0, @R%d", Rn ); :}
   214 MOVT Rn          {: snprintf( buf, len, "MOVT    R%d", Rn ); :}
   215 MUL.L Rm, Rn     {: snprintf( buf, len, "MUL.L   R%d, R%d", Rm, Rn ); :}
   216 MULS.W Rm, Rn    {: snprintf( buf, len, "MULS.W  R%d, R%d", Rm, Rn ); :}
   217 MULU.W Rm, Rn    {: snprintf( buf, len, "MULU.W  R%d, R%d", Rm, Rn ); :}
   218 NEG Rm, Rn       {: snprintf( buf, len, "NEG     R%d, R%d", Rm, Rn ); :}
   219 NEGC Rm, Rn      {: snprintf( buf, len, "NEGC    R%d, R%d", Rm, Rn ); :}
   220 NOP              {: snprintf( buf, len, "NOP     " ); :}
   221 NOT Rm, Rn       {: snprintf( buf, len, "NOT     R%d, R%d", Rm, Rn ); :}
   222 OCBI @Rn         {: snprintf( buf, len, "OCBI    @R%d", Rn ); :}
   223 OCBP @Rn         {: snprintf( buf, len, "OCBP    @R%d", Rn ); :}
   224 OCBWB @Rn        {: snprintf( buf, len, "OCBWB   @R%d", Rn ); :}
   225 OR Rm, Rn        {: snprintf( buf, len, "OR      R%d, R%d", Rm, Rn ); :}
   226 OR #imm, R0      {: snprintf( buf, len, "OR      #%d, R0", imm ); :}
   227 OR.B #imm, @(R0, GBR) {: snprintf( buf, len, "OR.B    #%d, @(R0, GBR)", imm ); :}
   228 PREF @Rn         {: snprintf( buf, len, "PREF    R%d", Rn ); :}
   229 ROTCL Rn         {: snprintf( buf, len, "ROTCL   R%d", Rn ); :}
   230 ROTCR Rn         {: snprintf( buf, len, "ROTCR   R%d", Rn ); :}
   231 ROTL Rn          {: snprintf( buf, len, "ROTL    R%d", Rn ); :}
   232 ROTR Rn          {: snprintf( buf, len, "ROTR    R%d", Rn ); :}
   233 RTE              {: snprintf( buf, len, "RTE     " ); :}
   234 RTS              {: snprintf( buf, len, "RTS     " ); :}
   235 SETS             {: snprintf( buf, len, "SETS    " ); :}
   236 SETT             {: snprintf( buf, len, "SETT    " ); :}
   237 SHAD Rm, Rn      {: snprintf( buf, len, "SHAD    R%d, R%d", Rm, Rn ); :}
   238 SHAL Rn          {: snprintf( buf, len, "SHAL    R%d", Rn ); :}
   239 SHAR Rn          {: snprintf( buf, len, "SHAR    R%d", Rn ); :}
   240 SHLD Rm, Rn      {: snprintf( buf, len, "SHLD    R%d, R%d", Rm, Rn ); :}
   241 SHLL Rn          {: snprintf( buf, len, "SHLL    R%d", Rn ); :}
   242 SHLL2 Rn         {: snprintf( buf, len, "SHLL2   R%d", Rn ); :}
   243 SHLL8 Rn         {: snprintf( buf, len, "SHLL8   R%d", Rn ); :}
   244 SHLL16 Rn        {: snprintf( buf, len, "SHLL16  R%d", Rn ); :}
   245 SHLR Rn          {: snprintf( buf, len, "SHLR    R%d", Rn ); :}
   246 SHLR2 Rn         {: snprintf( buf, len, "SHLR2   R%d", Rn ); :}
   247 SHLR8 Rn         {: snprintf( buf, len, "SHLR8   R%d", Rn ); :}
   248 SHLR16 Rn        {: snprintf( buf, len, "SHLR16  R%d", Rn ); :}
   249 SLEEP            {: snprintf( buf, len, "SLEEP   " ); :}
   250 STC SR, Rn       {: snprintf( buf, len, "STC     SR, R%d", Rn ); :}
   251 STC GBR, Rn      {: snprintf( buf, len, "STC     GBR, R%d", Rn ); :}
   252 STC VBR, Rn      {: snprintf( buf, len, "STC     VBR, R%d", Rn ); :}
   253 STC SSR, Rn      {: snprintf( buf, len, "STC     SSR, R%d", Rn ); :}
   254 STC SPC, Rn      {: snprintf( buf, len, "STC     SPC, R%d", Rn ); :}
   255 STC SGR, Rn      {: snprintf( buf, len, "STC     SGR, R%d", Rn ); :}
   256 STC DBR, Rn      {: snprintf( buf, len, "STC     DBR, R%d", Rn ); :}
   257 STC Rm_BANK, Rn  {: snprintf( buf, len, "STC     R%d_BANK, R%d", Rm_BANK, Rn ); :}
   258 STS FPSCR, Rn    {: snprintf( buf, len, "STS     FPSCR, R%d", Rn ); :}
   259 STS FPUL, Rn     {: snprintf( buf, len, "STS     FPUL, R%d", Rn ); :}
   260 STS MACH, Rn     {: snprintf( buf, len, "STS     MACH, R%d", Rn ); :}
   261 STS MACL, Rn     {: snprintf( buf, len, "STS     MACL, R%d", Rn ); :}
   262 STS PR, Rn       {: snprintf( buf, len, "STS     PR, R%d", Rn ); :}
   263 STC.L SR, @-Rn   {: snprintf( buf, len, "STC.L   SR, @-R%d", Rn ); :}
   264 STC.L GBR, @-Rn  {: snprintf( buf, len, "STC.L   GBR, @-R%d", Rn ); :}
   265 STC.L VBR, @-Rn  {: snprintf( buf, len, "STC.L   VBR, @-R%d", Rn ); :}
   266 STC.L SSR, @-Rn  {: snprintf( buf, len, "STC.L   SSR, @-R%d", Rn ); :}
   267 STC.L SPC, @-Rn  {: snprintf( buf, len, "STC.L   SPC, @-R%d", Rn ); :}
   268 STC.L SGR, @-Rn  {: snprintf( buf, len, "STC.L   SGR, @-R%d", Rn ); :}
   269 STC.L DBR, @-Rn  {: snprintf( buf, len, "STC.L    DBR, @-R%d", Rn ); :}
   270 STC.L Rm_BANK, @-Rn {: snprintf( buf, len, "STC.L   @-R%d_BANK, @-R%d", Rm_BANK, Rn ); :}
   271 STS.L FPSCR, @-Rn{: snprintf( buf, len, "STS.L   FPSCR, @-R%d", Rn ); :}
   272 STS.L FPUL, @-Rn {: snprintf( buf, len, "STS.L   FPUL, @-R%d", Rn ); :}
   273 STS.L MACH, @-Rn {: snprintf( buf, len, "STS.L   MACH, @-R%d", Rn ); :}
   274 STS.L MACL, @-Rn {: snprintf( buf, len, "STS.L   MACL, @-R%d", Rn ); :}
   275 STS.L PR, @-Rn   {: snprintf( buf, len, "STS.L   PR, @-R%d", Rn ); :}
   276 SUB Rm, Rn       {: snprintf( buf, len, "SUB     R%d, R%d", Rm, Rn ); :}
   277 SUBC Rm, Rn      {: snprintf( buf, len, "SUBC    R%d, R%d", Rm, Rn ); :}
   278 SUBV Rm, Rn      {: snprintf( buf, len, "SUBV    R%d, R%d", Rm, Rn ); :}
   279 SWAP.B Rm, Rn    {: snprintf( buf, len, "SWAP.B  R%d, R%d", Rm, Rn ); :}
   280 SWAP.W Rm, Rn    {: snprintf( buf, len, "SWAP.W  R%d, R%d", Rm, Rn ); :}
   281 TAS.B @Rn        {: snprintf( buf, len, "TAS.B   R%d", Rn ); :}
   282 TRAPA #imm       {: snprintf( buf, len, "TRAPA   #%d", imm ); :}
   283 TST Rm, Rn       {: snprintf( buf, len, "TST     R%d, R%d", Rm, Rn ); :}
   284 TST #imm, R0     {: snprintf( buf, len, "TST     #%d, R0", imm ); :}
   285 TST.B #imm, @(R0, GBR) {: snprintf( buf, len, "TST.B   #%d, @(R0, GBR)", imm ); :}
   286 XOR Rm, Rn       {: snprintf( buf, len, "XOR     R%d, R%d", Rm, Rn ); :}
   287 XOR #imm, R0     {: snprintf( buf, len, "XOR     #%d, R0", imm ); :}
   288 XOR.B #imm, @(R0, GBR) {: snprintf( buf, len, "XOR.B   #%d, @(R0, GBR)", imm ); :}
   289 XTRCT Rm, Rn     {: snprintf( buf, len, "XTRCT   R%d, R%d", Rm, Rn ); :}
   290 UNDEF            {: snprintf( buf, len, "UNDEF   " ); :}
   291 %%
   292     return pc+2;
   293 }
   296 void sh4_disasm_region( FILE *f, int from, int to )
   297 {
   298     int pc;
   299     char buf[80];
   300     char opcode[16];
   302     for( pc = from; pc < to; pc+=2 ) {
   303         buf[0] = '\0';
   304         sh4_disasm_instruction( pc,
   305                                 buf, sizeof(buf), opcode );
   306         fprintf( f, "  %08x:  %s  %s\n", pc, opcode, buf );
   307     }
   308 }
   310 void sh4_dump_region( int from, int to )
   311 {
   312     sh4_disasm_region( stdout, from, to );
   313 }
.