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lxdream.org :: lxdream/src/pvr2/pvr2.c
lxdream 0.9.1
released Jun 29
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filename src/pvr2/pvr2.c
changeset 197:f65ff8c8320d
prev193:31151fcc3cb7
next214:7a6501b74fbc
author nkeynes
date Sun Aug 06 02:47:08 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add masks on all PVR2 registers
Add missing registers and rename display registers for consistency
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     1 /**
     2  * $Id: pvr2.c,v 1.31 2006-08-06 02:47:08 nkeynes Exp $
     3  *
     4  * PVR2 (Video) Core module implementation and MMIO registers.
     5  *
     6  * Copyright (c) 2005 Nathan Keynes.
     7  *
     8  * This program is free software; you can redistribute it and/or modify
     9  * it under the terms of the GNU General Public License as published by
    10  * the Free Software Foundation; either version 2 of the License, or
    11  * (at your option) any later version.
    12  *
    13  * This program is distributed in the hope that it will be useful,
    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16  * GNU General Public License for more details.
    17  */
    18 #define MODULE pvr2_module
    20 #include "dream.h"
    21 #include "display.h"
    22 #include "mem.h"
    23 #include "asic.h"
    24 #include "pvr2/pvr2.h"
    25 #include "sh4/sh4core.h"
    26 #define MMIO_IMPL
    27 #include "pvr2/pvr2mmio.h"
    29 char *video_base;
    31 static void pvr2_init( void );
    32 static void pvr2_reset( void );
    33 static uint32_t pvr2_run_slice( uint32_t );
    34 static void pvr2_save_state( FILE *f );
    35 static int pvr2_load_state( FILE *f );
    37 void pvr2_display_frame( void );
    39 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
    41 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, 
    42 					pvr2_run_slice, NULL,
    43 					pvr2_save_state, pvr2_load_state };
    46 display_driver_t display_driver = NULL;
    48 struct video_timing {
    49     int fields_per_second;
    50     int total_lines;
    51     int retrace_lines;
    52     int line_time_ns;
    53 };
    55 struct video_timing pal_timing = { 50, 625, 65, 32000 };
    56 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
    58 struct pvr2_state {
    59     uint32_t frame_count;
    60     uint32_t line_count;
    61     uint32_t line_remainder;
    62     uint32_t irq_vpos1;
    63     uint32_t irq_vpos2;
    64     gboolean retrace;
    65     struct video_timing timing;
    66 } pvr2_state;
    68 struct video_buffer video_buffer[2];
    69 int video_buffer_idx = 0;
    71 static void pvr2_init( void )
    72 {
    73     register_io_region( &mmio_region_PVR2 );
    74     register_io_region( &mmio_region_PVR2PAL );
    75     register_io_region( &mmio_region_PVR2TA );
    76     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
    77     texcache_init();
    78     pvr2_reset();
    79 }
    81 static void pvr2_reset( void )
    82 {
    83     pvr2_state.line_count = 0;
    84     pvr2_state.line_remainder = 0;
    85     pvr2_state.irq_vpos1 = 0;
    86     pvr2_state.irq_vpos2 = 0;
    87     pvr2_state.retrace = FALSE;
    88     pvr2_state.timing = ntsc_timing;
    89     video_buffer_idx = 0;
    91     pvr2_ta_init();
    92     pvr2_render_init();
    93     texcache_flush();
    94 }
    96 static void pvr2_save_state( FILE *f )
    97 {
    98     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
    99     pvr2_ta_save_state( f );
   100 }
   102 static int pvr2_load_state( FILE *f )
   103 {
   104     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
   105 	return 1;
   106     return pvr2_ta_load_state(f);
   107 }
   109 static uint32_t pvr2_run_slice( uint32_t nanosecs ) 
   110 {
   111     pvr2_state.line_remainder += nanosecs;
   112     while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
   113 	pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
   115 	pvr2_state.line_count++;
   116 	if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
   117 	    asic_event( EVENT_RETRACE );
   118 	    pvr2_state.line_count = 0;
   119 	    pvr2_state.retrace = TRUE;
   120 	}
   122 	if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
   123 	    asic_event( EVENT_SCANLINE1 );
   124 	} 
   125 	if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
   126 	    asic_event( EVENT_SCANLINE2 );
   127 	}
   129 	if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
   130 	    if( pvr2_state.retrace ) {
   131 		pvr2_display_frame();
   132 		pvr2_state.retrace = FALSE;
   133 	    }
   134 	}
   135     }
   136     return nanosecs;
   137 }
   139 int pvr2_get_frame_count() 
   140 {
   141     return pvr2_state.frame_count;
   142 }
   144 /**
   145  * Display the next frame, copying the current contents of video ram to
   146  * the window. If the video configuration has changed, first recompute the
   147  * new frame size/depth.
   148  */
   149 void pvr2_display_frame( void )
   150 {
   151     uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
   153     int dispsize = MMIO_READ( PVR2, DISP_SIZE );
   154     int dispmode = MMIO_READ( PVR2, DISP_MODE );
   155     int vidcfg = MMIO_READ( PVR2, DISP_CFG );
   156     int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
   157     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
   158     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
   159     gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
   160     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
   161     video_buffer_t buffer = &video_buffer[video_buffer_idx];
   162     video_buffer_idx = !video_buffer_idx;
   163     video_buffer_t last = &video_buffer[video_buffer_idx];
   164     buffer->rowstride = (vid_ppl + vid_stride) << 2;
   165     buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
   166     buffer->vres = vid_lpf;
   167     if( interlaced ) buffer->vres <<= 1;
   168     switch( (dispmode & DISPMODE_COL) >> 2 ) {
   169     case 0: 
   170 	buffer->colour_format = COLFMT_ARGB1555;
   171 	buffer->hres = vid_ppl << 1; 
   172 	break;
   173     case 1: 
   174 	buffer->colour_format = COLFMT_RGB565;
   175 	buffer->hres = vid_ppl << 1; 
   176 	break;
   177     case 2:
   178 	buffer->colour_format = COLFMT_RGB888;
   179 	buffer->hres = (vid_ppl << 2) / 3; 
   180 	break;
   181     case 3: 
   182 	buffer->colour_format = COLFMT_ARGB8888;
   183 	buffer->hres = vid_ppl; 
   184 	break;
   185     }
   187     if( buffer->hres <=8 )
   188 	buffer->hres = 640;
   189     if( buffer->vres <=8 )
   190 	buffer->vres = 480;
   191     if( display_driver != NULL ) {
   192 	if( buffer->hres != last->hres ||
   193 	    buffer->vres != last->vres ||
   194 	    buffer->colour_format != last->colour_format) {
   195 	    display_driver->set_display_format( buffer->hres, buffer->vres,
   196 						buffer->colour_format );
   197 	}
   198 	if( !bEnabled ) {
   199 	    display_driver->display_blank_frame( 0 );
   200 	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
   201 	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
   202 	    display_driver->display_blank_frame( colour );
   203 	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
   204 	    display_driver->display_frame( buffer );
   205 	}
   206     }
   207     pvr2_state.frame_count++;
   208 }
   210 /**
   211  * This has to handle every single register individually as they all get masked 
   212  * off differently (and its easier to do it at write time)
   213  */
   214 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
   215 {
   216     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
   217         MMIO_WRITE( PVR2, reg, val );
   218         return;
   219     }
   221     switch(reg) {
   222     case PVRID:
   223     case PVRVER:
   224     case GUNPOS:
   225     case TA_POLYPOS:
   226     case TA_LISTPOS:
   227 	/* Readonly registers */
   228 	break;
   229     case PVRRESET:
   230 	val &= 0x00000007; /* Do stuff? */
   231 	MMIO_WRITE( PVR2, reg, val );
   232 	break;
   233     case RENDER_START:
   234 	if( val == 0xFFFFFFFF )
   235 	    pvr2_render_scene();
   236 	break;
   237     case PVRUNK1:
   238     	MMIO_WRITE( PVR2, reg, val&0x000007FF );
   239     	break;
   240     case RENDER_POLYBASE:
   241     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );
   242     	break;
   243     case RENDER_TSPCFG:
   244     	MMIO_WRITE( PVR2, reg, val&0x00010101 );
   245     	break;
   246     case DISP_BORDER:
   247     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
   248     	break;
   249     case DISP_MODE:
   250     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
   251     	break;
   252     case RENDER_MODE:
   253     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
   254     	break;
   255     case RENDER_SIZE:
   256     	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   257     	break;
   258     case DISP_ADDR1:
   259 	val &= 0x00FFFFFC;
   260 	MMIO_WRITE( PVR2, reg, val );
   261 	if( pvr2_state.retrace ) {
   262 	    pvr2_display_frame();
   263 	    pvr2_state.retrace = FALSE;
   264 	}
   265 	break;
   266     case DISP_ADDR2:
   267     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   268     	break;
   269     case DISP_SIZE:
   270     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
   271     	break;
   272     case RENDER_ADDR1:
   273     case RENDER_ADDR2:
   274     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
   275     	break;
   276     case RENDER_HCLIP:
   277 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
   278 	break;
   279     case RENDER_VCLIP:
   280 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   281 	break;
   282     case DISP_HPOSIRQ:
   283 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
   284 	break;
   285     case DISP_VPOSIRQ:
   286 	val = val & 0x03FF03FF;
   287 	pvr2_state.irq_vpos1 = (val >> 16);
   288 	pvr2_state.irq_vpos2 = val & 0x03FF;
   289 	MMIO_WRITE( PVR2, reg, val );
   290 	break;
   291     case RENDER_NEARCLIP:
   292 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
   293 	break;
   294     case RENDER_SHADOW:
   295 	MMIO_WRITE( PVR2, reg, val&0x000001FF );
   296 	break;
   297     case RENDER_OBJCFG:
   298     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   299     	break;
   300     case PVRUNK2:
   301 	MMIO_WRITE( PVR2, reg, val&0x00000007 );
   302 	break;
   303     case RENDER_TSPCLIP:
   304     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
   305     	break;
   306     case RENDER_FARCLIP:
   307 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
   308 	break;
   309     case RENDER_BGPLANE:
   310     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   311     	break;
   312     case RENDER_ISPCFG:
   313     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
   314     	break;
   315     case VRAM_CFG1:
   316 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   317 	break;
   318     case VRAM_CFG2:
   319 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
   320 	break;
   321     case VRAM_CFG3:
   322 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
   323 	break;
   324     case RENDER_FOGTBLCOL:
   325     case RENDER_FOGVRTCOL:
   326 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
   327 	break;
   328     case RENDER_FOGCOEFF:
   329 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   330 	break;
   331     case RENDER_CLAMPHI:
   332     case RENDER_CLAMPLO:
   333 	MMIO_WRITE( PVR2, reg, val );
   334 	break;
   335     case DISP_CFG:
   336 	MMIO_WRITE( PVR2, reg, val&0x000003FF );
   337 	break;
   338     case DISP_HBORDER:
   339     case DISP_SYNC:
   340     case DISP_VBORDER:
   341 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   342 	break;
   343     case DISP_SYNC2:
   344 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
   345 	break;
   346     case RENDER_TEXSIZE:
   347 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );
   348 	break;
   349     case DISP_CFG2:
   350 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );
   351 	break;
   352     case DISP_HPOS:
   353 	MMIO_WRITE( PVR2, reg, val&0x000003FF );
   354 	break;
   355     case DISP_VPOS:
   356 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
   357 	break;
   358     case SCALERCFG:
   359 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
   360 	break;
   361     case RENDER_PALETTE:
   362 	MMIO_WRITE( PVR2, reg, val&0x00000003 );
   363 	break;
   364     case PVRUNK3:
   365 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
   366 	break;
   367     case PVRUNK5:
   368 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
   369 	break;
   370     case PVRUNK6:
   371 	MMIO_WRITE( PVR2, reg, val&0x000000FF );
   372 	break;
   373     case TA_TILEBASE:
   374     case TA_LISTEND:
   375     case TA_LISTBASE:
   376 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
   377 	break;
   378     case RENDER_TILEBASE:
   379     case TA_POLYBASE:
   380     case TA_POLYEND:
   381 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
   382 	break;
   383     case TA_TILESIZE:
   384 	MMIO_WRITE( PVR2, reg, val&0x000F003F );
   385 	break;
   386     case TA_TILECFG:
   387 	MMIO_WRITE( PVR2, reg, val&0x00133333 );
   388 	break;
   389     case YUV_ADDR:
   390 	MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 );
   391 	break;
   392     case YUV_CFG:
   393 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );
   394 	break;
   395     case TA_INIT:
   396 	if( val & 0x80000000 )
   397 	    pvr2_ta_init();
   398 	break;
   399     case TA_REINIT:
   400 	break;
   401     case PVRUNK7:
   402 	MMIO_WRITE( PVR2, reg, val&0x00000001 );
   403 	break;
   404     }
   405 }
   407 MMIO_REGION_READ_FN( PVR2, reg )
   408 {
   409     switch( reg ) {
   410         case DISP_BEAMPOS:
   411             return sh4r.icount&0x20 ? 0x2000 : 1;
   412         default:
   413             return MMIO_READ( PVR2, reg );
   414     }
   415 }
   417 MMIO_REGION_DEFFNS( PVR2PAL )
   419 void pvr2_set_base_address( uint32_t base ) 
   420 {
   421     mmio_region_PVR2_write( DISP_ADDR1, base );
   422 }
   427 int32_t mmio_region_PVR2TA_read( uint32_t reg )
   428 {
   429     return 0xFFFFFFFF;
   430 }
   432 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
   433 {
   434     pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
   435 }
   438 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
   439 {
   440     int bank_flag = (destaddr & 0x04) >> 2;
   441     uint32_t *banks[2];
   442     uint32_t *dwsrc;
   443     int i;
   445     destaddr = destaddr & 0x7FFFFF;
   446     if( destaddr + length > 0x800000 ) {
   447 	length = 0x800000 - destaddr;
   448     }
   450     for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
   451 	texcache_invalidate_page( i );
   452     }
   454     banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
   455     banks[1] = banks[0] + 0x100000;
   456     if( bank_flag ) 
   457 	banks[0]++;
   459     /* Handle non-aligned start of source */
   460     if( destaddr & 0x03 ) {
   461 	char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
   462 	for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   463 	    *dest++ = *src++;
   464 	}
   465 	bank_flag = !bank_flag;
   466     }
   468     dwsrc = (uint32_t *)src;
   469     while( length >= 4 ) {
   470 	*banks[bank_flag]++ = *dwsrc++;
   471 	bank_flag = !bank_flag;
   472 	length -= 4;
   473     }
   475     /* Handle non-aligned end of source */
   476     if( length ) {
   477 	src = (char *)dwsrc;
   478 	char *dest = (char *)banks[bank_flag];
   479 	while( length-- > 0 ) {
   480 	    *dest++ = *src++;
   481 	}
   482     }  
   484 }
   486 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
   487 {
   488     int bank_flag = (srcaddr & 0x04) >> 2;
   489     uint32_t *banks[2];
   490     uint32_t *dwdest;
   491     int i;
   493     srcaddr = srcaddr & 0x7FFFFF;
   494     if( srcaddr + length > 0x800000 )
   495 	length = 0x800000 - srcaddr;
   497     banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
   498     banks[1] = banks[0] + 0x100000;
   499     if( bank_flag )
   500 	banks[0]++;
   502     /* Handle non-aligned start of source */
   503     if( srcaddr & 0x03 ) {
   504 	char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
   505 	for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
   506 	    *dest++ = *src++;
   507 	}
   508 	bank_flag = !bank_flag;
   509     }
   511     dwdest = (uint32_t *)dest;
   512     while( length >= 4 ) {
   513 	*dwdest++ = *banks[bank_flag]++;
   514 	bank_flag = !bank_flag;
   515 	length -= 4;
   516     }
   518     /* Handle non-aligned end of source */
   519     if( length ) {
   520 	dest = (char *)dwdest;
   521 	char *src = (char *)banks[bank_flag];
   522 	while( length-- > 0 ) {
   523 	    *dest++ = *src++;
   524 	}
   525     }
   526 }
   528 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) 
   529 {
   530     char tmp[length];
   531     pvr2_vram64_read( tmp, addr, length );
   532     fwrite_dump( tmp, length, f );
   533 }
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