2 * $Id: pvr2.c,v 1.33 2006-08-29 08:11:56 nkeynes Exp $
4 * PVR2 (Video) Core module implementation and MMIO registers.
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #define MODULE pvr2_module
24 #include "pvr2/pvr2.h"
25 #include "sh4/sh4core.h"
27 #include "pvr2/pvr2mmio.h"
31 static void pvr2_init( void );
32 static void pvr2_reset( void );
33 static uint32_t pvr2_run_slice( uint32_t );
34 static void pvr2_save_state( FILE *f );
35 static int pvr2_load_state( FILE *f );
37 void pvr2_display_frame( void );
39 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };
41 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
43 pvr2_save_state, pvr2_load_state };
46 display_driver_t display_driver = NULL;
49 int fields_per_second;
55 struct video_timing pal_timing = { 50, 625, 65, 32000 };
56 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };
61 uint32_t line_remainder;
65 struct video_timing timing;
68 struct video_buffer video_buffer[2];
69 int video_buffer_idx = 0;
71 static void pvr2_init( void )
73 register_io_region( &mmio_region_PVR2 );
74 register_io_region( &mmio_region_PVR2PAL );
75 register_io_region( &mmio_region_PVR2TA );
76 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
82 static void pvr2_reset( void )
84 pvr2_state.line_count = 0;
85 pvr2_state.line_remainder = 0;
86 pvr2_state.irq_vpos1 = 0;
87 pvr2_state.irq_vpos2 = 0;
88 pvr2_state.retrace = FALSE;
89 pvr2_state.timing = ntsc_timing;
97 static void pvr2_save_state( FILE *f )
99 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
100 pvr2_ta_save_state( f );
103 static int pvr2_load_state( FILE *f )
105 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
107 return pvr2_ta_load_state(f);
110 static uint32_t pvr2_run_slice( uint32_t nanosecs )
112 pvr2_state.line_remainder += nanosecs;
113 while( pvr2_state.line_remainder >= pvr2_state.timing.line_time_ns ) {
114 pvr2_state.line_remainder -= pvr2_state.timing.line_time_ns;
116 pvr2_state.line_count++;
117 if( pvr2_state.line_count == pvr2_state.timing.total_lines ) {
118 asic_event( EVENT_RETRACE );
119 pvr2_state.line_count = 0;
120 pvr2_state.retrace = TRUE;
123 if( pvr2_state.line_count == pvr2_state.irq_vpos1 ) {
124 asic_event( EVENT_SCANLINE1 );
126 if( pvr2_state.line_count == pvr2_state.irq_vpos2 ) {
127 asic_event( EVENT_SCANLINE2 );
130 if( pvr2_state.line_count == pvr2_state.timing.retrace_lines ) {
131 if( pvr2_state.retrace ) {
132 pvr2_display_frame();
133 pvr2_state.retrace = FALSE;
140 int pvr2_get_frame_count()
142 return pvr2_state.frame_count;
146 * Display the next frame, copying the current contents of video ram to
147 * the window. If the video configuration has changed, first recompute the
148 * new frame size/depth.
150 void pvr2_display_frame( void )
152 uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 );
154 int dispsize = MMIO_READ( PVR2, DISP_SIZE );
155 int dispmode = MMIO_READ( PVR2, DISP_MODE );
156 int vidcfg = MMIO_READ( PVR2, DISP_CFG );
157 int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1;
158 int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
159 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
160 gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
161 gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);
162 video_buffer_t buffer = &video_buffer[video_buffer_idx];
163 video_buffer_idx = !video_buffer_idx;
164 video_buffer_t last = &video_buffer[video_buffer_idx];
165 buffer->rowstride = (vid_ppl + vid_stride) << 2;
166 buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );
167 buffer->vres = vid_lpf;
168 if( interlaced ) buffer->vres <<= 1;
169 switch( (dispmode & DISPMODE_COL) >> 2 ) {
171 buffer->colour_format = COLFMT_ARGB1555;
172 buffer->hres = vid_ppl << 1;
175 buffer->colour_format = COLFMT_RGB565;
176 buffer->hres = vid_ppl << 1;
179 buffer->colour_format = COLFMT_RGB888;
180 buffer->hres = (vid_ppl << 2) / 3;
183 buffer->colour_format = COLFMT_ARGB8888;
184 buffer->hres = vid_ppl;
188 if( buffer->hres <=8 )
190 if( buffer->vres <=8 )
192 if( display_driver != NULL ) {
193 if( buffer->hres != last->hres ||
194 buffer->vres != last->vres ||
195 buffer->colour_format != last->colour_format) {
196 display_driver->set_display_format( buffer->hres, buffer->vres,
197 buffer->colour_format );
200 display_driver->display_blank_frame( 0 );
201 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */
202 uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );
203 display_driver->display_blank_frame( colour );
204 } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {
205 display_driver->display_frame( buffer );
208 pvr2_state.frame_count++;
212 * This has to handle every single register individually as they all get masked
213 * off differently (and its easier to do it at write time)
215 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )
217 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
218 MMIO_WRITE( PVR2, reg, val );
228 /* Readonly registers */
231 val &= 0x00000007; /* Do stuff? */
232 MMIO_WRITE( PVR2, reg, val );
235 if( val == 0xFFFFFFFF )
239 MMIO_WRITE( PVR2, reg, val&0x000007FF );
241 case RENDER_POLYBASE:
242 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
245 MMIO_WRITE( PVR2, reg, val&0x00010101 );
248 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
251 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
254 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
257 MMIO_WRITE( PVR2, reg, val&0x000001FF );
261 MMIO_WRITE( PVR2, reg, val );
262 if( pvr2_state.retrace ) {
263 pvr2_display_frame();
264 pvr2_state.retrace = FALSE;
268 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
271 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
275 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
278 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
281 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
284 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
287 val = val & 0x03FF03FF;
288 pvr2_state.irq_vpos1 = (val >> 16);
289 pvr2_state.irq_vpos2 = val & 0x03FF;
290 MMIO_WRITE( PVR2, reg, val );
292 case RENDER_NEARCLIP:
293 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
296 MMIO_WRITE( PVR2, reg, val&0x000001FF );
299 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
302 MMIO_WRITE( PVR2, reg, val&0x00000007 );
305 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
308 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
311 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
314 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
317 MMIO_WRITE( PVR2, reg, val&0x000000FF );
320 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
323 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
325 case RENDER_FOGTBLCOL:
326 case RENDER_FOGVRTCOL:
327 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
329 case RENDER_FOGCOEFF:
330 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
334 MMIO_WRITE( PVR2, reg, val );
337 MMIO_WRITE( PVR2, reg, val&0x000003FF );
342 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
345 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
348 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
351 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
354 MMIO_WRITE( PVR2, reg, val&0x000003FF );
357 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
360 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
363 MMIO_WRITE( PVR2, reg, val&0x00000003 );
366 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
369 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
372 MMIO_WRITE( PVR2, reg, val&0x000000FF );
377 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
379 case RENDER_TILEBASE:
382 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
385 MMIO_WRITE( PVR2, reg, val&0x000F003F );
388 MMIO_WRITE( PVR2, reg, val&0x00133333 );
391 MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 );
394 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
397 if( val & 0x80000000 )
403 MMIO_WRITE( PVR2, reg, val&0x00000001 );
408 MMIO_REGION_READ_FN( PVR2, reg )
412 return sh4r.icount&0x20 ? 0x2000 : 1;
414 return MMIO_READ( PVR2, reg );
418 MMIO_REGION_DEFFNS( PVR2PAL )
420 void pvr2_set_base_address( uint32_t base )
422 mmio_region_PVR2_write( DISP_ADDR1, base );
428 int32_t mmio_region_PVR2TA_read( uint32_t reg )
433 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
435 pvr2_ta_write( (char *)&val, sizeof(uint32_t) );
439 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )
441 int bank_flag = (destaddr & 0x04) >> 2;
446 destaddr = destaddr & 0x7FFFFF;
447 if( destaddr + length > 0x800000 ) {
448 length = 0x800000 - destaddr;
451 for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) {
452 texcache_invalidate_page( i );
455 banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
456 banks[1] = banks[0] + 0x100000;
460 /* Handle non-aligned start of source */
461 if( destaddr & 0x03 ) {
462 char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03);
463 for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
466 bank_flag = !bank_flag;
469 dwsrc = (uint32_t *)src;
470 while( length >= 4 ) {
471 *banks[bank_flag]++ = *dwsrc++;
472 bank_flag = !bank_flag;
476 /* Handle non-aligned end of source */
479 char *dest = (char *)banks[bank_flag];
480 while( length-- > 0 ) {
486 void pvr2_vram_write_invert( sh4addr_t destaddr, char *src, uint32_t length, uint32_t line_length )
488 char *dest = video_base + (destaddr & 0x007FFFFF);
489 char *p = src + length - line_length;
491 memcpy( dest, p, line_length );
497 void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length )
499 int bank_flag = (srcaddr & 0x04) >> 2;
504 srcaddr = srcaddr & 0x7FFFFF;
505 if( srcaddr + length > 0x800000 )
506 length = 0x800000 - srcaddr;
508 banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
509 banks[1] = banks[0] + 0x100000;
513 /* Handle non-aligned start of source */
514 if( srcaddr & 0x03 ) {
515 char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03);
516 for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) {
519 bank_flag = !bank_flag;
522 dwdest = (uint32_t *)dest;
523 while( length >= 4 ) {
524 *dwdest++ = *banks[bank_flag]++;
525 bank_flag = !bank_flag;
529 /* Handle non-aligned end of source */
531 dest = (char *)dwdest;
532 char *src = (char *)banks[bank_flag];
533 while( length-- > 0 ) {
539 void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f )
542 pvr2_vram64_read( tmp, addr, length );
543 fwrite_dump( tmp, length, f );
.