2 * $Id: sh4core.in,v 1.8 2007-09-20 08:37:19 nkeynes Exp $
4 * SH4 emulation core, and parent module for all the SH4 peripheral
7 * Copyright (c) 2005 Nathan Keynes.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #define MODULE sh4_module
23 #include "sh4/sh4core.h"
24 #include "sh4/sh4mmio.h"
30 #define SH4_CALLTRACE 1
32 #define MAX_INT 0x7FFFFFFF
33 #define MIN_INT 0x80000000
34 #define MAX_INTF 2147483647.0
35 #define MIN_INTF -2147483648.0
37 /********************** SH4 Module Definition ****************************/
39 uint16_t *sh4_icache = NULL;
40 uint32_t sh4_icache_addr = 0;
42 uint32_t sh4_run_slice( uint32_t nanosecs )
47 if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
48 if( sh4r.event_pending < nanosecs ) {
49 sh4r.sh4_state = SH4_STATE_RUNNING;
50 sh4r.slice_cycle = sh4r.event_pending;
54 if( sh4_breakpoint_count == 0 ) {
55 for( ; sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
56 if( SH4_EVENT_PENDING() ) {
57 if( sh4r.event_types & PENDING_EVENT ) {
60 /* Eventq execute may (quite likely) deliver an immediate IRQ */
61 if( sh4r.event_types & PENDING_IRQ ) {
62 sh4_accept_interrupt();
65 if( !sh4_execute_instruction() ) {
70 for( ;sh4r.slice_cycle < nanosecs; sh4r.slice_cycle += sh4_cpu_period ) {
71 if( SH4_EVENT_PENDING() ) {
72 if( sh4r.event_types & PENDING_EVENT ) {
75 /* Eventq execute may (quite likely) deliver an immediate IRQ */
76 if( sh4r.event_types & PENDING_IRQ ) {
77 sh4_accept_interrupt();
81 if( !sh4_execute_instruction() )
83 #ifdef ENABLE_DEBUG_MODE
84 for( i=0; i<sh4_breakpoint_count; i++ ) {
85 if( sh4_breakpoints[i].address == sh4r.pc ) {
89 if( i != sh4_breakpoint_count ) {
91 if( sh4_breakpoints[i].type == BREAK_ONESHOT )
92 sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
99 /* If we aborted early, but the cpu is still technically running,
100 * we're doing a hard abort - cut the timeslice back to what we
103 if( sh4r.slice_cycle != nanosecs && sh4r.sh4_state == SH4_STATE_RUNNING ) {
104 nanosecs = sh4r.slice_cycle;
106 if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
107 TMU_run_slice( nanosecs );
108 SCIF_run_slice( nanosecs );
113 /********************** SH4 emulation core ****************************/
115 #define UNDEF(ir) return sh4_raise_slot_exception(EXC_ILLEGAL, EXC_SLOT_ILLEGAL)
116 #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0)
118 #if(SH4_CALLTRACE == 1)
119 #define MAX_CALLSTACK 32
120 static struct call_stack {
122 sh4addr_t target_addr;
123 sh4addr_t stack_pointer;
124 } call_stack[MAX_CALLSTACK];
126 static int call_stack_depth = 0;
127 int sh4_call_trace_on = 0;
129 static inline trace_call( sh4addr_t source, sh4addr_t dest )
131 if( call_stack_depth < MAX_CALLSTACK ) {
132 call_stack[call_stack_depth].call_addr = source;
133 call_stack[call_stack_depth].target_addr = dest;
134 call_stack[call_stack_depth].stack_pointer = sh4r.r[15];
139 static inline trace_return( sh4addr_t source, sh4addr_t dest )
141 if( call_stack_depth > 0 ) {
146 void fprint_stack_trace( FILE *f )
148 int i = call_stack_depth -1;
149 if( i >= MAX_CALLSTACK )
150 i = MAX_CALLSTACK - 1;
151 for( ; i >= 0; i-- ) {
152 fprintf( f, "%d. Call from %08X => %08X, SP=%08X\n",
153 (call_stack_depth - i), call_stack[i].call_addr,
154 call_stack[i].target_addr, call_stack[i].stack_pointer );
158 #define TRACE_CALL( source, dest ) trace_call(source, dest)
159 #define TRACE_RETURN( source, dest ) trace_return(source, dest)
161 #define TRACE_CALL( dest, rts )
162 #define TRACE_RETURN( source, dest )
165 #define MEM_READ_BYTE( addr ) sh4_read_byte(addr)
166 #define MEM_READ_WORD( addr ) sh4_read_word(addr)
167 #define MEM_READ_LONG( addr ) sh4_read_long(addr)
168 #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val)
169 #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val)
170 #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val)
172 #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4)
174 #define MEM_FP_READ( addr, reg ) sh4_read_float( addr, reg );
175 #define MEM_FP_WRITE( addr, reg ) sh4_write_float( addr, reg );
177 #define CHECKPRIV() if( !IS_SH4_PRIVMODE() ) return sh4_raise_slot_exception( EXC_ILLEGAL, EXC_SLOT_ILLEGAL )
178 #define CHECKRALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
179 #define CHECKRALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_READ )
180 #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
181 #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_DATA_ADDR_WRITE )
183 #define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPU_DISABLED, EXC_SLOT_FPU_DISABLED ); } }
184 #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; }
185 #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL)
187 static void sh4_write_float( uint32_t addr, int reg )
189 if( IS_FPU_DOUBLESIZE() ) {
191 sh4_write_long( addr, *((uint32_t *)&XF((reg)&0x0E)) );
192 sh4_write_long( addr+4, *((uint32_t *)&XF(reg)) );
194 sh4_write_long( addr, *((uint32_t *)&FR(reg)) );
195 sh4_write_long( addr+4, *((uint32_t *)&FR((reg)|0x01)) );
198 sh4_write_long( addr, *((uint32_t *)&FR((reg))) );
202 static void sh4_read_float( uint32_t addr, int reg )
204 if( IS_FPU_DOUBLESIZE() ) {
206 *((uint32_t *)&XF((reg) & 0x0E)) = sh4_read_long(addr);
207 *((uint32_t *)&XF(reg)) = sh4_read_long(addr+4);
209 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
210 *((uint32_t *)&FR((reg) | 0x01)) = sh4_read_long(addr+4);
213 *((uint32_t *)&FR(reg)) = sh4_read_long(addr);
217 gboolean sh4_execute_instruction( void )
227 if( pc > 0xFFFFFF00 ) {
229 syscall_invoke( pc );
230 sh4r.in_delay_slot = 0;
231 pc = sh4r.pc = sh4r.pr;
232 sh4r.new_pc = sh4r.pc + 2;
236 /* Read instruction */
237 uint32_t pageaddr = pc >> 12;
238 if( sh4_icache != NULL && pageaddr == sh4_icache_addr ) {
239 ir = sh4_icache[(pc&0xFFF)>>1];
241 sh4_icache = (uint16_t *)mem_get_page(pc);
242 if( ((uint32_t)sh4_icache) < MAX_IO_REGIONS ) {
243 /* If someone's actually been so daft as to try to execute out of an IO
244 * region, fallback on the full-blown memory read
247 ir = MEM_READ_WORD(pc);
249 sh4_icache_addr = pageaddr;
250 ir = sh4_icache[(pc&0xFFF)>>1];
254 AND Rm, Rn {: sh4r.r[Rn] &= sh4r.r[Rm]; :}
255 AND #imm, R0 {: R0 &= imm; :}
256 AND.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
257 NOT Rm, Rn {: sh4r.r[Rn] = ~sh4r.r[Rm]; :}
258 OR Rm, Rn {: sh4r.r[Rn] |= sh4r.r[Rm]; :}
259 OR #imm, R0 {: R0 |= imm; :}
260 OR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
262 tmp = MEM_READ_BYTE( sh4r.r[Rn] );
263 sh4r.t = ( tmp == 0 ? 1 : 0 );
264 MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 );
266 TST Rm, Rn {: sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); :}
267 TST #imm, R0 {: sh4r.t = (R0 & imm ? 0 : 1); :}
268 TST.B #imm, @(R0, GBR) {: sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 ); :}
269 XOR Rm, Rn {: sh4r.r[Rn] ^= sh4r.r[Rm]; :}
270 XOR #imm, R0 {: R0 ^= imm; :}
271 XOR.B #imm, @(R0, GBR) {: MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); :}
272 XTRCT Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); :}
275 sh4r.t = sh4r.r[Rn] >> 31;
277 sh4r.r[Rn] |= sh4r.t;
280 sh4r.t = sh4r.r[Rn] & 0x00000001;
282 sh4r.r[Rn] |= (sh4r.t << 31);
285 tmp = sh4r.r[Rn] >> 31;
287 sh4r.r[Rn] |= sh4r.t;
291 tmp = sh4r.r[Rn] & 0x00000001;
293 sh4r.r[Rn] |= (sh4r.t << 31 );
298 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
299 else if( (tmp & 0x1F) == 0 )
300 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31;
302 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1);
306 if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f);
307 else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0;
308 else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1);
311 sh4r.t = sh4r.r[Rn] >> 31;
315 sh4r.t = sh4r.r[Rn] & 0x00000001;
316 sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1;
318 SHLL Rn {: sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; :}
319 SHLR Rn {: sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; :}
320 SHLL2 Rn {: sh4r.r[Rn] <<= 2; :}
321 SHLR2 Rn {: sh4r.r[Rn] >>= 2; :}
322 SHLL8 Rn {: sh4r.r[Rn] <<= 8; :}
323 SHLR8 Rn {: sh4r.r[Rn] >>= 8; :}
324 SHLL16 Rn {: sh4r.r[Rn] <<= 16; :}
325 SHLR16 Rn {: sh4r.r[Rn] >>= 16; :}
327 EXTU.B Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; :}
328 EXTU.W Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; :}
329 EXTS.B Rm, Rn {: sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); :}
330 EXTS.W Rm, Rn {: sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); :}
331 SWAP.B Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); :}
332 SWAP.W Rm, Rn {: sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); :}
334 CLRT {: sh4r.t = 0; :}
335 SETT {: sh4r.t = 1; :}
336 CLRMAC {: sh4r.mac = 0; :}
337 LDTLB {: /* TODO */ :}
338 CLRS {: sh4r.s = 0; :}
339 SETS {: sh4r.s = 1; :}
340 MOVT Rn {: sh4r.r[Rn] = sh4r.t; :}
345 if( (tmp & 0xFC000000) == 0xE0000000 ) {
346 sh4_flush_store_queue(tmp);
355 MEM_WRITE_LONG( tmp, R0 );
357 MOV.B Rm, @(R0, Rn) {: MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); :}
358 MOV.W Rm, @(R0, Rn) {:
359 CHECKWALIGN16( R0 + sh4r.r[Rn] );
360 MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] );
362 MOV.L Rm, @(R0, Rn) {:
363 CHECKWALIGN32( R0 + sh4r.r[Rn] );
364 MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] );
366 MOV.B @(R0, Rm), Rn {: sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] ); :}
367 MOV.W @(R0, Rm), Rn {: CHECKRALIGN16( R0 + sh4r.r[Rm] );
368 sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] );
370 MOV.L @(R0, Rm), Rn {: CHECKRALIGN32( R0 + sh4r.r[Rm] );
371 sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] );
373 MOV.L Rm, @(disp, Rn) {:
374 tmp = sh4r.r[Rn] + disp;
375 CHECKWALIGN32( tmp );
376 MEM_WRITE_LONG( tmp, sh4r.r[Rm] );
378 MOV.B Rm, @Rn {: MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
379 MOV.W Rm, @Rn {: CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
380 MOV.L Rm, @Rn {: CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
381 MOV.B Rm, @-Rn {: sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); :}
382 MOV.W Rm, @-Rn {: sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); :}
383 MOV.L Rm, @-Rn {: sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); :}
384 MOV.L @(disp, Rm), Rn {:
385 tmp = sh4r.r[Rm] + disp;
386 CHECKRALIGN32( tmp );
387 sh4r.r[Rn] = MEM_READ_LONG( tmp );
389 MOV.B @Rm, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); :}
390 MOV.W @Rm, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); :}
391 MOV.L @Rm, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); :}
392 MOV Rm, Rn {: sh4r.r[Rn] = sh4r.r[Rm]; :}
393 MOV.B @Rm+, Rn {: sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++; :}
394 MOV.W @Rm+, Rn {: CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2; :}
395 MOV.L @Rm+, Rn {: CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4; :}
396 MOV.L @(disp, PC), Rn {:
398 tmp = (pc&0xFFFFFFFC) + disp + 4;
399 sh4r.r[Rn] = MEM_READ_LONG( tmp );
401 MOV.B R0, @(disp, GBR) {: MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); :}
402 MOV.W R0, @(disp, GBR) {:
403 tmp = sh4r.gbr + disp;
404 CHECKWALIGN16( tmp );
405 MEM_WRITE_WORD( tmp, R0 );
407 MOV.L R0, @(disp, GBR) {:
408 tmp = sh4r.gbr + disp;
409 CHECKWALIGN32( tmp );
410 MEM_WRITE_LONG( tmp, R0 );
412 MOV.B @(disp, GBR), R0 {: R0 = MEM_READ_BYTE( sh4r.gbr + disp ); :}
413 MOV.W @(disp, GBR), R0 {:
414 tmp = sh4r.gbr + disp;
415 CHECKRALIGN16( tmp );
416 R0 = MEM_READ_WORD( tmp );
418 MOV.L @(disp, GBR), R0 {:
419 tmp = sh4r.gbr + disp;
420 CHECKRALIGN32( tmp );
421 R0 = MEM_READ_LONG( tmp );
423 MOV.B R0, @(disp, Rn) {: MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); :}
424 MOV.W R0, @(disp, Rn) {:
425 tmp = sh4r.r[Rn] + disp;
426 CHECKWALIGN16( tmp );
427 MEM_WRITE_WORD( tmp, R0 );
429 MOV.B @(disp, Rm), R0 {: R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp ); :}
430 MOV.W @(disp, Rm), R0 {:
431 tmp = sh4r.r[Rm] + disp;
432 CHECKRALIGN16( tmp );
433 R0 = MEM_READ_WORD( tmp );
435 MOV.W @(disp, PC), Rn {:
438 sh4r.r[Rn] = MEM_READ_WORD( tmp );
440 MOVA @(disp, PC), R0 {:
442 R0 = (pc&0xFFFFFFFC) + disp + 4;
444 MOV #imm, Rn {: sh4r.r[Rn] = imm; :}
446 CMP/EQ #imm, R0 {: sh4r.t = ( R0 == imm ? 1 : 0 ); :}
447 CMP/EQ Rm, Rn {: sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); :}
448 CMP/GE Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
449 CMP/GT Rm, Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); :}
450 CMP/HI Rm, Rn {: sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); :}
451 CMP/HS Rm, Rn {: sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); :}
452 CMP/PL Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); :}
453 CMP/PZ Rn {: sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); :}
455 /* set T = 1 if any byte in RM & RN is the same */
456 tmp = sh4r.r[Rm] ^ sh4r.r[Rn];
457 sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 ||
458 (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0;
461 ADD Rm, Rn {: sh4r.r[Rn] += sh4r.r[Rm]; :}
462 ADD #imm, Rn {: sh4r.r[Rn] += imm; :}
465 sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t;
466 sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 );
469 tmp = sh4r.r[Rn] + sh4r.r[Rm];
470 sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) );
473 DIV0U {: sh4r.m = sh4r.q = sh4r.t = 0; :}
475 sh4r.q = sh4r.r[Rn]>>31;
476 sh4r.m = sh4r.r[Rm]>>31;
477 sh4r.t = sh4r.q ^ sh4r.m;
480 /* This is derived from the sh4 manual with some simplifications */
481 uint32_t tmp0, tmp1, tmp2, dir;
483 dir = sh4r.q ^ sh4r.m;
484 sh4r.q = (sh4r.r[Rn] >> 31);
486 sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t;
490 tmp1 = (sh4r.r[Rn]<tmp0 ? 1 : 0 );
493 tmp1 = (sh4r.r[Rn]>tmp0 ? 1 : 0 );
495 sh4r.q ^= sh4r.m ^ tmp1;
496 sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 );
498 DMULS.L Rm, Rn {: sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); :}
499 DMULU.L Rm, Rn {: sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); :}
502 sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 );
505 CHECKRALIGN16( sh4r.r[Rn] );
506 CHECKRALIGN16( sh4r.r[Rm] );
507 int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn]));
509 stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm]));
512 int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp;
513 if( tmpl > (int64_t)0x000000007FFFFFFFLL ) {
514 sh4r.mac = 0x000000017FFFFFFFLL;
515 } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) {
516 sh4r.mac = 0x0000000180000000LL;
518 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
519 ((uint32_t)(sh4r.mac + stmp));
522 sh4r.mac += SIGNEXT32(stmp);
526 CHECKRALIGN32( sh4r.r[Rm] );
527 CHECKRALIGN32( sh4r.r[Rn] );
528 int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn]));
530 tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac;
533 /* 48-bit Saturation. Yuch */
534 if( tmpl < (int64_t)0xFFFF800000000000LL )
535 tmpl = 0xFFFF800000000000LL;
536 else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL )
537 tmpl = 0x00007FFFFFFFFFFFLL;
541 MUL.L Rm, Rn {: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
542 (sh4r.r[Rm] * sh4r.r[Rn]); :}
544 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
545 (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF));
548 sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) |
549 (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF));
552 tmp = 0 - sh4r.r[Rm];
553 sh4r.r[Rn] = tmp - sh4r.t;
554 sh4r.t = ( 0<tmp || tmp<sh4r.r[Rn] ? 1 : 0 );
556 NEG Rm, Rn {: sh4r.r[Rn] = 0 - sh4r.r[Rm]; :}
557 SUB Rm, Rn {: sh4r.r[Rn] -= sh4r.r[Rm]; :}
560 sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t;
561 sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1));
566 CHECKDEST( pc + 4 + sh4r.r[Rn] );
567 sh4r.in_delay_slot = 1;
568 sh4r.pc = sh4r.new_pc;
569 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
574 CHECKDEST( pc + 4 + sh4r.r[Rn] );
575 sh4r.in_delay_slot = 1;
576 sh4r.pr = sh4r.pc + 4;
577 sh4r.pc = sh4r.new_pc;
578 sh4r.new_pc = pc + 4 + sh4r.r[Rn];
579 TRACE_CALL( pc, sh4r.new_pc );
585 CHECKDEST( sh4r.pc + disp + 4 )
587 sh4r.new_pc = sh4r.pc + 2;
594 CHECKDEST( sh4r.pc + disp + 4 )
596 sh4r.new_pc = sh4r.pc + 2;
603 CHECKDEST( sh4r.pc + disp + 4 )
604 sh4r.in_delay_slot = 1;
605 sh4r.pc = sh4r.new_pc;
606 sh4r.new_pc = pc + disp + 4;
607 sh4r.in_delay_slot = 1;
614 CHECKDEST( sh4r.pc + disp + 4 )
615 sh4r.in_delay_slot = 1;
616 sh4r.pc = sh4r.new_pc;
617 sh4r.new_pc = pc + disp + 4;
623 CHECKDEST( sh4r.pc + disp + 4 );
624 sh4r.in_delay_slot = 1;
625 sh4r.pc = sh4r.new_pc;
626 sh4r.new_pc = pc + 4 + disp;
630 CHECKDEST( sh4r.pc + disp + 4 );
632 sh4r.in_delay_slot = 1;
634 sh4r.pc = sh4r.new_pc;
635 sh4r.new_pc = pc + 4 + disp;
636 TRACE_CALL( pc, sh4r.new_pc );
641 MMIO_WRITE( MMU, TRA, imm<<2 );
643 sh4_raise_exception( EXC_TRAP );
647 CHECKDEST( sh4r.pr );
648 sh4r.in_delay_slot = 1;
649 sh4r.pc = sh4r.new_pc;
650 sh4r.new_pc = sh4r.pr;
651 TRACE_RETURN( pc, sh4r.new_pc );
655 if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
656 sh4r.sh4_state = SH4_STATE_STANDBY;
658 sh4r.sh4_state = SH4_STATE_SLEEP;
660 return FALSE; /* Halt CPU */
664 CHECKDEST( sh4r.spc );
666 sh4r.in_delay_slot = 1;
667 sh4r.pc = sh4r.new_pc;
668 sh4r.new_pc = sh4r.spc;
669 sh4_write_sr( sh4r.ssr );
673 CHECKDEST( sh4r.r[Rn] );
675 sh4r.in_delay_slot = 1;
676 sh4r.pc = sh4r.new_pc;
677 sh4r.new_pc = sh4r.r[Rn];
681 CHECKDEST( sh4r.r[Rn] );
683 sh4r.in_delay_slot = 1;
684 sh4r.pc = sh4r.new_pc;
685 sh4r.new_pc = sh4r.r[Rn];
687 TRACE_CALL( pc, sh4r.new_pc );
690 STS MACH, Rn {: sh4r.r[Rn] = (sh4r.mac>>32); :}
693 CHECKWALIGN32( sh4r.r[Rn] );
694 MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) );
699 CHECKWALIGN32( sh4r.r[Rn] );
700 MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() );
703 CHECKRALIGN32( sh4r.r[Rm] );
704 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
705 (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32);
711 CHECKWALIGN32( sh4r.r[Rm] );
712 sh4_write_sr( MEM_READ_LONG(sh4r.r[Rm]) );
716 sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) |
717 (((uint64_t)sh4r.r[Rm])<<32);
722 sh4_write_sr( sh4r.r[Rm] );
726 sh4r.sgr = sh4r.r[Rm];
730 CHECKRALIGN32( sh4r.r[Rm] );
731 sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]);
734 STS MACL, Rn {: sh4r.r[Rn] = (uint32_t)sh4r.mac; :}
737 CHECKWALIGN32( sh4r.r[Rn] );
738 MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac );
742 CHECKWALIGN32( sh4r.r[Rn] );
743 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr );
746 CHECKRALIGN32( sh4r.r[Rm] );
747 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
748 (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm]));
752 CHECKRALIGN32( sh4r.r[Rm] );
753 sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]);
757 sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) |
758 (uint64_t)((uint32_t)(sh4r.r[Rm]));
760 LDC Rm, GBR {: sh4r.gbr = sh4r.r[Rm]; :}
761 STS PR, Rn {: sh4r.r[Rn] = sh4r.pr; :}
764 CHECKWALIGN32( sh4r.r[Rn] );
765 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr );
770 CHECKWALIGN32( sh4r.r[Rn] );
771 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr );
774 CHECKRALIGN32( sh4r.r[Rm] );
775 sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] );
780 CHECKRALIGN32( sh4r.r[Rm] );
781 sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]);
784 LDS Rm, PR {: sh4r.pr = sh4r.r[Rm]; :}
787 sh4r.vbr = sh4r.r[Rm];
791 sh4r.r[Rn] = sh4r.sgr;
796 CHECKWALIGN32( sh4r.r[Rn] );
797 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr );
802 CHECKWALIGN32( sh4r.r[Rn] );
803 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr );
807 CHECKRALIGN32( sh4r.r[Rm] );
808 sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]);
813 sh4r.ssr = sh4r.r[Rm];
818 CHECKWALIGN32( sh4r.r[Rn] );
819 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc );
823 CHECKRALIGN32( sh4r.r[Rm] );
824 sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]);
829 sh4r.spc = sh4r.r[Rm];
831 STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
834 CHECKWALIGN32( sh4r.r[Rn] );
835 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul );
838 CHECKRALIGN32( sh4r.r[Rm] );
839 sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]);
842 LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
843 STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
846 CHECKWALIGN32( sh4r.r[Rn] );
847 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr );
850 CHECKRALIGN32( sh4r.r[Rm] );
851 sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]);
853 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
856 sh4r.fpscr = sh4r.r[Rm];
857 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
859 STC DBR, Rn {: CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; :}
863 CHECKWALIGN32( sh4r.r[Rn] );
864 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr );
868 CHECKRALIGN32( sh4r.r[Rm] );
869 sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]);
874 sh4r.dbr = sh4r.r[Rm];
876 STC.L Rm_BANK, @-Rn {:
879 CHECKWALIGN32( sh4r.r[Rn] );
880 MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] );
882 LDC.L @Rm+, Rn_BANK {:
884 CHECKRALIGN32( sh4r.r[Rm] );
885 sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] );
890 sh4r.r_bank[Rn_BANK] = sh4r.r[Rm];
894 sh4r.r[Rn] = sh4_read_sr();
898 sh4r.r[Rn] = sh4r.gbr;
902 sh4r.r[Rn] = sh4r.vbr;
906 sh4r.r[Rn] = sh4r.ssr;
910 sh4r.r[Rn] = sh4r.spc;
914 sh4r.r[Rn] = sh4r.r_bank[Rm_BANK];
919 if( IS_FPU_DOUBLEPREC() ) {
927 if( IS_FPU_DOUBLEPREC() ) {
936 if( IS_FPU_DOUBLEPREC() ) {
945 if( IS_FPU_DOUBLEPREC() ) {
954 if( IS_FPU_DOUBLEPREC() ) {
955 sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 );
957 sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 );
963 if( IS_FPU_DOUBLEPREC() ) {
964 sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 );
966 sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 );
970 FMOV @(R0, Rm), FRn {: MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); :}
971 FMOV FRm, @(R0, Rn) {: MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); :}
972 FMOV @Rm, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); :}
973 FMOV @Rm+, FRn {: MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; :}
974 FMOV FRm, @Rn {: MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
975 FMOV FRm, @-Rn {: sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); :}
977 if( IS_FPU_DOUBLESIZE() )
982 FSTS FPUL, FRn {: CHECKFPUEN(); FR(FRn) = FPULf; :}
983 FLDS FRm, FPUL {: CHECKFPUEN(); FPULf = FR(FRm); :}
986 if( IS_FPU_DOUBLEPREC() ) {
987 if( FRn&1 ) { // No, really...
988 dtmp = (double)FPULi;
989 FR(FRn) = *(((float *)&dtmp)+1);
991 DRF(FRn>>1) = (double)FPULi;
994 FR(FRn) = (float)FPULi;
999 if( IS_FPU_DOUBLEPREC() ) {
1002 *(((float *)&dtmp)+1) = FR(FRm);
1006 if( dtmp >= MAX_INTF )
1008 else if( dtmp <= MIN_INTF )
1011 FPULi = (int32_t)dtmp;
1014 if( ftmp >= MAX_INTF )
1016 else if( ftmp <= MIN_INTF )
1019 FPULi = (int32_t)ftmp;
1024 if( IS_FPU_DOUBLEPREC() ) {
1032 if( IS_FPU_DOUBLEPREC() ) {
1033 DR(FRn) = fabs(DR(FRn));
1035 FR(FRn) = fabsf(FR(FRn));
1040 if( IS_FPU_DOUBLEPREC() ) {
1041 DR(FRn) = sqrt(DR(FRn));
1043 FR(FRn) = sqrtf(FR(FRn));
1048 if( IS_FPU_DOUBLEPREC() ) {
1056 if( IS_FPU_DOUBLEPREC() ) {
1062 FMAC FR0, FRm, FRn {:
1064 if( IS_FPU_DOUBLEPREC() ) {
1065 DR(FRn) += DR(FRm)*DR(0);
1067 FR(FRn) += FR(FRm)*FR(0);
1072 sh4r.fpscr ^= FPSCR_FR;
1073 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
1075 FSCHG {: CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; :}
1078 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1079 DR(FRn) = (double)FPULf;
1084 if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) {
1085 FPULf = (float)DR(FRm);
1091 if( !IS_FPU_DOUBLEPREC() ) {
1092 FR(FRn) = 1.0/sqrtf(FR(FRn));
1097 if( !IS_FPU_DOUBLEPREC() ) {
1100 FR(tmp2+3) = FR(tmp)*FR(tmp2) +
1101 FR(tmp+1)*FR(tmp2+1) +
1102 FR(tmp+2)*FR(tmp2+2) +
1103 FR(tmp+3)*FR(tmp2+3);
1108 if( !IS_FPU_DOUBLEPREC() ) {
1109 sh4_fsca( FPULi, &(DRF(FRn>>1)) );
1111 float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;
1112 FR(FRn) = sinf(angle);
1113 FR((FRn)+1) = cosf(angle);
1119 if( !IS_FPU_DOUBLEPREC() ) {
1120 sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);
1123 float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];
1124 float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };
1125 FR(tmp) = xf[1] * fv[0] + xf[5]*fv[1] +
1126 xf[9]*fv[2] + xf[13]*fv[3];
1127 FR(tmp+1) = xf[0] * fv[0] + xf[4]*fv[1] +
1128 xf[8]*fv[2] + xf[12]*fv[3];
1129 FR(tmp+2) = xf[3] * fv[0] + xf[7]*fv[1] +
1130 xf[11]*fv[2] + xf[15]*fv[3];
1131 FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +
1132 xf[10]*fv[2] + xf[14]*fv[3];
1140 sh4r.pc = sh4r.new_pc;
1142 sh4r.in_delay_slot = 0;
.