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lxdream.org :: lxdream/test/sh4/excslot.s
lxdream 0.9.1
released Jun 29
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filename test/sh4/excslot.s
changeset 233:f8333b94f503
prev231:a9e61a96a885
next357:3592a10b3242
author nkeynes
date Wed Sep 27 10:21:34 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add user mode/system mode switch
Add undefined instruction tests
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     1 .section .text
     2 .include "sh4/inc.s"
     3 !
     4 ! Test for all cases that raise a slot-illegal exception (according to the SH4
     5 ! manual). See Page 103 of the Hitachi manual
     7 .global _test_slot_illegal
     8 _test_slot_illegal:	
     9 	start_test
    11 ! First the easy ones - instructions not permitted in delay slots at any
    12 ! time:
    13 ! JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA,
    14 ! LDC (to SR), MOV pcrel, MOVA
    15 !
    16 ! Note that the tests use BSR as the branch instruction, and assume it
    17 ! functions correctly.
    19 test_slot_1:	!JMP
    20 	add #1, r12
    21 	expect_exc 0x000001A0
    22 test_slot_1_pc:	
    23 	bsr test_slot_fail
    24 	jmp @r3
    25 	assert_exc_caught test_slot_str_k1 test_slot_1_pc
    27 test_slot_2:	! JSR
    28 	add #1, r12
    29 	expect_exc 0x000001A0
    30 test_slot_2_pc:
    31 	bsr test_slot_fail
    32 	jsr @r3
    33 	assert_exc_caught test_slot_str_k1 test_slot_2_pc
    35 test_slot_3:	! BRA
    36 	add #1, r12
    37 	expect_exc 0x000001A0
    38 test_slot_3_pc:
    39 	bsr test_slot_fail
    40 	bra test_slot_fail
    41 	assert_exc_caught test_slot_str_k1 test_slot_3_pc
    43 test_slot_4:	! BRAF
    44 	add #1, r12
    45 	expect_exc 0x000001A0
    46 test_slot_4_pc:
    47 	bsr test_slot_fail
    48 	braf r3
    49 	assert_exc_caught test_slot_str_k test_slot_4_pc
    51 test_slot_5:	! BSR
    52 	add #1, r12
    53 	expect_exc 0x000001A0
    54 test_slot_5_pc:
    55 	bsr test_slot_fail
    56 	bsr test_slot_fail
    57 	assert_exc_caught test_slot_str_k test_slot_5_pc
    59 test_slot_6:	! BSRF
    60 	add #1, r12
    61 	expect_exc 0x000001A0
    62 test_slot_6_pc:
    63 	bsr test_slot_fail
    64 	bsrf r3
    65 	assert_exc_caught test_slot_str_k test_slot_6_pc
    67 test_slot_7:	! BF
    68 	add #1, r12
    69 	expect_exc 0x000001A0
    70 test_slot_7_pc:
    71 	bsr test_slot_fail
    72 	bf test_slot_7_fail
    73 test_slot_7_fail:	
    74 	assert_exc_caught test_slot_str_k test_slot_7_pc
    76 test_slot_8:	! BT
    77 	add #1, r12
    78 	expect_exc 0x000001A0
    79 test_slot_8_pc:
    80 	bsr test_slot_fail
    81 	bt test_slot_8_fail
    82 test_slot_8_fail:	
    83 	assert_exc_caught test_slot_str_k test_slot_8_pc
    85 test_slot_9:	! BF/S
    86 	add #1, r12
    87 	expect_exc 0x000001A0
    88 test_slot_9_pc:
    89 	bsr test_slot_fail
    90 	bf/s test_slot_9_fail
    91 test_slot_9_fail:	
    92 	assert_exc_caught test_slot_str_k test_slot_9_pc
    94 test_slot_10:	! BT/S
    95 	add #1, r12
    96 	expect_exc 0x000001A0
    97 test_slot_10_pc:
    98 	bsr test_slot_fail
    99 	bt/s test_slot_10_fail
   100 test_slot_10_fail:	
   101 	assert_exc_caught test_slot_str_k test_slot_10_pc
   102 	bra test_slot_11
   103 	nop
   104 test_slot_str_k1:
   105 	.long test_slot_str
   108 test_slot_11:	! TRAPA
   109 	add #1, r12
   110 	expect_exc 0x000001A0
   111 test_slot_11_pc:
   112 	bsr test_slot_fail
   113 	trapa #12
   114 	assert_exc_caught test_slot_str_k test_slot_11_pc
   116 test_slot_12:	! LDC r0, sr
   117 	add #1, r12
   118 	expect_exc 0x000001A0
   119 	stc sr, r0
   120 test_slot_12_pc:
   121 	bsr test_slot_fail
   122 	ldc r0, sr
   123 	assert_exc_caught test_slot_str_k test_slot_12_pc
   125 test_slot_13:	! LDC @r0, sr
   126 	add #1, r12
   127 	expect_exc 0x000001A0
   128 	stc sr, r1
   129 	mova test_slot_13_temp, r0
   130 	mov.l r1, @r0
   131 test_slot_13_pc:
   132 	bsr test_slot_fail
   133 	ldc.l @r0+, sr
   134 	assert_exc_caught test_slot_str_k test_slot_13_pc
   135 	bra test_slot_14
   136 	nop
   137 test_slot_13_temp:
   138 	.long 0
   140 test_slot_14:	! MOVA
   141 	add #1, r12
   142 	expect_exc 0x000001A0
   143 test_slot_14_pc:
   144 	bsr test_slot_fail
   145 	mova test_slot_15, r0
   146 	assert_exc_caught test_slot_str_k test_slot_14_pc
   148 test_slot_15:	! MOV.W pcrel, Rn
   149 	add #1, r12
   150 	expect_exc 0x000001A0
   151 test_slot_15_pc:
   152 	bsr test_slot_fail
   153 	mov.w test_slot_16, r0
   154 	assert_exc_caught test_slot_str_k test_slot_15_pc
   156 test_slot_16:	! MOV.L pcrel, Rn
   157 	add #1, r12
   158 	expect_exc 0x000001A0
   159 test_slot_16_pc:
   160 	bsr test_slot_fail
   161 	mov.l test_slot_str_k, r0
   162 	assert_exc_caught test_slot_str_k test_slot_16_pc
   164 test_slot_17:	! "Undefined" 0xFFFD
   165 	add #1, r12
   166 	expect_exc 0x000001A0
   167 test_slot_17_pc:
   168 	bsr test_slot_fail
   169 	.word 0xFFFD
   170 	assert_exc_caught test_slot_str_k test_slot_17_pc
   172 !
   173 ! Ok now the privilege tests. These should raise SLOT_ILLEGAL when executed
   174 ! in a delay slot (otherwise it's GENERAL_ILLEGAL)
   176 test_slot_18:   ! LDC Rn, SPC in user mode
   177 	add #1, r12
   178 	expect_exc 0x000001A0
   179 	stc spc, r4
   180 	usermode
   181 test_slot_18_pc:
   182 	bsr test_slot_fail
   183 	ldc r4, spc
   184 	systemmode
   185 	assert_exc_caught test_slot_str_k test_slot_18_pc
   188 test_slot_end:
   189 	end_test test_slot_str_k
   191 ! Returns after the delay slot, which should hit the "no exception" test
   192 test_slot_fail:
   193 	rts
   194 	nop
   196 test_slot_str_k:
   197 	.long test_slot_str
   198 test_slot_str:
   199 	.string "SLOT-ILLEGAL"
.