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lxdream.org :: lxdream/test/sh4/inc.s
lxdream 0.9.1
released Jun 29
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filename test/sh4/inc.s
changeset 233:f8333b94f503
prev231:a9e61a96a885
next357:3592a10b3242
author nkeynes
date Wed Sep 27 10:21:34 2006 +0000 (14 years ago)
permissions -rw-r--r--
last change Add user mode/system mode switch
Add undefined instruction tests
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     1 .altmacro
     2 .macro	fail name
     3 LOCAL LC1
     4 LOCAL LC2
     5 	add #1, r13
     6 	mov.l LC1, r3
     7 	mov r12, r5
     8 	mov.l \name, r4
     9 	xor r6, r6
    10 	jsr @r3
    11 	nop
    12 	bra LC2
    13 	nop
    14 .align 4
    15 LC1:
    16 	.long _test_print_failure
    17 LC2:	
    18 .endm
    20 .macro failm name msg
    21 LOCAL LC1
    22 LOCAL LC2
    23 	add #1, r13
    24 	mov.l LC1, r3
    25 	mov r12, r5
    26 	mov.l \name, r4
    27 	mov.l \msg, r6
    28 	jsr @r3
    29 	nop
    30 	bra LC2
    31 	nop
    32 .align 4
    33 LC1:
    34 	.long _test_print_failure
    35 LC2:	
    36 .endm
    39 .macro start_test
    40 	mov.l r14, @-r15
    41 	sts.l pr, @-r15
    42 	mov.l r12, @-r15
    43 	mov.l r13, @-r15
    44 	mov r15, r14
    45 	xor r12,r12
    46 	xor r13,r13
    47 ! r12 is the test counter
    48 ! r13 is the failed-test counter
    49 .endm
    51 .macro end_test name
    52 LOCAL test_print_result_k
    53 	mov.l \name, r4
    54 	mov r13, r5
    55 	mov r12, r6
    56 	mov.l test_print_result_k, r3
    57 	jsr @r3
    58 	nop
    59 	mov r14, r15
    60 	mov.l @r15+, r13
    61 	mov.l @r15+, r12
    62 	lds.l @r15+, pr
    63 	mov.l @r15+, r14	
    64 	rts
    65 	nop
    66 .align 4
    67 test_print_result_k:
    68 	.long _test_print_result
    69 .endm	
    72 .macro assert_t_set testname
    73 LOCAL LC1
    74 LOCAL LC2
    75 LOCAL LCM
    76 	stc sr, r1
    77 	mov.l r1, @-r15
    78 	xor r0, r0
    79 	add #1, r0
    80 	and r0, r1
    81 	cmp/eq r0, r1
    82 	bt LC2
    83 	add #1, r13
    84 	mov.l LC1, r3
    85 	mov r12, r5
    86 	mov.l \testname, r4
    87 	mov.l LCM, r6
    88 	jsr @r3
    89 	nop
    90 	bra LC2
    91 	nop
    92 .align 4
    93 LC1:
    94 	.long _test_print_failure
    95 LCM:	.long assert_t_clear_message
    96 LC2:
    97 	mov.l @r15+, r1
    98 	ldc r1, sr
    99 .endm
   101 .macro assert_t_clear testname
   102 LOCAL LC1
   103 LOCAL LC2
   104 LOCAL LCM
   105 	stc sr, r1
   106 	mov.l r1, @-r15
   107 	xor r0, r0
   108 	add #1, r0
   109 	and r0, r1
   110 	cmp/eq r0, r1
   111 	bf LC2
   112 	add #1, r13
   113 	mov.l LC1, r3
   114 	mov r12, r5
   115 	mov.l \testname, r4
   116 	mov.l LCM, r6
   117 	jsr @r3
   118 	nop
   119 	bra LC2
   120 	nop
   121 .align 4
   122 LC1:
   123 	.long _test_print_failure
   124 LCM:	.long assert_t_clear_message
   125 LC2:
   126 	mov.l @r15+, r1
   127 	ldc r1, sr
   128 .endm
   130 ! Note that yes there is a perfectly good clrt instruction, but we try to
   131 ! minimize the number of instructions we depend on here.
   133 .macro clc
   134 	xor r0, r0
   135 	addc r0, r0
   136 .endm
   137 .macro setc
   138 	xor r0, r0
   139 	not r0, r0
   140 	addc r0, r0
   141 .endm
   143 ! Switch to user-mode
   144 .macro usermode
   145 	stc sr, r0
   146 	mov #64, r1
   147 	mov #24, r2
   148 	shld r2, r1
   149 	not r1, r1
   150 	and r0, r1
   151 	ldc r1, sr
   152 .endm
   154 ! Switch to system-mode
   155 ! NB: implemented as a trap to the interrupt handler, as obviously
   156 ! we can't just update SR...
   157 .macro systemmode
   158 	trapa #42
   159 	nop
   160 .endm
   162 .macro clearbl
   163 LOCAL L1
   164 LOCAL L2
   165 	mov.l L1, r0
   166 	stc sr, r1
   167 	and r0, r1
   168 	ldc r1, sr
   169 	bra L2
   170 	nop
   171 .align 4
   172 L1:	.long 0xEFFFFFFF
   173 L2:	
   174 .endm
   176 .macro setbl
   177 LOCAL L1
   178 LOCAL L2
   179 	xor r0, r0
   180 	add #1, r0
   181 	shll r0, 28
   182 	stc sr, r1
   183 	or r0, r1
   184 	ldc r1, sr
   185 	bra L2
   186 	nop
   187 .align 4
   188 L1:	.long 0x10000000
   189 L2:	
   190 .endm
   192 .macro expect_exc code
   193 LOCAL L1, L2, L3
   194 	mov.l L1, r3
   195 	mov.l L2, r4
   196 	jsr @r3
   197 	nop
   198 	bra L3
   199 	nop
   200 .align 4
   201 L1:	.long _expect_exception
   202 L2:	.long \code
   203 L3:
   205 .endm
   207 .macro assert_exc_caught testname, expectpc
   208 LOCAL L1, L2, L3
   209 	mov.l L1, r3
   210 	mov.l \testname, r4
   211 	mov r12, r5
   212 	mov.l L2, r6
   213 	jsr @r3
   214 	nop
   215 	add r0, r13
   216 	bra L3
   217 	nop
   218 .align 4
   219 L1:	.long _assert_exception_caught
   220 L2:	.long \expectpc
   221 L3:	
   222 .endm
   224 	.align 2
   225 assert_t_set_message:
   226 	.string "Expected T=1 but was 0"
   228 assert_t_clear_message:
   229 	.string "Expected T=0 but was 1"
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