lxdream.org :: lxdream/src/pvr2/pvr2.c r335:fb890e1814c0

tree revision 335:fb890e1814c0

filename	src/pvr2/pvr2.c
changeset	335:fb890e1814c0
prev	304:2855cf8709a5
next	337:cdd757aa8e8c
author	nkeynes
date	Sat Jan 27 12:03:53 2007 +0000 (14 years ago)
permissions	-rw-r--r--
last change	Start working towards more thorough interlaced support

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     1 /**

     2  * $Id: pvr2.c,v 1.42 2007-01-27 12:03:53 nkeynes Exp $

     3  *

     4  * PVR2 (Video) Core module implementation and MMIO registers.

     5  *

     6  * Copyright (c) 2005 Nathan Keynes.

     7  *

     8  * This program is free software; you can redistribute it and/or modify

     9  * it under the terms of the GNU General Public License as published by

    10  * the Free Software Foundation; either version 2 of the License, or

    11  * (at your option) any later version.

    12  *

    13  * This program is distributed in the hope that it will be useful,

    14  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

    16  * GNU General Public License for more details.

    17  */

    18 #define MODULE pvr2_module

    20 #include "dream.h"

    21 #include "eventq.h"

    22 #include "display.h"

    23 #include "mem.h"

    24 #include "asic.h"

    25 #include "clock.h"

    26 #include "pvr2/pvr2.h"

    27 #include "sh4/sh4core.h"

    28 #define MMIO_IMPL

    29 #include "pvr2/pvr2mmio.h"

    31 char *video_base;

    33 #define HPOS_PER_FRAME 0

    34 #define HPOS_PER_LINECOUNT 1

    36 static void pvr2_init( void );

    37 static void pvr2_reset( void );

    38 static uint32_t pvr2_run_slice( uint32_t );

    39 static void pvr2_save_state( FILE *f );

    40 static int pvr2_load_state( FILE *f );

    41 static void pvr2_update_raster_posn( uint32_t nanosecs );

    42 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );

    43 uint32_t pvr2_get_sync_status();

    45 void pvr2_display_frame( void );

    47 int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 };

    49 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,

    50 					pvr2_run_slice, NULL,

    51 					pvr2_save_state, pvr2_load_state };

    54 display_driver_t display_driver = NULL;

    56 struct video_timing {

    57     int fields_per_second;

    58     int total_lines;

    59     int retrace_lines;

    60     int line_time_ns;

    61 };

    63 struct video_timing pal_timing = { 50, 625, 65, 31945 };

    64 struct video_timing ntsc_timing= { 60, 525, 65, 31746 };

    66 struct pvr2_state {

    67     uint32_t frame_count;

    68     uint32_t line_count;

    69     uint32_t line_remainder;

    70     uint32_t cycles_run; /* Cycles already executed prior to main time slice */

    71     uint32_t irq_hpos_line;

    72     uint32_t irq_hpos_line_count;

    73     uint32_t irq_hpos_mode;

    74     uint32_t irq_hpos_time_ns; /* Time within the line */

    75     uint32_t irq_vpos1;

    76     uint32_t irq_vpos2;

    77     uint32_t odd_even_field; /* 1 = odd, 0 = even */

    78     gchar *save_next_render_filename;

    79     /* timing */

    80     uint32_t dot_clock;

    81     uint32_t total_lines;

    82     uint32_t line_size;

    83     uint32_t line_time_ns;

    84     uint32_t vsync_lines;

    85     uint32_t hsync_width_ns;

    86     uint32_t front_porch_ns;

    87     uint32_t back_porch_ns;

    88     uint32_t retrace_start_line;

    89     uint32_t retrace_end_line;

    90     gboolean interlaced;

    91     struct video_timing timing;

    92 } pvr2_state;

    94 struct video_buffer video_buffer[2];

    95 int video_buffer_idx = 0;

    97 /**

    98  * Event handler for the hpos callback

    99  */

   100 static void pvr2_hpos_callback( int eventid ) {

   101     asic_event( eventid );

   102     pvr2_update_raster_posn(sh4r.slice_cycle);

   103     if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {

   104 	pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;

   105 	while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {

   106 	    pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);

   107 	}

   108     }

   109     pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,

   110 				  pvr2_state.irq_hpos_time_ns );

   111 }

   113 /**

   114  * Event handler for the scanline callbacks. Fires the corresponding

   115  * ASIC event, and resets the timer for the next field.

   116  */

   117 static void pvr2_scanline_callback( int eventid ) {

   118     asic_event( eventid );

   119     pvr2_update_raster_posn(sh4r.slice_cycle);

   120     if( eventid == EVENT_SCANLINE1 ) {

   121 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );

   122     } else {

   123 	pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );

   124     }

   125 }

   127 static void pvr2_init( void )

   128 {

   129     register_io_region( &mmio_region_PVR2 );

   130     register_io_region( &mmio_region_PVR2PAL );

   131     register_io_region( &mmio_region_PVR2TA );

   132     register_event_callback( EVENT_HPOS, pvr2_hpos_callback );

   133     register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );

   134     register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );

   135     video_base = mem_get_region_by_name( MEM_REGION_VIDEO );

   136     texcache_init();

   137     pvr2_reset();

   138     pvr2_ta_reset();

   139     pvr2_state.save_next_render_filename = NULL;

   140 }

   142 static void pvr2_reset( void )

   143 {

   144     pvr2_state.line_count = 0;

   145     pvr2_state.line_remainder = 0;

   146     pvr2_state.cycles_run = 0;

   147     pvr2_state.irq_vpos1 = 0;

   148     pvr2_state.irq_vpos2 = 0;

   149     pvr2_state.timing = ntsc_timing;

   150     pvr2_state.dot_clock = PVR2_DOT_CLOCK;

   151     pvr2_state.back_porch_ns = 4000;

   152     mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );

   153     mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );

   154     mmio_region_PVR2_write( YUV_ADDR, 0 );

   155     mmio_region_PVR2_write( YUV_CFG, 0 );

   156     video_buffer_idx = 0;

   158     pvr2_ta_init();

   159     pvr2_render_init();

   160     texcache_flush();

   161 }

   163 static void pvr2_save_state( FILE *f )

   164 {

   165     fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );

   166     pvr2_ta_save_state( f );

   167     pvr2_yuv_save_state( f );

   168 }

   170 static int pvr2_load_state( FILE *f )

   171 {

   172     if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )

   173 	return 1;

   174     if( pvr2_ta_load_state(f) ) {

   175 	return 1;

   176     }

   177     return pvr2_yuv_load_state(f);

   178 }

   180 /**

   181  * Update the current raster position to the given number of nanoseconds,

   182  * relative to the last time slice. (ie the raster will be adjusted forward

   183  * by nanosecs - nanosecs_already_run_this_timeslice)

   184  */

   185 static void pvr2_update_raster_posn( uint32_t nanosecs )

   186 {

   187     uint32_t old_line_count = pvr2_state.line_count;

   188     if( pvr2_state.line_time_ns == 0 ) {

   189 	return; /* do nothing */

   190     }

   191     pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);

   192     pvr2_state.cycles_run = nanosecs;

   193     while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {

   194 	pvr2_state.line_count ++;

   195 	pvr2_state.line_remainder -= pvr2_state.line_time_ns;

   196     }

   198     if( pvr2_state.line_count >= pvr2_state.total_lines ) {

   199 	pvr2_state.line_count -= pvr2_state.total_lines;

   200 	if( pvr2_state.interlaced ) {

   201 	    pvr2_state.odd_even_field = !pvr2_state.odd_even_field;

   202 	}

   203     }

   204     if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&

   205 	(old_line_count < pvr2_state.retrace_end_line ||

   206 	 old_line_count > pvr2_state.line_count) ) {

   207 	pvr2_display_frame();

   208     }

   209 }

   211 static uint32_t pvr2_run_slice( uint32_t nanosecs )

   212 {

   213     pvr2_update_raster_posn( nanosecs );

   214     pvr2_state.cycles_run = 0;

   215     return nanosecs;

   216 }

   218 int pvr2_get_frame_count()

   219 {

   220     return pvr2_state.frame_count;

   221 }

   223 gboolean pvr2_save_next_scene( const gchar *filename )

   224 {

   225     if( pvr2_state.save_next_render_filename != NULL ) {

   226 	g_free( pvr2_state.save_next_render_filename );

   227     }

   228     pvr2_state.save_next_render_filename = g_strdup(filename);

   229     return TRUE;

   230 }

   234 /**

   235  * Display the next frame, copying the current contents of video ram to

   236  * the window. If the video configuration has changed, first recompute the

   237  * new frame size/depth.

   238  */

   239 void pvr2_display_frame( void )

   240 {

   241     uint32_t display_addr;

   242     int dispsize = MMIO_READ( PVR2, DISP_SIZE );

   243     int dispmode = MMIO_READ( PVR2, DISP_MODE );

   244     int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );

   245     int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);

   246     int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1;

   247     int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;

   248     gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;

   249     gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE);

   250     video_buffer_t buffer = &video_buffer[video_buffer_idx];

   251     video_buffer_idx = !video_buffer_idx;

   252     video_buffer_t last = &video_buffer[video_buffer_idx];

   253     buffer->rowstride = (vid_ppl + vid_stride) << 2;

   254     buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 );

   255     buffer->line_double = (dispmode & DISPMODE_LINEDOUBLE) ? TRUE : FALSE;

   256     buffer->vres = vid_lpf;

   257     if( interlaced ) {

   258 	if( vid_ppl == vid_stride ) { /* Magic deinterlace */

   259 	    buffer->vres <<= 1;

   260 	    buffer->rowstride = vid_ppl << 2;

   261 	    display_addr = MMIO_READ( PVR2, DISP_ADDR1 );

   262 	} else { /* Just display the field as is, folks */

   263 	    if( pvr2_state.odd_even_field ) {

   264 		display_addr = MMIO_READ( PVR2, DISP_ADDR1 );

   265 	    } else {

   266 		display_addr = MMIO_READ( PVR2, DISP_ADDR2 );

   267 	    }

   268 	}

   269     } else {

   270 	display_addr = MMIO_READ( PVR2, DISP_ADDR1 );

   271     }

   272     switch( (dispmode & DISPMODE_COLFMT) >> 2 ) {

   273     case 0:

   274 	buffer->colour_format = COLFMT_ARGB1555;

   275 	buffer->hres = vid_ppl << 1;

   276 	break;

   277     case 1:

   278 	buffer->colour_format = COLFMT_RGB565;

   279 	buffer->hres = vid_ppl << 1;

   280 	break;

   281     case 2:

   282 	buffer->colour_format = COLFMT_RGB888;

   283 	buffer->hres = (vid_ppl << 2) / 3;

   284 	break;

   285     case 3:

   286 	buffer->colour_format = COLFMT_ARGB8888;

   287 	buffer->hres = vid_ppl;

   288 	break;

   289     }

   291     if( buffer->hres <=8 )

   292 	buffer->hres = 640;

   293     if( buffer->vres <=8 )

   294 	buffer->vres = 480;

   295     if( display_driver != NULL ) {

   296 	if( buffer->hres != last->hres ||

   297 	    buffer->vres != last->vres ||

   298 	    buffer->colour_format != last->colour_format) {

   299 	    display_driver->set_display_format( buffer->hres, buffer->vres,

   300 						buffer->colour_format );

   301 	}

   302 	if( !bEnabled ) {

   303 	    display_driver->display_blank_frame( 0 );

   304 	} else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */

   305 	    uint32_t colour = MMIO_READ( PVR2, DISP_BORDER );

   306 	    display_driver->display_blank_frame( colour );

   307 	} else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) {

   308 	    display_driver->display_frame( buffer );

   309 	}

   310     }

   311     pvr2_state.frame_count++;

   312 }

   314 /**

   315  * This has to handle every single register individually as they all get masked

   316  * off differently (and its easier to do it at write time)

   317  */

   318 void mmio_region_PVR2_write( uint32_t reg, uint32_t val )

   319 {

   320     if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */

   321         MMIO_WRITE( PVR2, reg, val );

   322         return;

   323     }

   325     switch(reg) {

   326     case PVRID:

   327     case PVRVER:

   328     case GUNPOS: /* Read only registers */

   329 	break;

   330     case PVRRESET:

   331 	val &= 0x00000007; /* Do stuff? */

   332 	MMIO_WRITE( PVR2, reg, val );

   333 	break;

   334     case RENDER_START: /* Don't really care what value */

   335 	if( pvr2_state.save_next_render_filename != NULL ) {

   336 	    if( pvr2_render_save_scene(pvr2_state.save_next_render_filename) == 0 ) {

   337 		INFO( "Saved scene to %s", pvr2_state.save_next_render_filename);

   338 	    }

   339 	    g_free( pvr2_state.save_next_render_filename );

   340 	    pvr2_state.save_next_render_filename = NULL;

   341 	}

   342 	pvr2_render_scene();

   343 	break;

   344     case RENDER_POLYBASE:

   345     	MMIO_WRITE( PVR2, reg, val&0x00F00000 );

   346     	break;

   347     case RENDER_TSPCFG:

   348     	MMIO_WRITE( PVR2, reg, val&0x00010101 );

   349     	break;

   350     case DISP_BORDER:

   351     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );

   352     	break;

   353     case DISP_MODE:

   354     	MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );

   355     	break;

   356     case RENDER_MODE:

   357     	MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );

   358     	break;

   359     case RENDER_SIZE:

   360     	MMIO_WRITE( PVR2, reg, val&0x000001FF );

   361     	break;

   362     case DISP_ADDR1:

   363 	val &= 0x00FFFFFC;

   364 	MMIO_WRITE( PVR2, reg, val );

   365 	pvr2_update_raster_posn(sh4r.slice_cycle);

   366 	if( pvr2_state.line_count >= pvr2_state.retrace_start_line ||

   367 	    pvr2_state.line_count < pvr2_state.retrace_end_line ) {

   368 	    pvr2_display_frame();

   369 	}

   370 	break;

   371     case DISP_ADDR2:

   372     	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );

   373     	break;

   374     case DISP_SIZE:

   375     	MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );

   376     	break;

   377     case RENDER_ADDR1:

   378     case RENDER_ADDR2:

   379     	MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );

   380     	break;

   381     case RENDER_HCLIP:

   382 	MMIO_WRITE( PVR2, reg, val&0x07FF07FF );

   383 	break;

   384     case RENDER_VCLIP:

   385 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   386 	break;

   387     case DISP_HPOSIRQ:

   388 	MMIO_WRITE( PVR2, reg, val&0x03FF33FF );

   389 	pvr2_state.irq_hpos_line = val & 0x03FF;

   390 	pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;

   391 	pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;

   392 	switch( pvr2_state.irq_hpos_mode ) {

   393 	case 3: /* Reserved - treat as 0 */

   394 	case 0: /* Once per frame at specified line */

   395 	    pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;

   396 	    break;

   397 	case 2: /* Once per line - as per-line-count */

   398 	    pvr2_state.irq_hpos_line = 1;

   399 	    pvr2_state.irq_hpos_mode = 1;

   400 	case 1: /* Once per N lines */

   401 	    pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;

   402 	    pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +

   403 		pvr2_state.irq_hpos_line_count;

   404 	    while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {

   405 		pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);

   406 	    }

   407 	    pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;

   408 	}

   409 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,

   410 					  pvr2_state.irq_hpos_time_ns );

   411 	break;

   412     case DISP_VPOSIRQ:

   413 	val = val & 0x03FF03FF;

   414 	pvr2_state.irq_vpos1 = (val >> 16);

   415 	pvr2_state.irq_vpos2 = val & 0x03FF;

   416 	pvr2_update_raster_posn(sh4r.slice_cycle);

   417 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );

   418 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );

   419 	MMIO_WRITE( PVR2, reg, val );

   420 	break;

   421     case RENDER_NEARCLIP:

   422 	MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );

   423 	break;

   424     case RENDER_SHADOW:

   425 	MMIO_WRITE( PVR2, reg, val&0x000001FF );

   426 	break;

   427     case RENDER_OBJCFG:

   428     	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );

   429     	break;

   430     case RENDER_TSPCLIP:

   431     	MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );

   432     	break;

   433     case RENDER_FARCLIP:

   434 	MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );

   435 	break;

   436     case RENDER_BGPLANE:

   437     	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );

   438     	break;

   439     case RENDER_ISPCFG:

   440     	MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );

   441     	break;

   442     case VRAM_CFG1:

   443 	MMIO_WRITE( PVR2, reg, val&0x000000FF );

   444 	break;

   445     case VRAM_CFG2:

   446 	MMIO_WRITE( PVR2, reg, val&0x003FFFFF );

   447 	break;

   448     case VRAM_CFG3:

   449 	MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );

   450 	break;

   451     case RENDER_FOGTBLCOL:

   452     case RENDER_FOGVRTCOL:

   453 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );

   454 	break;

   455     case RENDER_FOGCOEFF:

   456 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );

   457 	break;

   458     case RENDER_CLAMPHI:

   459     case RENDER_CLAMPLO:

   460 	MMIO_WRITE( PVR2, reg, val );

   461 	break;

   462     case RENDER_TEXSIZE:

   463 	MMIO_WRITE( PVR2, reg, val&0x00031F1F );

   464 	break;

   465     case RENDER_PALETTE:

   466 	MMIO_WRITE( PVR2, reg, val&0x00000003 );

   467 	break;

   469 	/********** CRTC registers *************/

   470     case DISP_HBORDER:

   471     case DISP_VBORDER:

   472 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   473 	break;

   474     case DISP_TOTAL:

   475 	val = val & 0x03FF03FF;

   476 	MMIO_WRITE( PVR2, reg, val );

   477 	pvr2_update_raster_posn(sh4r.slice_cycle);

   478 	pvr2_state.total_lines = (val >> 16) + 1;

   479 	pvr2_state.line_size = (val & 0x03FF) + 1;

   480 	pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;

   481 	pvr2_state.retrace_end_line = 0x2A;

   482 	pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;

   483 	pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );

   484 	pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );

   485 	pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,

   486 					  pvr2_state.irq_hpos_time_ns );

   487 	break;

   488     case DISP_SYNCCFG:

   489 	MMIO_WRITE( PVR2, reg, val&0x000003FF );

   490 	pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;

   491 	break;

   492     case DISP_SYNCTIME:

   493 	pvr2_state.vsync_lines = (val >> 8) & 0x0F;

   494 	pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;

   495 	MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );

   496 	break;

   497     case DISP_CFG2:

   498 	MMIO_WRITE( PVR2, reg, val&0x003F01FF );

   499 	break;

   500     case DISP_HPOS:

   501 	val = val & 0x03FF;

   502 	pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;

   503 	MMIO_WRITE( PVR2, reg, val );

   504 	break;

   505     case DISP_VPOS:

   506 	MMIO_WRITE( PVR2, reg, val&0x03FF03FF );

   507 	break;

   509 	/*********** Tile accelerator registers ***********/

   510     case TA_POLYPOS:

   511     case TA_LISTPOS:

   512 	/* Readonly registers */

   513 	break;

   514     case TA_TILEBASE:

   515     case TA_LISTEND:

   516     case TA_LISTBASE:

   517 	MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );

   518 	break;

   519     case RENDER_TILEBASE:

   520     case TA_POLYBASE:

   521     case TA_POLYEND:

   522 	MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );

   523 	break;

   524     case TA_TILESIZE:

   525 	MMIO_WRITE( PVR2, reg, val&0x000F003F );

   526 	break;

   527     case TA_TILECFG:

   528 	MMIO_WRITE( PVR2, reg, val&0x00133333 );

   529 	break;

   530     case TA_INIT:

   531 	if( val & 0x80000000 )

   532 	    pvr2_ta_init();

   533 	break;

   534     case TA_REINIT:

   535 	break;

   536 	/**************** Scaler registers? ****************/

   537     case RENDER_SCALER:

   538 	MMIO_WRITE( PVR2, reg, val&0x0007FFFF );

   539 	break;

   541     case YUV_ADDR:

   542 	val = val & 0x00FFFFF8;

   543 	MMIO_WRITE( PVR2, reg, val );

   544 	pvr2_yuv_init( val );

   545 	break;

   546     case YUV_CFG:

   547 	MMIO_WRITE( PVR2, reg, val&0x01013F3F );

   548 	pvr2_yuv_set_config(val);

   549 	break;

   551 	/**************** Unknowns ***************/

   552     case PVRUNK1:

   553     	MMIO_WRITE( PVR2, reg, val&0x000007FF );

   554     	break;

   555     case PVRUNK2:

   556 	MMIO_WRITE( PVR2, reg, val&0x00000007 );

   557 	break;

   558     case PVRUNK3:

   559 	MMIO_WRITE( PVR2, reg, val&0x000FFF3F );

   560 	break;

   561     case PVRUNK5:

   562 	MMIO_WRITE( PVR2, reg, val&0x0000FFFF );

   563 	break;

   564     case PVRUNK6:

   565 	MMIO_WRITE( PVR2, reg, val&0x000000FF );

   566 	break;

   567     case PVRUNK7:

   568 	MMIO_WRITE( PVR2, reg, val&0x00000001 );

   569 	break;

   570     }

   571 }

   573 /**

   574  * Calculate the current read value of the syncstat register, using

   575  * the current SH4 clock time as an offset from the last timeslice.

   576  * The register reads (LSB to MSB) as:

   577  *     0..9  Current scan line

   578  *     10    Odd/even field (1 = odd, 0 = even)

   579  *     11    Display active (including border and overscan)

   580  *     12    Horizontal sync off

   581  *     13    Vertical sync off

   582  * Note this method is probably incorrect for anything other than straight

   583  * interlaced PAL/NTSC, and needs further testing.

   584  */

   585 uint32_t pvr2_get_sync_status()

   586 {

   587     pvr2_update_raster_posn(sh4r.slice_cycle);

   588     uint32_t result = pvr2_state.line_count;

   590     if( pvr2_state.odd_even_field ) {

   591 	result |= 0x0400;

   592     }

   593     if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {

   594 	if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {

   595 	    result |= 0x1000; /* !HSYNC */

   596 	}

   597 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {

   598 	    if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {

   599 		result |= 0x2800; /* Display active */

   600 	    } else {

   601 		result |= 0x2000; /* Front porch */

   602 	    }

   603 	}

   604     } else {

   605 	if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {

   606 	    if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {

   607 		result |= 0x3800; /* Display active */

   608 	    } else {

   609 		result |= 0x3000;

   610 	    }

   611 	} else {

   612 	    result |= 0x1000; /* Back porch */

   613 	}

   614     }

   615     return result;

   616 }

   618 /**

   619  * Schedule a "scanline" event. This actually goes off at

   620  * 2 * line in even fields and 2 * line + 1 in odd fields.

   621  * Otherwise this behaves as per pvr2_schedule_line_event().

   622  * The raster position should be updated before calling this

   623  * method.

   624  * @param eventid Event to fire at the specified time

   625  * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced

   626  *  displays).

   627  * @param hpos_ns Nanoseconds into the line at which to fire.

   628  */

   629 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )

   630 {

   631     uint32_t field = pvr2_state.odd_even_field;

   632     if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {

   633 	field = !field;

   634     }

   635     if( hpos_ns > pvr2_state.line_time_ns ) {

   636 	hpos_ns = pvr2_state.line_time_ns;

   637     }

   639     line <<= 1;

   640     if( field ) {

   641 	line += 1;

   642     }

   644     if( line < pvr2_state.total_lines ) {

   645 	uint32_t lines;

   646 	uint32_t time;

   647 	if( line <= pvr2_state.line_count ) {

   648 	    lines = (pvr2_state.total_lines - pvr2_state.line_count + line);

   649 	} else {

   650 	    lines = (line - pvr2_state.line_count);

   651 	}

   652 	if( lines <= minimum_lines ) {

   653 	    lines += pvr2_state.total_lines;

   654 	}

   655 	time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;

   656 	event_schedule( eventid, time );

   657     } else {

   658 	event_cancel( eventid );

   659     }

   660 }

   662 MMIO_REGION_READ_FN( PVR2, reg )

   663 {

   664     switch( reg ) {

   665         case DISP_SYNCSTAT:

   666             return pvr2_get_sync_status();

   667         default:

   668             return MMIO_READ( PVR2, reg );

   669     }

   670 }

   672 MMIO_REGION_DEFFNS( PVR2PAL )

   674 void pvr2_set_base_address( uint32_t base )

   675 {

   676     mmio_region_PVR2_write( DISP_ADDR1, base );

   677 }

   682 int32_t mmio_region_PVR2TA_read( uint32_t reg )

   683 {

   684     return 0xFFFFFFFF;

   685 }

   687 void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )

   688 {

   689     pvr2_ta_write( (char *)&val, sizeof(uint32_t) );

   690 }