4 * PVR2 (Video) Core module implementation and MMIO registers.
6 * Copyright (c) 2005 Nathan Keynes.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #define MODULE pvr2_module
27 #include "pvr2/pvr2.h"
28 #include "pvr2/pvr2mmio.h"
29 #include "pvr2/scene.h"
32 #include "pvr2/pvr2mmio.h"
34 unsigned char *video_base;
36 #define MAX_RENDER_BUFFERS 4
38 #define HPOS_PER_FRAME 0
39 #define HPOS_PER_LINECOUNT 1
41 static void pvr2_init( void );
42 static void pvr2_reset( void );
43 static uint32_t pvr2_run_slice( uint32_t );
44 static void pvr2_save_state( FILE *f );
45 static int pvr2_load_state( FILE *f );
46 static void pvr2_update_raster_posn( uint32_t nanosecs );
47 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int line_time_ns );
48 static render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame );
49 static render_buffer_t pvr2_next_render_buffer( );
50 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame );
51 uint32_t pvr2_get_sync_status();
53 void pvr2_display_frame( void );
55 static int output_colour_formats[] = { COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGR888, COLFMT_BGRA8888 };
56 static int render_colour_formats[8] = {
57 COLFMT_BGRA1555, COLFMT_RGB565, COLFMT_BGRA4444, COLFMT_BGRA1555,
58 COLFMT_BGR888, COLFMT_BGRA8888, COLFMT_BGRA8888, COLFMT_BGRA4444 };
61 struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL,
63 pvr2_save_state, pvr2_load_state };
66 display_driver_t display_driver = NULL;
71 uint32_t line_remainder;
72 uint32_t cycles_run; /* Cycles already executed prior to main time slice */
73 uint32_t irq_hpos_line;
74 uint32_t irq_hpos_line_count;
75 uint32_t irq_hpos_mode;
76 uint32_t irq_hpos_time_ns; /* Time within the line */
79 uint32_t odd_even_field; /* 1 = odd, 0 = even */
80 int32_t palette_changed; /* TRUE if palette has changed since last render */
85 uint32_t line_time_ns;
87 uint32_t hsync_width_ns;
88 uint32_t front_porch_ns;
89 uint32_t back_porch_ns;
90 uint32_t retrace_start_line;
91 uint32_t retrace_end_line;
95 static gchar *save_next_render_filename;
96 static render_buffer_t render_buffers[MAX_RENDER_BUFFERS];
97 static uint32_t render_buffer_count = 0;
98 static render_buffer_t displayed_render_buffer = NULL;
99 static uint32_t displayed_border_colour = 0;
102 * Event handler for the hpos callback
104 static void pvr2_hpos_callback( int eventid ) {
105 asic_event( eventid );
106 pvr2_update_raster_posn(sh4r.slice_cycle);
107 if( pvr2_state.irq_hpos_mode == HPOS_PER_LINECOUNT ) {
108 pvr2_state.irq_hpos_line += pvr2_state.irq_hpos_line_count;
109 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
110 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
113 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_hpos_line, 1,
114 pvr2_state.irq_hpos_time_ns );
118 * Event handler for the scanline callbacks. Fires the corresponding
119 * ASIC event, and resets the timer for the next field.
121 static void pvr2_scanline_callback( int eventid )
123 asic_event( eventid );
124 pvr2_update_raster_posn(sh4r.slice_cycle);
125 if( eventid == EVENT_SCANLINE1 ) {
126 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1, 0 );
128 pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1, 0 );
132 static void pvr2_gunpos_callback( int eventid )
134 pvr2_update_raster_posn(sh4r.slice_cycle);
135 int hpos = pvr2_state.line_remainder * pvr2_state.dot_clock / 1000000;
136 MMIO_WRITE( PVR2, GUNPOS, ((pvr2_state.line_count<<16)|(hpos&0x3FF)) );
137 asic_event( EVENT_MAPLE_DMA );
140 static void pvr2_init( void )
143 register_io_region( &mmio_region_PVR2 );
144 register_io_region( &mmio_region_PVR2PAL );
145 register_io_region( &mmio_region_PVR2TA );
146 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
147 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
148 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
149 register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
150 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
154 save_next_render_filename = NULL;
155 for( i=0; i<MAX_RENDER_BUFFERS; i++ ) {
156 render_buffers[i] = NULL;
158 render_buffer_count = 0;
159 displayed_render_buffer = NULL;
160 displayed_border_colour = 0;
163 static void pvr2_reset( void )
166 pvr2_state.line_count = 0;
167 pvr2_state.line_remainder = 0;
168 pvr2_state.cycles_run = 0;
169 pvr2_state.irq_vpos1 = 0;
170 pvr2_state.irq_vpos2 = 0;
171 pvr2_state.dot_clock = PVR2_DOT_CLOCK;
172 pvr2_state.back_porch_ns = 4000;
173 pvr2_state.palette_changed = FALSE;
174 mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F );
175 mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F );
176 mmio_region_PVR2_write( YUV_ADDR, 0 );
177 mmio_region_PVR2_write( YUV_CFG, 0 );
181 if( display_driver ) {
182 display_driver->display_blank(0);
183 for( i=0; i<render_buffer_count; i++ ) {
184 display_driver->destroy_render_buffer(render_buffers[i]);
185 render_buffers[i] = NULL;
187 render_buffer_count = 0;
191 void pvr2_save_render_buffer( FILE *f, render_buffer_t buffer )
193 struct frame_buffer fbuf;
195 fbuf.width = buffer->width;
196 fbuf.height = buffer->height;
197 fbuf.rowstride = fbuf.width*3;
198 fbuf.colour_format = COLFMT_BGR888;
199 fbuf.inverted = buffer->inverted;
200 fbuf.data = g_malloc0( buffer->width * buffer->height * 3 );
202 display_driver->read_render_buffer( fbuf.data, buffer, fbuf.rowstride, COLFMT_BGR888 );
203 write_png_to_stream( f, &fbuf );
206 fwrite( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
207 fwrite( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
208 fwrite( &buffer->address, sizeof(buffer->address), 1, f );
209 fwrite( &buffer->scale, sizeof(buffer->scale), 1, f );
210 int32_t flushed = (int32_t)buffer->flushed; // Force to 32-bits for save-file consistency
211 fwrite( &flushed, sizeof(flushed), 1, f );
215 render_buffer_t pvr2_load_render_buffer( FILE *f, gboolean *status )
217 frame_buffer_t frame = read_png_from_stream( f );
218 if( frame == NULL ) {
224 render_buffer_t buffer = pvr2_frame_buffer_to_render_buffer(frame);
225 if( buffer != NULL ) {
227 fread( &buffer->rowstride, sizeof(buffer->rowstride), 1, f );
228 fread( &buffer->colour_format, sizeof(buffer->colour_format), 1, f );
229 fread( &buffer->address, sizeof(buffer->address), 1, f );
230 fread( &buffer->scale, sizeof(buffer->scale), 1, f );
231 fread( &flushed, sizeof(flushed), 1, f );
232 buffer->flushed = (gboolean)flushed;
234 fseek( f, sizeof(buffer->rowstride)+sizeof(buffer->colour_format)+
235 sizeof(buffer->address)+sizeof(buffer->scale)+
236 sizeof(int32_t), SEEK_CUR );
244 void pvr2_save_render_buffers( FILE *f )
247 uint32_t has_frontbuffer;
248 fwrite( &render_buffer_count, sizeof(render_buffer_count), 1, f );
249 if( displayed_render_buffer != NULL ) {
251 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
252 pvr2_save_render_buffer( f, displayed_render_buffer );
255 fwrite( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
258 for( i=0; i<render_buffer_count; i++ ) {
259 if( render_buffers[i] != displayed_render_buffer && render_buffers[i] != NULL ) {
260 pvr2_save_render_buffer( f, render_buffers[i] );
265 gboolean pvr2_load_render_buffers( FILE *f )
267 uint32_t count, has_frontbuffer;
271 fread( &count, sizeof(count), 1, f );
272 if( count > MAX_RENDER_BUFFERS ) {
275 fread( &has_frontbuffer, sizeof(has_frontbuffer), 1, f );
276 for( i=0; i<render_buffer_count; i++ ) {
277 display_driver->destroy_render_buffer(render_buffers[i]);
278 render_buffers[i] = NULL;
280 render_buffer_count = 0;
282 if( has_frontbuffer ) {
283 displayed_render_buffer = pvr2_load_render_buffer(f, &loadok);
284 if( displayed_render_buffer != NULL )
285 display_driver->display_render_buffer( displayed_render_buffer );
291 for( i=0; i<count; i++ ) {
292 pvr2_load_render_buffer( f, &loadok );
300 static void pvr2_save_state( FILE *f )
302 pvr2_save_render_buffers( f );
303 fwrite( &pvr2_state, sizeof(pvr2_state), 1, f );
304 pvr2_ta_save_state( f );
305 pvr2_yuv_save_state( f );
308 static int pvr2_load_state( FILE *f )
310 if( !pvr2_load_render_buffers(f) )
312 if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 )
314 if( pvr2_ta_load_state(f) ) {
317 return pvr2_yuv_load_state(f);
321 * Update the current raster position to the given number of nanoseconds,
322 * relative to the last time slice. (ie the raster will be adjusted forward
323 * by nanosecs - nanosecs_already_run_this_timeslice)
325 static void pvr2_update_raster_posn( uint32_t nanosecs )
327 uint32_t old_line_count = pvr2_state.line_count;
328 if( pvr2_state.line_time_ns == 0 ) {
329 return; /* do nothing */
331 pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run);
332 pvr2_state.cycles_run = nanosecs;
333 while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) {
334 pvr2_state.line_count ++;
335 pvr2_state.line_remainder -= pvr2_state.line_time_ns;
338 if( pvr2_state.line_count >= pvr2_state.total_lines ) {
339 pvr2_state.line_count -= pvr2_state.total_lines;
340 if( pvr2_state.interlaced ) {
341 pvr2_state.odd_even_field = !pvr2_state.odd_even_field;
344 if( pvr2_state.line_count >= pvr2_state.retrace_end_line &&
345 (old_line_count < pvr2_state.retrace_end_line ||
346 old_line_count > pvr2_state.line_count) ) {
347 pvr2_state.frame_count++;
348 pvr2_display_frame();
352 static uint32_t pvr2_run_slice( uint32_t nanosecs )
354 pvr2_update_raster_posn( nanosecs );
355 pvr2_state.cycles_run = 0;
359 int pvr2_get_frame_count()
361 return pvr2_state.frame_count;
364 void pvr2_redraw_display()
366 if( display_driver != NULL ) {
367 if( displayed_render_buffer == NULL ) {
368 display_driver->display_blank(displayed_border_colour);
370 display_driver->display_render_buffer(displayed_render_buffer);
375 gboolean pvr2_save_next_scene( const gchar *filename )
377 if( save_next_render_filename != NULL ) {
378 g_free( save_next_render_filename );
380 save_next_render_filename = g_strdup(filename);
387 * Display the next frame, copying the current contents of video ram to
388 * the window. If the video configuration has changed, first recompute the
389 * new frame size/depth.
391 void pvr2_display_frame( void )
393 int dispmode = MMIO_READ( PVR2, DISP_MODE );
394 int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG );
395 gboolean bEnabled = (dispmode & DISPMODE_ENABLE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE;
397 if( display_driver == NULL ) {
398 return; /* can't really do anything much */
399 } else if( !bEnabled ) {
400 /* Output disabled == black */
401 displayed_render_buffer = NULL;
402 displayed_border_colour = 0;
403 display_driver->display_blank( 0 );
404 } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) {
405 /* Enabled but blanked - border colour */
406 displayed_border_colour = MMIO_READ( PVR2, DISP_BORDER );
407 displayed_render_buffer = NULL;
408 display_driver->display_blank( displayed_border_colour );
410 /* Real output - determine dimensions etc */
411 struct frame_buffer fbuf;
412 uint32_t dispsize = MMIO_READ( PVR2, DISP_SIZE );
413 int vid_stride = (((dispsize & DISPSIZE_MODULO) >> 20) - 1);
414 int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1;
416 fbuf.colour_format = output_colour_formats[(dispmode & DISPMODE_COLFMT) >> 2];
417 fbuf.width = (vid_ppl << 2) / colour_formats[fbuf.colour_format].bpp;
418 fbuf.height = ((dispsize & DISPSIZE_LPF) >> 10) + 1;
419 fbuf.size = (vid_ppl << 2) * fbuf.height;
420 fbuf.rowstride = (vid_ppl + vid_stride) << 2;
422 /* Determine the field to display, and deinterlace if possible */
423 if( pvr2_state.interlaced ) {
424 if( vid_ppl == vid_stride ) { /* Magic deinterlace */
425 fbuf.height = fbuf.height << 1;
426 fbuf.rowstride = vid_ppl << 2;
427 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
429 /* Just display the field as is, folks. This is slightly tricky -
430 * we pick the field based on which frame is about to come through,
431 * which may not be the same as the odd_even_field.
433 gboolean oddfield = pvr2_state.odd_even_field;
434 if( pvr2_state.line_count >= pvr2_state.retrace_start_line ) {
435 oddfield = !oddfield;
438 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
440 fbuf.address = MMIO_READ( PVR2, DISP_ADDR2 );
444 fbuf.address = MMIO_READ( PVR2, DISP_ADDR1 );
446 fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
447 fbuf.inverted = FALSE;
448 fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
450 render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
452 rbuf = pvr2_frame_buffer_to_render_buffer( &fbuf );
454 displayed_render_buffer = rbuf;
456 display_driver->display_render_buffer( rbuf );
462 * This has to handle every single register individually as they all get masked
463 * off differently (and its easier to do it at write time)
465 MMIO_REGION_WRITE_FN( PVR2, reg, val )
468 if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */
469 MMIO_WRITE( PVR2, reg, val );
476 case GUNPOS: /* Read only registers */
479 val &= 0x00000007; /* Do stuff? */
480 MMIO_WRITE( PVR2, reg, val );
482 case RENDER_START: /* Don't really care what value */
483 if( save_next_render_filename != NULL ) {
484 if( pvr2_render_save_scene(save_next_render_filename) == 0 ) {
485 INFO( "Saved scene to %s", save_next_render_filename);
487 g_free( save_next_render_filename );
488 save_next_render_filename = NULL;
491 render_buffer_t buffer = pvr2_next_render_buffer();
492 if( buffer != NULL ) {
493 pvr2_scene_render( buffer );
494 if( buffer->address < PVR2_RAM_BASE ) {
495 // Flush immediately - optimize this later. Otherwise this gets
496 // complicated very quickly trying to second-guess how it's
497 // going to be used as a texture.
498 pvr2_finish_render_buffer( buffer );
499 pvr2_render_buffer_copy_to_sh4( buffer );
502 asic_event( EVENT_PVR_RENDER_DONE );
504 case RENDER_POLYBASE:
505 MMIO_WRITE( PVR2, reg, val&0x00F00000 );
508 MMIO_WRITE( PVR2, reg, val&0x00010101 );
511 MMIO_WRITE( PVR2, reg, val&0x01FFFFFF );
514 MMIO_WRITE( PVR2, reg, val&0x00FFFF7F );
517 MMIO_WRITE( PVR2, reg, val&0x00FFFF0F );
520 MMIO_WRITE( PVR2, reg, val&0x000001FF );
524 MMIO_WRITE( PVR2, reg, val );
525 pvr2_update_raster_posn(sh4r.slice_cycle);
528 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
529 pvr2_update_raster_posn(sh4r.slice_cycle);
532 MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF );
536 MMIO_WRITE( PVR2, reg, val&0x01FFFFFC );
539 MMIO_WRITE( PVR2, reg, val&0x07FF07FF );
542 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
545 MMIO_WRITE( PVR2, reg, val&0x03FF33FF );
546 pvr2_state.irq_hpos_line = val & 0x03FF;
547 pvr2_state.irq_hpos_time_ns = 2000000*((val>>16)&0x03FF)/pvr2_state.dot_clock;
548 pvr2_state.irq_hpos_mode = (val >> 12) & 0x03;
549 switch( pvr2_state.irq_hpos_mode ) {
550 case 3: /* Reserved - treat as 0 */
551 case 0: /* Once per frame at specified line */
552 pvr2_state.irq_hpos_mode = HPOS_PER_FRAME;
554 case 2: /* Once per line - as per-line-count */
555 pvr2_state.irq_hpos_line = 1;
556 pvr2_state.irq_hpos_mode = 1;
557 case 1: /* Once per N lines */
558 pvr2_state.irq_hpos_line_count = pvr2_state.irq_hpos_line;
559 pvr2_state.irq_hpos_line = (pvr2_state.line_count >> 1) +
560 pvr2_state.irq_hpos_line_count;
561 while( pvr2_state.irq_hpos_line > (pvr2_state.total_lines>>1) ) {
562 pvr2_state.irq_hpos_line -= (pvr2_state.total_lines>>1);
564 pvr2_state.irq_hpos_mode = HPOS_PER_LINECOUNT;
566 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
567 pvr2_state.irq_hpos_time_ns );
570 val = val & 0x03FF03FF;
571 pvr2_state.irq_vpos1 = (val >> 16);
572 pvr2_state.irq_vpos2 = val & 0x03FF;
573 pvr2_update_raster_posn(sh4r.slice_cycle);
574 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
575 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
576 MMIO_WRITE( PVR2, reg, val );
578 case RENDER_NEARCLIP:
579 MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF );
582 MMIO_WRITE( PVR2, reg, val&0x000001FF );
585 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
588 MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF );
591 MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 );
594 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
597 MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 );
600 MMIO_WRITE( PVR2, reg, val&0x000000FF );
603 MMIO_WRITE( PVR2, reg, val&0x003FFFFF );
606 MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF );
608 case RENDER_FOGTBLCOL:
609 case RENDER_FOGVRTCOL:
610 MMIO_WRITE( PVR2, reg, val&0x00FFFFFF );
612 case RENDER_FOGCOEFF:
613 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
617 MMIO_WRITE( PVR2, reg, val );
620 MMIO_WRITE( PVR2, reg, val&0x00031F1F );
623 MMIO_WRITE( PVR2, reg, val&0x00000003 );
625 case RENDER_ALPHA_REF:
626 MMIO_WRITE( PVR2, reg, val&0x000000FF );
628 /********** CRTC registers *************/
631 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
634 val = val & 0x03FF03FF;
635 MMIO_WRITE( PVR2, reg, val );
636 pvr2_update_raster_posn(sh4r.slice_cycle);
637 pvr2_state.total_lines = (val >> 16) + 1;
638 pvr2_state.line_size = (val & 0x03FF) + 1;
639 pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock;
640 pvr2_state.retrace_end_line = 0x2A;
641 pvr2_state.retrace_start_line = pvr2_state.total_lines - 6;
642 pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0, 0 );
643 pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0, 0 );
644 pvr2_schedule_scanline_event( EVENT_HPOS, pvr2_state.irq_hpos_line, 0,
645 pvr2_state.irq_hpos_time_ns );
648 MMIO_WRITE( PVR2, reg, val&0x000003FF );
649 pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE;
652 pvr2_state.vsync_lines = (val >> 8) & 0x0F;
653 pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock;
654 MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F );
657 MMIO_WRITE( PVR2, reg, val&0x003F01FF );
661 pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock;
662 MMIO_WRITE( PVR2, reg, val );
665 MMIO_WRITE( PVR2, reg, val&0x03FF03FF );
668 /*********** Tile accelerator registers ***********/
671 /* Readonly registers */
676 MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 );
678 case RENDER_TILEBASE:
681 MMIO_WRITE( PVR2, reg, val&0x00FFFFFC );
684 MMIO_WRITE( PVR2, reg, val&0x000F003F );
687 MMIO_WRITE( PVR2, reg, val&0x00133333 );
690 if( val & 0x80000000 )
695 /**************** Scaler registers? ****************/
697 MMIO_WRITE( PVR2, reg, val&0x0007FFFF );
701 val = val & 0x00FFFFF8;
702 MMIO_WRITE( PVR2, reg, val );
703 pvr2_yuv_init( val );
706 MMIO_WRITE( PVR2, reg, val&0x01013F3F );
707 pvr2_yuv_set_config(val);
710 /**************** Unknowns ***************/
712 MMIO_WRITE( PVR2, reg, val&0x000007FF );
715 MMIO_WRITE( PVR2, reg, val&0x00000007 );
718 MMIO_WRITE( PVR2, reg, val&0x000FFF3F );
721 MMIO_WRITE( PVR2, reg, val&0x0000FFFF );
724 MMIO_WRITE( PVR2, reg, val&0x00000001 );
727 MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
733 * Calculate the current read value of the syncstat register, using
734 * the current SH4 clock time as an offset from the last timeslice.
735 * The register reads (LSB to MSB) as:
736 * 0..9 Current scan line
737 * 10 Odd/even field (1 = odd, 0 = even)
738 * 11 Display active (including border and overscan)
739 * 12 Horizontal sync off
740 * 13 Vertical sync off
741 * Note this method is probably incorrect for anything other than straight
742 * interlaced PAL/NTSC, and needs further testing.
744 uint32_t pvr2_get_sync_status()
746 pvr2_update_raster_posn(sh4r.slice_cycle);
747 uint32_t result = pvr2_state.line_count;
749 if( pvr2_state.odd_even_field ) {
752 if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) {
753 if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) {
754 result |= 0x1000; /* !HSYNC */
756 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
757 if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) {
758 result |= 0x2800; /* Display active */
760 result |= 0x2000; /* Front porch */
764 if( pvr2_state.line_count >= pvr2_state.vsync_lines ) {
765 if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) {
766 result |= 0x3800; /* Display active */
771 result |= 0x1000; /* Back porch */
778 * Schedule a "scanline" event. This actually goes off at
779 * 2 * line in even fields and 2 * line + 1 in odd fields.
780 * Otherwise this behaves as per pvr2_schedule_line_event().
781 * The raster position should be updated before calling this
783 * @param eventid Event to fire at the specified time
784 * @param line Line on which to fire the event (this is 2n/2n+1 for interlaced
786 * @param hpos_ns Nanoseconds into the line at which to fire.
788 static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines, int hpos_ns )
790 uint32_t field = pvr2_state.odd_even_field;
791 if( line <= pvr2_state.line_count && pvr2_state.interlaced ) {
794 if( hpos_ns > pvr2_state.line_time_ns ) {
795 hpos_ns = pvr2_state.line_time_ns;
803 if( line < pvr2_state.total_lines ) {
806 if( line <= pvr2_state.line_count ) {
807 lines = (pvr2_state.total_lines - pvr2_state.line_count + line);
809 lines = (line - pvr2_state.line_count);
811 if( lines <= minimum_lines ) {
812 lines += pvr2_state.total_lines;
814 time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder + hpos_ns;
815 event_schedule( eventid, time );
817 event_cancel( eventid );
821 void pvr2_queue_gun_event( int xpos, int ypos )
823 pvr2_update_raster_posn(sh4r.slice_cycle);
824 pvr2_schedule_scanline_event( EVENT_GUNPOS, (ypos >> 1) + pvr2_state.vsync_lines, 0,
825 (1000000 * xpos / pvr2_state.dot_clock) + pvr2_state.hsync_width_ns );
828 MMIO_REGION_READ_FN( PVR2, reg )
833 return pvr2_get_sync_status();
835 return MMIO_READ( PVR2, reg );
839 MMIO_REGION_WRITE_FN( PVR2PAL, reg, val )
842 MMIO_WRITE( PVR2PAL, reg, val );
843 pvr2_state.palette_changed = TRUE;
846 void pvr2_check_palette_changed()
848 if( pvr2_state.palette_changed ) {
849 texcache_invalidate_palette();
850 pvr2_state.palette_changed = FALSE;
854 MMIO_REGION_READ_DEFFN( PVR2PAL );
856 void pvr2_set_base_address( uint32_t base )
858 mmio_region_PVR2_write( DISP_ADDR1, base );
864 MMIO_REGION_READ_FN( PVR2TA, reg )
869 MMIO_REGION_WRITE_FN( PVR2TA, reg, val )
871 pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
874 render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
876 if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
877 render_buffer_t buffer = display_driver->create_render_buffer(width,height,tex_id);
878 buffer->address = addr;
884 void pvr2_destroy_render_buffer( render_buffer_t buffer )
886 if( !buffer->flushed )
887 pvr2_render_buffer_copy_to_sh4( buffer );
888 display_driver->destroy_render_buffer( buffer );
891 void pvr2_finish_render_buffer( render_buffer_t buffer )
893 display_driver->finish_render( buffer );
897 * Find the render buffer corresponding to the requested output frame
898 * (does not consider texture renders).
899 * @return the render_buffer if found, or null if no such buffer.
901 * Note: Currently does not consider "partial matches", ie partial
902 * frame overlap - it probably needs to do this.
904 render_buffer_t pvr2_get_render_buffer( frame_buffer_t frame )
907 for( i=0; i<render_buffer_count; i++ ) {
908 if( render_buffers[i] != NULL && render_buffers[i]->address == frame->address ) {
909 return render_buffers[i];
916 * Allocate a render buffer with the requested parameters.
917 * The order of preference is:
918 * 1. An existing buffer with the same address. (not flushed unless the new
919 * size is smaller than the old one).
920 * 2. An existing buffer with the same size chosen by LRU order. Old buffer
921 * is flushed to vram.
922 * 3. A new buffer if one can be created.
923 * 4. The current display buff
924 * Note: The current display field(s) will never be overwritten except as a last
927 render_buffer_t pvr2_alloc_render_buffer( sh4addr_t render_addr, int width, int height )
930 render_buffer_t result = NULL;
932 /* Check existing buffers for an available buffer */
933 for( i=0; i<render_buffer_count; i++ ) {
934 if( render_buffers[i]->width == width && render_buffers[i]->height == height ) {
935 /* needs to be the right dimensions */
936 if( render_buffers[i]->address == render_addr ) {
937 if( displayed_render_buffer == render_buffers[i] ) {
938 /* Same address, but we can't use it because the
939 * display has it. Mark it as unaddressed for later.
941 render_buffers[i]->address = -1;
944 result = render_buffers[i];
947 } else if( render_buffers[i]->address == -1 && result == NULL &&
948 displayed_render_buffer != render_buffers[i] ) {
949 result = render_buffers[i];
952 } else if( render_buffers[i]->address == render_addr ) {
953 /* right address, wrong size - if it's larger, flush it, otherwise
955 if( render_buffers[i]->width * render_buffers[i]->height >
957 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
959 render_buffers[i]->address = -1;
963 /* Nothing available - make one */
964 if( result == NULL ) {
965 if( render_buffer_count == MAX_RENDER_BUFFERS ) {
966 /* maximum buffers reached - need to throw one away */
967 uint32_t field1_addr = MMIO_READ( PVR2, DISP_ADDR1 );
968 uint32_t field2_addr = MMIO_READ( PVR2, DISP_ADDR2 );
969 for( i=0; i<render_buffer_count; i++ ) {
970 if( render_buffers[i]->address != field1_addr &&
971 render_buffers[i]->address != field2_addr &&
972 render_buffers[i] != displayed_render_buffer ) {
973 /* Never throw away the current "front buffer(s)" */
974 result = render_buffers[i];
975 if( !result->flushed && result->address != -1 ) {
976 pvr2_render_buffer_copy_to_sh4( result );
978 if( result->width != width || result->height != height ) {
979 display_driver->destroy_render_buffer(render_buffers[i]);
980 result = display_driver->create_render_buffer(width,height,0);
981 render_buffers[i] = result;
987 result = display_driver->create_render_buffer(width,height,0);
988 if( result != NULL ) {
989 render_buffers[render_buffer_count++] = result;
994 if( result != NULL ) {
995 result->address = render_addr;
1001 * Allocate a render buffer based on the current rendering settings
1003 render_buffer_t pvr2_next_render_buffer()
1005 render_buffer_t result = NULL;
1006 uint32_t render_addr = MMIO_READ( PVR2, RENDER_ADDR1 );
1007 uint32_t render_mode = MMIO_READ( PVR2, RENDER_MODE );
1008 uint32_t render_scale = MMIO_READ( PVR2, RENDER_SCALER );
1009 uint32_t render_stride = MMIO_READ( PVR2, RENDER_SIZE ) << 3;
1011 int width = pvr2_scene_buffer_width();
1012 int height = pvr2_scene_buffer_height();
1013 int colour_format = render_colour_formats[render_mode&0x07];
1015 if( render_addr & 0x01000000 ) { /* vram64 */
1016 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE_INT;
1017 } else { /* vram32 */
1018 render_addr = (render_addr & 0x00FFFFFF) + PVR2_RAM_BASE;
1020 result = pvr2_alloc_render_buffer( render_addr, width, height );
1022 /* Setup the buffer */
1023 if( result != NULL ) {
1024 result->rowstride = render_stride;
1025 result->colour_format = colour_format;
1026 result->scale = render_scale;
1027 result->size = width * height * colour_formats[colour_format].bpp;
1028 result->flushed = FALSE;
1029 result->inverted = TRUE; // render buffers are inverted normally
1034 static render_buffer_t pvr2_frame_buffer_to_render_buffer( frame_buffer_t frame )
1036 render_buffer_t result = pvr2_alloc_render_buffer( frame->address, frame->width, frame->height );
1037 if( result != NULL ) {
1038 int bpp = colour_formats[frame->colour_format].bpp;
1039 result->rowstride = frame->rowstride;
1040 result->colour_format = frame->colour_format;
1041 result->scale = 0x400;
1042 result->size = frame->width * frame->height * bpp;
1043 result->flushed = TRUE;
1044 result->inverted = frame->inverted;
1045 display_driver->load_frame_buffer( frame, result );
1052 * Invalidate any caching on the supplied address. Specifically, if it falls
1053 * within any of the render buffers, flush the buffer back to PVR2 ram.
1055 gboolean pvr2_render_buffer_invalidate( sh4addr_t address, gboolean isWrite )
1058 address = address & 0x1FFFFFFF;
1059 for( i=0; i<render_buffer_count; i++ ) {
1060 uint32_t bufaddr = render_buffers[i]->address;
1061 if( bufaddr != -1 && bufaddr <= address &&
1062 (bufaddr + render_buffers[i]->size) > address ) {
1063 if( !render_buffers[i]->flushed ) {
1064 pvr2_render_buffer_copy_to_sh4( render_buffers[i] );
1067 render_buffers[i]->address = -1; /* Invalid */
1069 return TRUE; /* should never have overlapping buffers */
.