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lxdream.org :: lxdream/src/sh4/sh4.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/sh4.c
changeset 929:fd8cb0c82f5f
prev905:4c17ebd9ef5e
next930:07e5b11419db
author nkeynes
date Sat Dec 20 03:01:40 2008 +0000 (12 years ago)
branchlxdream-mem
permissions -rw-r--r--
last change First pass experiment using cached decoding.
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     1 /**
     2  * $Id$
     3  * 
     4  * SH4 parent module for all CPU modes and SH4 peripheral
     5  * modules.
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #define MODULE sh4_module
    21 #include <math.h>
    22 #include <setjmp.h>
    23 #include <assert.h>
    24 #include "lxdream.h"
    25 #include "dreamcast.h"
    26 #include "mem.h"
    27 #include "clock.h"
    28 #include "eventq.h"
    29 #include "syscall.h"
    30 #include "sh4/intc.h"
    31 #include "sh4/sh4core.h"
    32 #include "sh4/sh4mmio.h"
    33 #include "sh4/sh4stat.h"
    34 #include "sh4/sh4trans.h"
    35 #include "sh4/xltcache.h"
    37 void sh4_init( void );
    38 void sh4_xlat_init( void );
    39 void sh4_reset( void );
    40 void sh4_start( void );
    41 void sh4_stop( void );
    42 void sh4_save_state( FILE *f );
    43 int sh4_load_state( FILE *f );
    44 static void sh4_reset_pointer_cache();
    46 uint32_t sh4_run_slice( uint32_t );
    47 uint32_t sh4_xlat_run_slice( uint32_t );
    49 struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
    50         sh4_start, sh4_run_slice, sh4_stop,
    51         sh4_save_state, sh4_load_state };
    53 struct sh4_registers sh4r __attribute__((aligned(16)));
    54 struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    55 int sh4_breakpoint_count = 0;
    56 sh4ptr_t sh4_main_ram;
    57 sh4ptr_t dc_boot_rom;
    58 sh4ptr_t dc_flash_ram;
    59 sh4ptr_t dc_audio_ram;
    61 gboolean sh4_starting = FALSE;
    62 static gboolean sh4_use_translator = FALSE;
    63 static jmp_buf sh4_exit_jmp_buf;
    64 static gboolean sh4_running = FALSE;
    65 struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
    67 void sh4_translate_set_enabled( gboolean use )
    68 {
    69     // No-op if the translator was not built
    70 #ifdef SH4_TRANSLATOR
    71     xlat_cache_init();
    72     if( use ) {
    73         sh4_translate_init();
    74     }
    75     sh4_use_translator = use;
    76 #endif
    77 }
    79 gboolean sh4_translate_is_enabled()
    80 {
    81     return sh4_use_translator;
    82 }
    84 void sh4_init(void)
    85 {
    86     register_io_regions( mmio_list_sh4mmio );
    87     sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
    88     dc_boot_rom = mem_get_region_by_name(MEM_REGION_BIOS);
    89     dc_flash_ram = mem_get_region_by_name(MEM_REGION_FLASH);
    90     dc_audio_ram = mem_get_region_by_name(MEM_REGION_AUDIO);
    91     MMU_init();
    92     TMU_init();
    93     sh4_reset();
    94 #ifdef ENABLE_SH4STATS
    95     sh4_stats_reset();
    96 #endif
    97 }
    99 void sh4_start(void)
   100 {
   101     sh4_starting = TRUE;
   102 }
   104 void sh4_reset(void)
   105 {
   106     if(	sh4_use_translator ) {
   107         xlat_flush_cache();
   108     }
   110     /* zero everything out, for the sake of having a consistent state. */
   111     memset( &sh4r, 0, sizeof(sh4r) );
   112     sh4_reset_pointer_cache();
   114     /* Resume running if we were halted */
   115     sh4r.sh4_state = SH4_STATE_RUNNING;
   117     sh4r.pc    = 0xA0000000;
   118     sh4r.new_pc= 0xA0000002;
   119     sh4r.vbr   = 0x00000000;
   120     sh4r.fpscr = 0x00040001;
   121     sh4r.sr    = 0x700000F0;
   123     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
   124     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
   126     /* Peripheral modules */
   127     CPG_reset();
   128     INTC_reset();
   129     MMU_reset();
   130     PMM_reset();
   131     TMU_reset();
   132     SCIF_reset();
   134 #ifdef ENABLE_SH4STATS
   135     sh4_stats_reset();
   136 #endif
   137 }
   139 void sh4_stop(void)
   140 {
   141     if(	sh4_use_translator ) {
   142         /* If we were running with the translator, update new_pc and in_delay_slot */
   143         sh4r.new_pc = sh4r.pc+2;
   144         sh4r.in_delay_slot = FALSE;
   145     }
   147 }
   149 /**
   150  * Execute a timeslice using translated code only (ie translate/execute loop)
   151  */
   152 uint32_t sh4_run_slice( uint32_t nanosecs ) 
   153 {
   154     sh4r.slice_cycle = 0;
   156     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
   157         sh4_sleep_run_slice(nanosecs);
   158     }
   160     /* Setup for sudden vm exits */
   161     switch( setjmp(sh4_exit_jmp_buf) ) {
   162     case CORE_EXIT_BREAKPOINT:
   163         sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
   164         /* fallthrough */
   165     case CORE_EXIT_HALT:
   166         if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   167             TMU_run_slice( sh4r.slice_cycle );
   168             SCIF_run_slice( sh4r.slice_cycle );
   169             PMM_run_slice( sh4r.slice_cycle );
   170             dreamcast_stop();
   171             return sh4r.slice_cycle;
   172         }
   173     case CORE_EXIT_SYSRESET:
   174         dreamcast_reset();
   175         break;
   176     case CORE_EXIT_SLEEP:
   177         sh4_sleep_run_slice(nanosecs);
   178         break;  
   179     case CORE_EXIT_FLUSH_ICACHE:
   180 #ifdef SH4_TRANSLATOR
   181         xlat_flush_cache();
   182 #endif
   183         break;
   184     }
   186     sh4_running = TRUE;
   188     /* Execute the core's real slice */
   189 #ifdef SH4_TRANSLATOR
   190     if( sh4_use_translator ) {
   191         sh4_translate_run_slice(nanosecs);
   192     } else {
   193         sh4_emulate_run_slice(nanosecs);
   194     }
   195 #else
   196     sh4_emulate_run_slice(nanosecs);
   197 #endif
   199     /* And finish off the peripherals afterwards */
   201     sh4_running = FALSE;
   202     sh4_starting = FALSE;
   203     sh4r.slice_cycle = nanosecs;
   204     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
   205         TMU_run_slice( nanosecs );
   206         SCIF_run_slice( nanosecs );
   207         PMM_run_slice( sh4r.slice_cycle );
   208     }
   209     return nanosecs;   
   210 }
   212 void sh4_core_exit( int exit_code )
   213 {
   214     if( sh4_running ) {
   215 #ifdef SH4_TRANSLATOR
   216         if( sh4_use_translator ) {
   217             sh4_translate_exit_recover();
   218         }
   219 #endif
   220         // longjmp back into sh4_run_slice
   221         sh4_running = FALSE;
   222         longjmp(sh4_exit_jmp_buf, exit_code);
   223     }
   224 }
   226 void sh4_flush_icache()
   227 {
   228 #ifdef SH4_TRANSLATOR
   229     // FIXME: Special case needs to be generalized
   230     if( sh4_use_translator ) {
   231         if( sh4_translate_flush_cache() ) {
   232             longjmp(sh4_exit_jmp_buf, CORE_EXIT_CONTINUE);
   233         }
   234     }
   235 #endif
   236 }
   238 void sh4_save_state( FILE *f )
   239 {
   240     if(	sh4_use_translator ) {
   241         /* If we were running with the translator, update new_pc and in_delay_slot */
   242         sh4r.new_pc = sh4r.pc+2;
   243         sh4r.in_delay_slot = FALSE;
   244     }
   246     int len = ((char *)&sh4r.pointer_cache) - ((char *)&sh4r);
   247     fwrite( &sh4r, len, 1, f );
   248     MMU_save_state( f );
   249     PMM_save_state( f );
   250     INTC_save_state( f );
   251     TMU_save_state( f );
   252     SCIF_save_state( f );
   253 }
   255 int sh4_load_state( FILE * f )
   256 {
   257     if(	sh4_use_translator ) {
   258         xlat_flush_cache();
   259     }
   260     int len = ((char *)&sh4r.pointer_cache) - ((char *)&sh4r);
   261     fread( &sh4r, len, 1, f );
   262     sh4_reset_pointer_cache();
   263     MMU_load_state( f );
   264     PMM_load_state( f );
   265     INTC_load_state( f );
   266     TMU_load_state( f );
   267     return SCIF_load_state( f );
   268 }
   270 static void sh4_reset_pointer_cache()
   271 {
   272     int i;
   273     for( i=0; i<16; i++ ) {
   274         sh4r.pointer_cache[i].page_vma = -1;
   275         sh4r.pointer_cache[i].page_mask = 0xFFFFF000;
   276     }
   277     sh4r.pointer_cache[16].page_vma = -1;
   278     sh4r.pointer_cache[16].page_mask = 0xFFFFF000;
   279 }
   281 void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
   282 {
   283     sh4_breakpoints[sh4_breakpoint_count].address = pc;
   284     sh4_breakpoints[sh4_breakpoint_count].type = type;
   285     if( sh4_use_translator ) {
   286         xlat_invalidate_word( pc );
   287     }
   288     sh4_breakpoint_count++;
   289 }
   291 gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
   292 {
   293     int i;
   295     for( i=0; i<sh4_breakpoint_count; i++ ) {
   296         if( sh4_breakpoints[i].address == pc && 
   297                 sh4_breakpoints[i].type == type ) {
   298             while( ++i < sh4_breakpoint_count ) {
   299                 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
   300                 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
   301             }
   302             if( sh4_use_translator ) {
   303                 xlat_invalidate_word( pc );
   304             }
   305             sh4_breakpoint_count--;
   306             return TRUE;
   307         }
   308     }
   309     return FALSE;
   310 }
   312 int sh4_get_breakpoint( uint32_t pc )
   313 {
   314     int i;
   315     for( i=0; i<sh4_breakpoint_count; i++ ) {
   316         if( sh4_breakpoints[i].address == pc )
   317             return sh4_breakpoints[i].type;
   318     }
   319     return 0;
   320 }
   322 void sh4_set_pc( int pc )
   323 {
   324     sh4r.pc = pc;
   325     sh4r.new_pc = pc+2;
   326 }
   329 /******************************* Support methods ***************************/
   331 static void sh4_switch_banks( )
   332 {
   333     uint32_t tmp[8];
   335     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
   336     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
   337     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
   338 }
   340 void FASTCALL sh4_switch_fr_banks()
   341 {
   342     int i;
   343     for( i=0; i<16; i++ ) {
   344         float tmp = sh4r.fr[0][i];
   345         sh4r.fr[0][i] = sh4r.fr[1][i];
   346         sh4r.fr[1][i] = tmp;
   347     }
   348 }
   350 void FASTCALL sh4_write_sr( uint32_t newval )
   351 {
   352     int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
   353     int newbank = (newval&SR_MDRB) == SR_MDRB;
   354     if( oldbank != newbank )
   355         sh4_switch_banks();
   356     sh4r.sr = newval & SR_MASK;
   357     sh4r.t = (newval&SR_T) ? 1 : 0;
   358     sh4r.s = (newval&SR_S) ? 1 : 0;
   359     sh4r.m = (newval&SR_M) ? 1 : 0;
   360     sh4r.q = (newval&SR_Q) ? 1 : 0;
   361     intc_mask_changed();
   362 }
   364 void FASTCALL sh4_write_fpscr( uint32_t newval )
   365 {
   366     if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
   367         sh4_switch_fr_banks();
   368     }
   369     sh4r.fpscr = newval & FPSCR_MASK;
   370 }
   372 uint32_t FASTCALL sh4_read_sr( void )
   373 {
   374     /* synchronize sh4r.sr with the various bitflags */
   375     sh4r.sr &= SR_MQSTMASK;
   376     if( sh4r.t ) sh4r.sr |= SR_T;
   377     if( sh4r.s ) sh4r.sr |= SR_S;
   378     if( sh4r.m ) sh4r.sr |= SR_M;
   379     if( sh4r.q ) sh4r.sr |= SR_Q;
   380     return sh4r.sr;
   381 }
   385 #define RAISE( x, v ) do{			\
   386     if( sh4r.vbr == 0 ) { \
   387         ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \
   388         sh4_core_exit(CORE_EXIT_HALT); return FALSE;	\
   389     } else { \
   390         sh4r.spc = sh4r.pc;	\
   391         sh4r.ssr = sh4_read_sr(); \
   392         sh4r.sgr = sh4r.r[15]; \
   393         MMIO_WRITE(MMU,EXPEVT,x); \
   394         sh4r.pc = sh4r.vbr + v; \
   395         sh4r.new_pc = sh4r.pc + 2; \
   396         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \
   397         if( sh4r.in_delay_slot ) { \
   398             sh4r.in_delay_slot = 0; \
   399             sh4r.spc -= 2; \
   400         } \
   401     } \
   402     return TRUE; } while(0)
   404 /**
   405  * Raise a general CPU exception for the specified exception code.
   406  * (NOT for TRAPA or TLB exceptions)
   407  */
   408 gboolean FASTCALL sh4_raise_exception( int code )
   409 {
   410     RAISE( code, EXV_EXCEPTION );
   411 }
   413 /**
   414  * Raise a CPU reset exception with the specified exception code.
   415  */
   416 gboolean FASTCALL sh4_raise_reset( int code )
   417 {
   418     // FIXME: reset modules as per "manual reset"
   419     sh4_reset();
   420     MMIO_WRITE(MMU,EXPEVT,code);
   421     sh4r.vbr = 0;
   422     sh4r.pc = 0xA0000000;
   423     sh4r.new_pc = sh4r.pc + 2;
   424     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)
   425                   &(~SR_FD) );
   426     return TRUE;
   427 }
   429 gboolean FASTCALL sh4_raise_trap( int trap )
   430 {
   431     MMIO_WRITE( MMU, TRA, trap<<2 );
   432     RAISE( EXC_TRAP, EXV_EXCEPTION );
   433 }
   435 gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
   436     if( sh4r.in_delay_slot ) {
   437         return sh4_raise_exception(slot_code);
   438     } else {
   439         return sh4_raise_exception(normal_code);
   440     }
   441 }
   443 gboolean FASTCALL sh4_raise_tlb_exception( int code )
   444 {
   445     RAISE( code, EXV_TLBMISS );
   446 }
   448 void FASTCALL sh4_accept_interrupt( void )
   449 {
   450     uint32_t code = intc_accept_interrupt();
   451     sh4r.ssr = sh4_read_sr();
   452     sh4r.spc = sh4r.pc;
   453     sh4r.sgr = sh4r.r[15];
   454     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
   455     MMIO_WRITE( MMU, INTEVT, code );
   456     sh4r.pc = sh4r.vbr + 0x600;
   457     sh4r.new_pc = sh4r.pc + 2;
   458     //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
   459 }
   461 void FASTCALL signsat48( void )
   462 {
   463     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
   464         sh4r.mac = 0xFFFF800000000000LL;
   465     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
   466         sh4r.mac = 0x00007FFFFFFFFFFFLL;
   467 }
   469 void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
   470 {
   471     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   472     *fr++ = cosf(angle);
   473     *fr = sinf(angle);
   474 }
   476 /**
   477  * Enter sleep mode (eg by executing a SLEEP instruction).
   478  * Sets sh4_state appropriately and ensures any stopping peripheral modules
   479  * are up to date.
   480  */
   481 void FASTCALL sh4_sleep(void)
   482 {
   483     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   484         sh4r.sh4_state = SH4_STATE_STANDBY;
   485         /* Bring all running peripheral modules up to date, and then halt them. */
   486         TMU_run_slice( sh4r.slice_cycle );
   487         SCIF_run_slice( sh4r.slice_cycle );
   488         PMM_run_slice( sh4r.slice_cycle );
   489     } else {
   490         if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
   491             sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
   492             /* Halt DMAC but other peripherals still running */
   494         } else {
   495             sh4r.sh4_state = SH4_STATE_SLEEP;
   496         }
   497     }
   498     sh4_core_exit( CORE_EXIT_SLEEP );
   499 }
   501 /**
   502  * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
   503  * and restarts any peripheral devices that were stopped.
   504  */
   505 void sh4_wakeup(void)
   506 {
   507     switch( sh4r.sh4_state ) {
   508     case SH4_STATE_STANDBY:
   509         break;
   510     case SH4_STATE_DEEP_SLEEP:
   511         break;
   512     case SH4_STATE_SLEEP:
   513         break;
   514     }
   515     sh4r.sh4_state = SH4_STATE_RUNNING;
   516 }
   518 /**
   519  * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
   520  * Returns when either the SH4 wakes up (interrupt received) or the end of
   521  * the slice is reached. Updates sh4.slice_cycle with the exit time and
   522  * returns the same value.
   523  */
   524 uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
   525 {
   526     int sleep_state = sh4r.sh4_state;
   527     assert( sleep_state != SH4_STATE_RUNNING );
   529     while( sh4r.event_pending < nanosecs ) {
   530         sh4r.slice_cycle = sh4r.event_pending;
   531         if( sh4r.event_types & PENDING_EVENT ) {
   532             event_execute();
   533         }
   534         if( sh4r.event_types & PENDING_IRQ ) {
   535             sh4_wakeup();
   536             return sh4r.slice_cycle;
   537         }
   538     }
   539     sh4r.slice_cycle = nanosecs;
   540     return sh4r.slice_cycle;
   541 }
   544 /**
   545  * Compute the matrix tranform of fv given the matrix xf.
   546  * Both fv and xf are word-swapped as per the sh4r.fr banks
   547  */
   548 void FASTCALL sh4_ftrv( float *target )
   549 {
   550     float fv[4] = { target[1], target[0], target[3], target[2] };
   551     target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
   552     sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
   553     target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
   554     sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
   555     target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
   556     sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
   557     target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
   558     sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
   559 }
   561 gboolean sh4_has_page( sh4vma_t vma )
   562 {
   563     sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
   564     return addr != MMU_VMA_ERROR && mem_has_page(addr);
   565 }
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