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lxdream.org :: lxdream/src/sh4/scif.c
lxdream 0.9.1
released Jun 29
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filename src/sh4/scif.c
changeset 21:fda269b432a7
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author nkeynes
date Thu Dec 22 13:52:02 2005 +0000 (15 years ago)
permissions -rw-r--r--
last change Implement status clearing correctly
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     1 /**
     2  * $Id: scif.c,v 1.2 2005-12-22 13:52:02 nkeynes Exp $
     3  * SCIF (Serial Communication Interface with FIFO) implementation - part of the 
     4  * SH4 standard on-chip peripheral set. The SCIF is hooked up to the DCs
     5  * external serial port
     6  *
     7  * Copyright (c) 2005 Nathan Keynes.
     8  *
     9  * This program is free software; you can redistribute it and/or modify
    10  * it under the terms of the GNU General Public License as published by
    11  * the Free Software Foundation; either version 2 of the License, or
    12  * (at your option) any later version.
    13  *
    14  * This program is distributed in the hope that it will be useful,
    15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    17  * GNU General Public License for more details.
    18  */
    20 #include <glib.h>
    21 #include "dream.h"
    22 #include "mem.h"
    23 #include "sh4core.h"
    24 #include "sh4mmio.h"
    25 #include "intc.h"
    26 #include "clock.h"
    27 #include "serial.h"
    28 #include "modules.h"
    30 void SCIF_set_break(void);
    32 /************************* External serial interface ************************/
    34 /**
    35  * Note: serial_* operations are called from outside the SH4, and as such are
    36  * named relative to the external serial device. SCIF_* operations are only
    37  * called internally to the SH4 and so are named relative to the CPU.
    38  */
    40 /**
    41  * Storage space for inbound/outbound data blocks. It's a little more
    42  * convenient for serial consumers to be able to deal with block-sized pieces
    43  * rather than a byte at a time, even if it makes all this look rather
    44  * complicated.
    45  *
    46  * Currently there's no limit on the number of blocks that can be queued up.
    47  */
    48 typedef struct serial_data_block {
    49     uint32_t length;
    50     uint32_t offset;
    51     struct serial_data_block *next;
    52     char data[];
    53 } *serial_data_block_t;
    55 serial_data_block_t serial_recvq_head = NULL, serial_recvq_tail = NULL;
    56 serial_device_t serial_device = NULL;
    58 void serial_attach_device( serial_device_t dev ) 
    59 {
    60     if( serial_device != NULL )
    61 	serial_detach_device();
    62     serial_device = dev;
    63 }
    66 void serial_detach_device( void )
    67 {
    68     serial_device = NULL;
    69 }
    71 /**
    72  * Add a block of data to the serial receive queue. The data will be received
    73  * by the CPU at the appropriate baud rate.
    74  */
    75 void serial_transmit_data( char *data, int length ) {
    76     if( length == 0 )
    77 	return;
    78     serial_data_block_t block = 
    79 	g_malloc( sizeof( struct serial_data_block ) + length );
    80     block->length = length;
    81     block->offset = 0;
    82     block->next = NULL;
    83     memcpy( block->data, data, length );
    85     if( serial_recvq_head == NULL ) {
    86 	serial_recvq_head = serial_recvq_tail = block;
    87     } else {
    88 	serial_recvq_tail->next = block;
    89 	serial_recvq_tail = block;
    90     }
    91 }
    93 /**
    94  * Dequeue a byte from the serial input queue
    95  */
    96 static int serial_transmit_dequeue( ) {
    97     if( serial_recvq_head != NULL ) {
    98 	uint8_t val = serial_recvq_head->data[serial_recvq_head->offset++];
    99 	if( serial_recvq_head->offset >= serial_recvq_head->length ) {
   100 	    serial_data_block_t next = serial_recvq_head->next;
   101 	    g_free( serial_recvq_head );
   102 	    serial_recvq_head = next;
   103 	    if( next == NULL )
   104 		serial_recvq_tail = NULL;
   105 	}
   106 	return (int)(unsigned int)val;
   107     }
   108     return -1;
   110 }
   112 void serial_transmit_break() {
   113     SCIF_set_break();
   114 }
   116 /********************************* SCIF *************************************/
   118 #define FIFO_LENGTH 16
   119 #define FIFO_ARR_LENGTH (FIFO_LENGTH+1)
   121 /* Serial control register flags */
   122 #define SCSCR2_TIE  0x80
   123 #define SCSCR2_RIE  0x40
   124 #define SCSCR2_TE   0x20
   125 #define SCSCR2_RE   0x10
   126 #define SCSCR2_REIE 0x08
   127 #define SCSCR2_CKE 0x02
   129 #define IS_TRANSMIT_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_TIE)
   130 #define IS_RECEIVE_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RIE)
   131 #define IS_RECEIVE_ERROR_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & (SCSCR2_RIE|SCSCR2_REIE))
   132 /* Receive is enabled if the RE bit is set in SCSCR2, and the ORER bit is cleared in SCLSR2 */
   133 #define IS_RECEIVE_ENABLED() ( (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RE) && (MMIO_READ(SCIF,SCLSR2) & SCLSR2_ORER == 0) )
   134 /* Transmit is enabled if the TE bit is set in SCSCR2 */
   135 #define IS_TRANSMIT_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_TE)
   136 #define IS_LOOPBACK_ENABLED() (MMIO_READ(SCIF,SCFCR2) & SCFCR2_LOOP)
   138 /* Serial status register flags */
   139 #define SCFSR2_ER   0x80
   140 #define SCFSR2_TEND 0x40
   141 #define SCFSR2_TDFE 0x20
   142 #define SCFSR2_BRK  0x10
   143 #define SCFSR2_RDF  0x02
   144 #define SCFSR2_DR   0x01
   146 /* FIFO control register flags */
   147 #define SCFCR2_MCE   0x08
   148 #define SCFCR2_TFRST 0x04
   149 #define SCFCR2_RFRST 0x02
   150 #define SCFCR2_LOOP  0x01
   152 /* Line Status Register */
   153 #define SCLSR2_ORER 0x01
   155 struct SCIF_fifo {
   156     int head;
   157     int tail;
   158     int trigger;
   159     uint8_t data[FIFO_ARR_LENGTH];
   160 };
   162 void SCIF_save_state( FILE *f ) 
   163 {
   166 }
   168 int SCIF_load_state( FILE *f ) 
   169 {
   170     return 0;
   171 }
   173 int SCIF_recvq_triggers[4] = {1, 4, 8, 14};
   174 struct SCIF_fifo SCIF_recvq = {0,0,1};
   176 int SCIF_sendq_triggers[4] = {8, 4, 2, 1};
   177 struct SCIF_fifo SCIF_sendq = {0,0,8};
   179 static inline uint8_t SCIF_recvq_size( ) 
   180 {
   181     int val = SCIF_recvq.tail - SCIF_recvq.head;
   182     if( val < 0 ) {
   183 	val = FIFO_ARR_LENGTH - SCIF_recvq.head + SCIF_recvq.tail;
   184     }
   185     return val;
   186 }
   188 int SCIF_recvq_dequeue( gboolean clearFlags )
   189 {
   190     uint8_t result;
   191     uint32_t tmp, length;
   192     if( SCIF_recvq.head == SCIF_recvq.tail )
   193 	return -1; /* No data */
   194     result = SCIF_recvq.data[SCIF_recvq.head++];
   195     if( SCIF_recvq.head > FIFO_LENGTH )
   196 	SCIF_recvq.head = 0;
   198     /* Update data count register */
   199     tmp = MMIO_READ( SCIF, SCFDR2 ) & 0xF0;
   200     length = SCIF_recvq_size();
   201     MMIO_WRITE( SCIF, SCFDR2, tmp | length );
   203     /* Clear flags (if requested ) */
   204     if( clearFlags && length < SCIF_recvq.trigger ) {
   205 	tmp = SCFSR2_RDF;
   206 	if( length == 0 )
   207 	    tmp |= SCFSR2_DR;
   208 	tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp);
   209 	MMIO_WRITE( SCIF, SCFSR2, tmp );
   210 	/* If both flags are cleared, clear the interrupt as well */
   211 	if( (tmp & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() )
   212 	    intc_clear_interrupt( INT_SCIF_RXI );
   213     }
   215     return (int)(unsigned int)result;
   216 }
   218 gboolean SCIF_recvq_enqueue( uint8_t value )
   219 {
   220     uint32_t tmp, length;
   221     int newpos = SCIF_recvq.tail + 1;
   222     if( newpos > FIFO_LENGTH )
   223 	newpos = 0;
   224     if( newpos == SCIF_recvq.head ) {
   225 	/* FIFO full - set ORER and discard the value */
   226 	MMIO_WRITE( SCIF, SCLSR2, SCLSR2_ORER );
   227 	if( IS_RECEIVE_ERROR_IRQ_ENABLED() )
   228 	    intc_raise_interrupt( INT_SCIF_ERI );
   229 	return FALSE;
   230     }
   231     SCIF_recvq.data[SCIF_recvq.tail] = value;
   233     /* Update data count register */
   234     tmp = MMIO_READ( SCIF, SCFDR2 ) & 0xF0;
   235     length = SCIF_recvq_size();
   236     MMIO_WRITE( SCIF, SCFDR2, tmp | length );
   238     /* Update status register */
   239     tmp = MMIO_READ( SCIF, SCFSR2 );
   240     if( length >= SCIF_recvq.trigger ) {
   241 	tmp |= SCFSR2_RDF;
   242 	if( IS_RECEIVE_IRQ_ENABLED() ) 
   243 	    intc_raise_interrupt( INT_SCIF_RXI );
   244     }
   245     MMIO_WRITE( SCIF, SCFSR2, tmp );
   246     return TRUE;
   247 }
   250 /**
   251  * Reset the receive FIFO to its initial state. Manual is unclear as to
   252  * whether this also clears flags/interrupts, but we're assuming here that
   253  * it does until proven otherwise.
   254  */
   255 void SCIF_recvq_clear( void ) 
   256 {
   257     SCIF_recvq.head = SCIF_recvq.tail = 0;
   258     MMIO_WRITE( SCIF, SCFDR2, MMIO_READ( SCIF, SCFDR2 ) & 0xF0 );
   259     MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) & ~(SCFSR2_DR|SCFSR2_RDF) );
   260     if( IS_RECEIVE_IRQ_ENABLED() )
   261 	intc_clear_interrupt( INT_SCIF_RXI );
   262 }
   264 static inline uint8_t SCIF_sendq_size( ) 
   265 {
   266     int val = SCIF_sendq.tail - SCIF_sendq.head;
   267     if( val < 0 ) {
   268 	val = FIFO_ARR_LENGTH - SCIF_sendq.head + SCIF_sendq.tail;
   269     }
   270     return val;
   271 }
   273 /**
   274  * Dequeue one byte from the SCIF transmit queue (ie transmit the byte),
   275  * updating all status flags as required.
   276  * @return The byte dequeued, or -1 if the queue is empty.
   277  */
   278 int SCIF_sendq_dequeue( )
   279 {
   280     uint8_t result;
   281     uint32_t tmp, length;
   282     if( SCIF_sendq.head == SCIF_sendq.tail )
   283 	return -1; /* No data */
   285     /* Update queue head pointer */
   286     result = SCIF_sendq.data[SCIF_sendq.head++];
   287     if( SCIF_sendq.head > FIFO_LENGTH )
   288 	SCIF_sendq.head = 0;
   290     /* Update data count register */
   291     tmp = MMIO_READ( SCIF, SCFDR2 ) & 0x0F;
   292     length = SCIF_sendq_size();
   293     MMIO_WRITE( SCIF, SCFDR2, tmp | (length << 8) );
   295     /* Update status register */
   296     if( length <= SCIF_sendq.trigger ) {
   297 	tmp = MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TDFE;
   298 	if( length == 0 )
   299 	    tmp |= SCFSR2_TEND; /* Transmission ended - no data waiting */
   300 	if( IS_TRANSMIT_IRQ_ENABLED() ) 
   301 	    intc_raise_interrupt( INT_SCIF_TXI );
   302 	MMIO_WRITE( SCIF, SCFSR2, tmp );
   303     }
   304     return (int)(unsigned int)result;
   305 }
   307 /**
   308  * Enqueue a single byte in the SCIF transmit queue. If the queue is full,
   309  * the value will be discarded.
   310  * @param value to be queued.
   311  * @param clearFlags TRUE if the TEND/TDFE flags should be cleared
   312  *   if the queue exceeds the trigger level. (According to the manual,
   313  *   DMAC writes will clear the flag, whereas regular SH4 writes do NOT
   314  *   automatically clear it. Go figure).
   315  * @return gboolean TRUE if the value was queued, FALSE if the queue was
   316  *   full.
   317  */
   318 gboolean SCIF_sendq_enqueue( uint8_t value, gboolean clearFlags )
   319 {
   320     uint32_t tmp, length;
   321     int newpos = SCIF_sendq.tail + 1;
   322     if( newpos > FIFO_LENGTH )
   323 	newpos = 0;
   324     if( newpos == SCIF_sendq.head ) {
   325 	/* FIFO full - discard */
   326 	return FALSE;
   327     }
   328     SCIF_sendq.data[SCIF_sendq.tail] = value;
   329     SCIF_sendq.tail = newpos;
   331     /* Update data count register */
   332     tmp = MMIO_READ( SCIF, SCFDR2 ) & 0x0F;
   333     length = SCIF_sendq_size();
   334     MMIO_WRITE( SCIF, SCFDR2, tmp | (length << 8) );
   336     /* Update flags if requested */
   337     if( clearFlags ) {
   338 	tmp = SCFSR2_TEND;
   339 	if( length > SCIF_sendq.trigger ) {
   340 	    tmp |= SCFSR2_TDFE;
   341 	    if( IS_TRANSMIT_IRQ_ENABLED() )
   342 		intc_clear_interrupt( INT_SCIF_TXI );
   343 	}
   344 	tmp = MMIO_READ( SCIF, SCFSR2 ) & (~tmp);
   345 	MMIO_WRITE( SCIF, SCFSR2, tmp );
   346     }
   347     return TRUE;
   348 }
   350 void SCIF_sendq_clear( void ) 
   351 {
   352     SCIF_sendq.head = SCIF_sendq.tail = 0;
   353     MMIO_WRITE( SCIF, SCFDR2, MMIO_READ( SCIF, SCFDR2 ) & 0x0F );
   354     MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_TEND | SCFSR2_TDFE );
   355     if( IS_TRANSMIT_IRQ_ENABLED() ) {
   356 	intc_raise_interrupt( INT_SCIF_TXI );
   357     }
   358 }
   360 /**
   361  * Update the SCFSR2 status register with the given mask (ie clear any values
   362  * that are set to 0 in the mask. According to a strict reading of the doco
   363  * though, the bits will only actually clear if the flag state is no longer
   364  * true, so we need to recheck everything...
   365  */
   366 void SCIF_update_status( uint32_t mask )
   367 {
   368     uint32_t value = MMIO_READ( SCIF, SCFSR2 );
   369     uint32_t result = value & mask;
   370     uint32_t sendq_size = SCIF_sendq_size();
   371     uint32_t recvq_size = SCIF_recvq_size();
   373     if( sendq_size != 0 )
   374 	result |= SCFSR2_TEND;
   376     if( sendq_size <= SCIF_sendq.trigger )
   377 	result |= SCFSR2_TDFE;
   378     else if( result & SCFSR2_TDFE == 0 && IS_TRANSMIT_IRQ_ENABLED() )
   379 	intc_clear_interrupt( INT_SCIF_TXI );
   381     if( recvq_size >= SCIF_recvq.trigger )
   382 	result |= SCFSR2_RDF;
   383     if( (value & SCFSR2_DR) != 0 && (result & SCFSR2_DR) == 0 &&
   384 	recvq_size != 0 )
   385 	result |= SCFSR2_DR;
   386     if( (result & (SCFSR2_DR|SCFSR2_RDF)) == 0 && IS_RECEIVE_IRQ_ENABLED() )
   387 	intc_clear_interrupt( INT_SCIF_RXI );
   389     if( IS_RECEIVE_ERROR_IRQ_ENABLED() ) {
   390 	if( (result & SCFSR2_BRK) == 0 )
   391 	    intc_clear_interrupt( INT_SCIF_BRI );
   392 	if( (result & SCFSR2_ER) == 0 && 
   393 	    (MMIO_READ( SCIF, SCLSR2 ) & SCLSR2_ORER) == 0 )
   394 	    intc_clear_interrupt( INT_SCIF_ERI );
   395     }
   396 }
   398 /**
   399  * Set the break detected flag
   400  */
   401 void SCIF_set_break( void ) 
   402 {
   403     MMIO_WRITE( SCIF, SCFSR2, MMIO_READ( SCIF, SCFSR2 ) | SCFSR2_BRK );
   404     if( IS_RECEIVE_ERROR_IRQ_ENABLED() )
   405 	intc_raise_interrupt( INT_SCIF_BRI );
   406 }
   408 const static int SCIF_CLOCK_MULTIPLIER[4] = {1, 4, 16, 64};
   410 /**
   411  * Calculate the current line speed.
   412  */
   413 void SCIF_update_line_speed( void )
   414 {
   415     /* If CKE1 is set, use the external clock as a base */
   416     if( MMIO_READ( SCIF, SCSCR2 ) & SCSCR2_CKE ) {
   419     } else {
   421 	/* Otherwise, SH4 peripheral clock divided by n */
   422 	int mult = SCIF_CLOCK_MULTIPLIER[MMIO_READ( SCIF, SCSMR2 ) & 0x03];
   424 	/* Then process the bitrate register */
   425 	int bbr = MMIO_READ( SCIF, SCBRR2 ) & 0xFF;
   427 	int baudrate = sh4_peripheral_freq / (32 * mult * (bbr+1) );
   429 	if( serial_device != NULL && serial_device->set_line_speed != NULL )
   430 	    serial_device->set_line_speed( baudrate );
   431 	INFO( "SCIF baud rate set to %d", baudrate );
   432 	/*
   433 	  clock_set_tick_rate( CLOCK_SCIF, baudrate / 10 );
   434 	*/
   435     }
   436 }
   438 int32_t mmio_region_SCIF_read( uint32_t reg )
   439 {
   440     switch( reg ) {
   441     case SCFRDR2: /* Receive data */
   442 	return SCIF_recvq_dequeue(FALSE);
   443     default:
   444 	return MMIO_READ( SCIF, reg );
   445     }
   446 }
   448 void mmio_region_SCIF_write( uint32_t reg, uint32_t val ) 
   449 {
   450     uint32_t tmp;
   451     switch( reg ) {
   452     case SCSMR2: /* Serial mode register */
   453 	/* Bit 6 => 0 = 8-bit, 1 = 7-bit
   454 	 * Bit 5 => 0 = Parity disabled, 1 = parity enabled
   455 	 * Bit 4 => 0 = Even parity, 1 = Odd parity
   456 	 * Bit 3 => 0 = 1 stop bit, 1 = 2 stop bits
   457 	 * Bits 0-1 => Clock select 00 = P, 01 = P/4, 10 = P/16, 11 = P/64
   458 	 */
   459 	val &= 0x007B;
   460 	if( serial_device != NULL ) {
   461 	    serial_device->set_line_params( val );
   462 	}
   463 	tmp = MMIO_READ( SCIF, SCSMR2 );
   464 	if( tmp & 0x03 != val & 0x03 ) {
   465 	    /* Clock change */
   466 	    SCIF_update_line_speed( );
   467 	}
   468 	/* Save for later read-back */
   469 	MMIO_WRITE( SCIF, SCSMR2, val );
   470 	break;
   471     case SCBRR2: /* Bit rate register */
   472 	MMIO_WRITE( SCIF, SCBRR2, val );
   473 	SCIF_update_line_speed( );
   474 	break;
   475     case SCSCR2: /* Serial control register */
   476 	/* Bit 7 => Transmit-FIFO-data-empty interrupt enabled 
   477 	 * Bit 6 => Receive-data-full interrupt enabled 
   478 	 * Bit 5 => Transmit enable 
   479 	 * Bit 4 => Receive enable 
   480 	 * Bit 3 => Receive-error/break interrupt enabled
   481 	 * Bit 1 => Clock enable
   482 	 */
   483 	val &= 0x00FA;
   484 	/* Clear any interrupts that just became disabled */
   485 	if( val & SCSCR2_TIE == 0 )
   486 	    intc_clear_interrupt( INT_SCIF_TXI );
   487 	if( val & SCSCR2_RIE == 0 )
   488 	    intc_clear_interrupt( INT_SCIF_RXI );
   489 	if( val & (SCSCR2_RIE|SCSCR2_REIE) == 0 ) {
   490 	    intc_clear_interrupt( INT_SCIF_ERI );
   491 	    intc_clear_interrupt( INT_SCIF_BRI );
   492 	}
   494 	MMIO_WRITE( SCIF, reg, val );
   495 	break;
   496     case SCFTDR2: /* Transmit FIFO data register */
   497 	SCIF_sendq_enqueue( val, FALSE );
   498 	break;
   499     case SCFSR2: /* Serial status register */
   500 	/* Bits 12-15 Parity error count
   501 	 * Bits 8-11 Framing erro count 
   502 	 * Bit 7 - Receive error
   503 	 * Bit 6 - Transmit end
   504 	 * Bit 5 - Transmit FIFO data empty
   505 	 * Bit 4 - Break detect
   506 	 * Bit 3 - Framing error
   507 	 * Bit 2 - Parity error
   508 	 * Bit 1 - Receive FIFO data full
   509 	 * Bit 0 - Receive data ready
   510 	 */
   511 	/* Clear off any flags/interrupts that are being set to 0 */
   512 	SCIF_update_status( val );
   513 	break;
   514     case SCFCR2: /* FIFO control register */
   515 	val &= 0x0F;
   516 	SCIF_recvq.trigger = SCIF_recvq_triggers[val >> 6];
   517 	SCIF_sendq.trigger = SCIF_sendq_triggers[(val >> 4) & 0x03];
   518 	if( val & SCFCR2_TFRST ) {
   519 	    SCIF_sendq_clear();
   520 	}
   521 	if( val & SCFCR2_RFRST ) {
   522 	    SCIF_recvq_clear();
   523 	}
   525 	MMIO_WRITE( SCIF, reg, val );
   526 	break;
   527     case SCSPTR2: /* Serial Port Register */
   528 	MMIO_WRITE( SCIF, reg, val );
   529 	/* NOT IMPLEMENTED */
   530 	WARN( "SCSPTR2 not implemented: Write %08X", val );
   531 	break;
   532     case SCLSR2:
   533 	val = val & SCLSR2_ORER;
   534 	if( val == 0 ) {
   535 	    MMIO_WRITE( SCIF, SCLSR2, val );
   536 	    if( (MMIO_READ( SCIF, SCFSR2 ) & SCFSR2_ER) == 0 &&
   537 		IS_RECEIVE_ERROR_IRQ_ENABLED() ) 
   538 		intc_clear_interrupt( INT_SCIF_ERI );
   539 	}
   541 	break;
   542     }
   543 }
   545 /**
   546  * Flag to indicate if data was received (ie added to the receive queue)
   547  * during the last SCIF clock tick. Used to determine when to set the DR
   548  * flag.
   549  */
   550 gboolean SCIF_rcvd_last_tick = FALSE;
   552 /**
   553  * Actions for a single tick of the serial clock, defined as the transmission
   554  * time of a single frame.
   555  *
   556  * If transmit queue is non-empty:
   557  *    Transmit one byte and remove from queue
   558  * If input receive source is non-empty:
   559  *    Transfer one byte to the receive queue (if queue is full, byte is lost)
   560  * If recvq is non-empty, less than the trigger level, and no data has been
   561  *    received in the last 2 ticks (including this one), set the DR flag and
   562  *    IRQ if appropriate.
   563  */
   564 void SCIF_clock_tick( void ) 
   565 {
   566     gboolean rcvd = FALSE;
   568     if( IS_LOOPBACK_ENABLED() ) {
   569 	if( IS_TRANSMIT_ENABLED() ) {
   570 	    int val = SCIF_sendq_dequeue();
   571 	    if( val != -1 && IS_RECEIVE_ENABLED() ) {
   572 		SCIF_recvq_enqueue( val );
   573 		rcvd = TRUE;
   574 	    }
   575 	}
   576     } else {
   577 	if( IS_TRANSMIT_ENABLED() ) {
   578 	    int val = SCIF_sendq_dequeue();
   579 	    if( val != -1 && serial_device != NULL && 
   580 		serial_device->receive_data != NULL ) {
   581 		serial_device->receive_data( val );
   582 	    }
   583 	}
   585 	if( IS_RECEIVE_ENABLED() ) {
   586 	    int val = serial_transmit_dequeue();
   587 	    if( val != -1 ) {
   588 		SCIF_recvq_enqueue( val );
   589 		rcvd = TRUE;
   590 	    }
   591 	}
   592     }
   594     /* Check if we need to set the DR flag */
   595     if( !rcvd && !SCIF_rcvd_last_tick &&
   596 	SCIF_recvq.head != SCIF_recvq.tail &&
   597 	SCIF_recvq_size() < SCIF_recvq.trigger ) {
   598 	uint32_t tmp = MMIO_READ( SCIF, SCFSR2 );
   599 	if( tmp & SCFSR2_DR == 0 ) {
   600 	    MMIO_WRITE( SCIF, SCFSR2, tmp | SCFSR2_DR );
   601 	    if( IS_RECEIVE_IRQ_ENABLED() )
   602 		intc_raise_interrupt( INT_SCIF_RXI );
   603 	}
   604     }
   605     SCIF_rcvd_last_tick = rcvd;
   606 }
.