Fix IDE DMA to actually work for real.
Implement the mystery packet 0x71 by cribbing a block of data from the dc.
src/asic.c
src/asic.h
src/gdrom/gdrom.c
src/gdrom/ide.c
src/gdrom/packet.h
Implement the mystery packet 0x71 by cribbing a block of data from the dc.
src/asic.c
src/asic.h
src/gdrom/gdrom.c
src/gdrom/ide.c
src/gdrom/packet.h
Add preliminary call-stack tracing ability
Fix INTC state save/load/reset
src/sh4/intc.c
src/sh4/sh4core.c
src/sh4/sh4core.h
Fix INTC state save/load/reset
src/sh4/intc.c
src/sh4/sh4core.c
src/sh4/sh4core.h
Add P4 I/O tracing
Add ability to set I/O trace by region address
src/mem.c
src/mem.h
src/mmio.h
src/sh4/sh4mem.c
Add ability to set I/O trace by region address
src/mem.c
src/mem.h
src/mmio.h
src/sh4/sh4mem.c
Skip 8-byte subheader at start of mode-2/1 sectors when performing a mode-1
read...
src/gdrom/gdrom.c
read...
src/gdrom/gdrom.c
Clean up the buffer and i/o handling
Implement save/load state
src/gdrom/gdrom.c
src/gdrom/gdrom.h
src/gdrom/ide.c
src/gdrom/ide.h
Implement save/load state
src/gdrom/gdrom.c
src/gdrom/gdrom.h
src/gdrom/ide.c
src/gdrom/ide.h
Add texcache invalidates on direct writes to 64-bit vram.
Technically we should do it on direct writes to 32-bit vram as well, but
noone (sane) is going to try to write a texture there...
src/sh4/sh4mem.c
Technically we should do it on direct writes to 32-bit vram as well, but
noone (sane) is going to try to write a texture there...
src/sh4/sh4mem.c
.