Mask off SR correctly when writing to it - this turns out to be important
in some cases
src/sh4/sh4.c
test/Makefile.in
test/sh4/ldcsr.s
test/sh4/testsh4.c
in some cases
src/sh4/sh4.c
test/Makefile.in
test/sh4/ldcsr.s
test/sh4/testsh4.c
Setup the interrupt/exception vectors properly in the arm crt0
Use fully guarded memcpy_to_aica for program transfer
test/lib-arm/crt0.s
test/testaica.c
Use fully guarded memcpy_to_aica for program transfer
test/lib-arm/crt0.s
test/testaica.c
Add semi-documented PVR register at 0xFF000030 (SH4 version identification)
src/sh4/mmu.c
src/sh4/sh4mmio.h
test/testregs.c
src/sh4/mmu.c
src/sh4/sh4mmio.h
test/testregs.c
Implement memcpy_to_aica, still a work in progress though
test/Makefile.in
test/asic.c
test/asic.h
test/dmac.c
test/interrupt.s
test/lib.h
test/Makefile.in
test/asic.c
test/asic.h
test/dmac.c
test/interrupt.s
test/lib.h
Move arm clock rate back to clock.h where it's supposed to be
Fix STM with R15 (should be current pc +12, was +8...) - not sure how this managed
to work as long as it did
src/aica/armcore.c
src/aica/armcore.h
src/clock.h
Fix STM with R15 (should be current pc +12, was +8...) - not sure how this managed
to work as long as it did
src/aica/armcore.c
src/aica/armcore.h
src/clock.h
Display opcode as 32-bit word rather than 4 bytes... easier to match up with the manual this way
src/aica/armdasm.c
src/aica/armdasm.c
.