Implement the main CRTC registers, along with the sync status register.
Timings are now pretty close to the real thing.
src/clock.h
src/pvr2/pvr2.c
src/pvr2/pvr2mmio.h

Adjust timers when they're read rather than waiting until the next time
slice. Also temporarily cut the CPU time by 4.
Initialize the FRQCR register to 0x0E0A for convenience
src/sh4/sh4core.c
src/sh4/sh4core.h
src/sh4/timer.c

Limit number of sectors read at once (linux driver seems to throw a hissy
fit if you request too many at a time)
src/gdrom/linux.c

Fix byte-count handling in accordance with the actual DC chip
src/gdrom/ide.c
test/testide.c

Fix comment for the IO bit
src/gdrom/ide.h

Put ide_raise_interrupt() back in after set feature - it's needed even tho
the test case seemed to indicate that it didn't happen...
src/gdrom/ide.c

Fix reset PC when invoked from the SH4 itself
src/asic.c

Fix 0x40,0x01 in accordance with test results
Add reset flag to fail first packet command (also as per tests)
src/gdrom/ide.c
src/gdrom/ide.h

Add reset error and fix BADREAD error code
src/gdrom/packet.h

Add tests for 0x40,0x01 command
test/testide.c