Add semi-documented PVR register at 0xFF000030 (SH4 version identification)
src/sh4/mmu.c
src/sh4/sh4mmio.h
test/testregs.c
src/sh4/mmu.c
src/sh4/sh4mmio.h
test/testregs.c
Implement memcpy_to_aica, still a work in progress though
test/Makefile.in
test/asic.c
test/asic.h
test/dmac.c
test/interrupt.s
test/lib.h
test/Makefile.in
test/asic.c
test/asic.h
test/dmac.c
test/interrupt.s
test/lib.h
Move arm clock rate back to clock.h where it's supposed to be
Fix STM with R15 (should be current pc +12, was +8...) - not sure how this managed
to work as long as it did
src/aica/armcore.c
src/aica/armcore.h
src/clock.h
Fix STM with R15 (should be current pc +12, was +8...) - not sure how this managed
to work as long as it did
src/aica/armcore.c
src/aica/armcore.h
src/clock.h
Display opcode as 32-bit word rather than 4 bytes... easier to match up with the manual this way
src/aica/armdasm.c
src/aica/armdasm.c
Add ARM test harness (not quite working on DC but almost...)
test/Makefile.in
test/aica.x
test/asic.h
test/crt0.s
test/dma.h
test/dmac.c
test/lib-arm/crt0.s
test/lib-arm/libc.a
test/lib-arm/libm.a
test/lib.h
...
test/Makefile.in
test/aica.x
test/asic.h
test/crt0.s
test/dma.h
test/dmac.c
test/lib-arm/crt0.s
test/lib-arm/libc.a
test/lib-arm/libm.a
test/lib.h
...
Implement LDRH/STRH/LDRSH/LDRSB instructions
src/aica/armcore.c
src/aica/armdasm.c
src/aica/armmem.c
src/aica/armcore.c
src/aica/armdasm.c
src/aica/armmem.c
.