nkeynes@31: /** nkeynes@282: * $Id: pvr2.c,v 1.38 2007-01-14 11:43:00 nkeynes Exp $ nkeynes@31: * nkeynes@133: * PVR2 (Video) Core module implementation and MMIO registers. nkeynes@31: * nkeynes@31: * Copyright (c) 2005 Nathan Keynes. nkeynes@31: * nkeynes@31: * This program is free software; you can redistribute it and/or modify nkeynes@31: * it under the terms of the GNU General Public License as published by nkeynes@31: * the Free Software Foundation; either version 2 of the License, or nkeynes@31: * (at your option) any later version. nkeynes@31: * nkeynes@31: * This program is distributed in the hope that it will be useful, nkeynes@31: * but WITHOUT ANY WARRANTY; without even the implied warranty of nkeynes@31: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the nkeynes@31: * GNU General Public License for more details. nkeynes@31: */ nkeynes@35: #define MODULE pvr2_module nkeynes@31: nkeynes@1: #include "dream.h" nkeynes@265: #include "eventq.h" nkeynes@144: #include "display.h" nkeynes@1: #include "mem.h" nkeynes@1: #include "asic.h" nkeynes@261: #include "clock.h" nkeynes@103: #include "pvr2/pvr2.h" nkeynes@56: #include "sh4/sh4core.h" nkeynes@1: #define MMIO_IMPL nkeynes@103: #include "pvr2/pvr2mmio.h" nkeynes@1: nkeynes@1: char *video_base; nkeynes@1: nkeynes@133: static void pvr2_init( void ); nkeynes@133: static void pvr2_reset( void ); nkeynes@133: static uint32_t pvr2_run_slice( uint32_t ); nkeynes@133: static void pvr2_save_state( FILE *f ); nkeynes@133: static int pvr2_load_state( FILE *f ); nkeynes@265: static void pvr2_update_raster_posn( uint32_t nanosecs ); nkeynes@265: static void pvr2_schedule_line_event( int eventid, int line ); nkeynes@274: static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines ); nkeynes@265: uint32_t pvr2_get_sync_status(); nkeynes@133: nkeynes@94: void pvr2_display_frame( void ); nkeynes@94: nkeynes@161: int colour_format_bytes[] = { 2, 2, 2, 1, 3, 4, 1, 1 }; nkeynes@161: nkeynes@133: struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, pvr2_reset, NULL, nkeynes@133: pvr2_run_slice, NULL, nkeynes@133: pvr2_save_state, pvr2_load_state }; nkeynes@133: nkeynes@103: nkeynes@144: display_driver_t display_driver = NULL; nkeynes@15: nkeynes@103: struct video_timing { nkeynes@103: int fields_per_second; nkeynes@103: int total_lines; nkeynes@108: int retrace_lines; nkeynes@103: int line_time_ns; nkeynes@103: }; nkeynes@103: nkeynes@261: struct video_timing pal_timing = { 50, 625, 65, 31945 }; nkeynes@108: struct video_timing ntsc_timing= { 60, 525, 65, 31746 }; nkeynes@103: nkeynes@133: struct pvr2_state { nkeynes@133: uint32_t frame_count; nkeynes@133: uint32_t line_count; nkeynes@133: uint32_t line_remainder; nkeynes@265: uint32_t cycles_run; /* Cycles already executed prior to main time slice */ nkeynes@133: uint32_t irq_vpos1; nkeynes@133: uint32_t irq_vpos2; nkeynes@261: uint32_t odd_even_field; /* 1 = odd, 0 = even */ nkeynes@261: nkeynes@261: /* timing */ nkeynes@261: uint32_t dot_clock; nkeynes@261: uint32_t total_lines; nkeynes@261: uint32_t line_size; nkeynes@261: uint32_t line_time_ns; nkeynes@261: uint32_t vsync_lines; nkeynes@261: uint32_t hsync_width_ns; nkeynes@261: uint32_t front_porch_ns; nkeynes@261: uint32_t back_porch_ns; nkeynes@265: uint32_t retrace_start_line; nkeynes@265: uint32_t retrace_end_line; nkeynes@261: gboolean interlaced; nkeynes@133: struct video_timing timing; nkeynes@133: } pvr2_state; nkeynes@15: nkeynes@133: struct video_buffer video_buffer[2]; nkeynes@133: int video_buffer_idx = 0; nkeynes@133: nkeynes@265: /** nkeynes@265: * Event handler for the retrace callback (fires on line 0 normally) nkeynes@265: */ nkeynes@265: static void pvr2_retrace_callback( int eventid ) { nkeynes@265: asic_event( eventid ); nkeynes@265: pvr2_update_raster_posn(sh4r.slice_cycle); nkeynes@265: pvr2_schedule_line_event( EVENT_RETRACE, 0 ); nkeynes@265: } nkeynes@265: nkeynes@265: /** nkeynes@265: * Event handler for the scanline callbacks. Fires the corresponding nkeynes@265: * ASIC event, and resets the timer for the next field. nkeynes@265: */ nkeynes@265: static void pvr2_scanline_callback( int eventid ) { nkeynes@265: asic_event( eventid ); nkeynes@265: pvr2_update_raster_posn(sh4r.slice_cycle); nkeynes@265: if( eventid == EVENT_SCANLINE1 ) { nkeynes@274: pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos1, 1 ); nkeynes@265: } else { nkeynes@274: pvr2_schedule_scanline_event( eventid, pvr2_state.irq_vpos2, 1 ); nkeynes@265: } nkeynes@265: } nkeynes@265: nkeynes@133: static void pvr2_init( void ) nkeynes@1: { nkeynes@1: register_io_region( &mmio_region_PVR2 ); nkeynes@85: register_io_region( &mmio_region_PVR2PAL ); nkeynes@56: register_io_region( &mmio_region_PVR2TA ); nkeynes@265: register_event_callback( EVENT_RETRACE, pvr2_retrace_callback ); nkeynes@265: register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback ); nkeynes@265: register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback ); nkeynes@1: video_base = mem_get_region_by_name( MEM_REGION_VIDEO ); nkeynes@133: texcache_init(); nkeynes@133: pvr2_reset(); nkeynes@214: pvr2_ta_reset(); nkeynes@133: } nkeynes@133: nkeynes@133: static void pvr2_reset( void ) nkeynes@133: { nkeynes@133: pvr2_state.line_count = 0; nkeynes@133: pvr2_state.line_remainder = 0; nkeynes@265: pvr2_state.cycles_run = 0; nkeynes@133: pvr2_state.irq_vpos1 = 0; nkeynes@133: pvr2_state.irq_vpos2 = 0; nkeynes@133: pvr2_state.timing = ntsc_timing; nkeynes@265: pvr2_state.dot_clock = PVR2_DOT_CLOCK; nkeynes@265: pvr2_state.back_porch_ns = 4000; nkeynes@265: mmio_region_PVR2_write( DISP_TOTAL, 0x0270035F ); nkeynes@265: mmio_region_PVR2_write( DISP_SYNCTIME, 0x07D6A53F ); nkeynes@133: video_buffer_idx = 0; nkeynes@133: nkeynes@133: pvr2_ta_init(); nkeynes@107: pvr2_render_init(); nkeynes@133: texcache_flush(); nkeynes@133: } nkeynes@133: nkeynes@133: static void pvr2_save_state( FILE *f ) nkeynes@133: { nkeynes@133: fwrite( &pvr2_state, sizeof(pvr2_state), 1, f ); nkeynes@193: pvr2_ta_save_state( f ); nkeynes@133: } nkeynes@133: nkeynes@133: static int pvr2_load_state( FILE *f ) nkeynes@133: { nkeynes@153: if( fread( &pvr2_state, sizeof(pvr2_state), 1, f ) != 1 ) nkeynes@153: return 1; nkeynes@193: return pvr2_ta_load_state(f); nkeynes@133: } nkeynes@133: nkeynes@265: /** nkeynes@265: * Update the current raster position to the given number of nanoseconds, nkeynes@265: * relative to the last time slice. (ie the raster will be adjusted forward nkeynes@265: * by nanosecs - nanosecs_already_run_this_timeslice) nkeynes@265: */ nkeynes@265: static void pvr2_update_raster_posn( uint32_t nanosecs ) nkeynes@265: { nkeynes@265: uint32_t old_line_count = pvr2_state.line_count; nkeynes@265: if( pvr2_state.line_time_ns == 0 ) { nkeynes@265: return; /* do nothing */ nkeynes@265: } nkeynes@265: pvr2_state.line_remainder += (nanosecs - pvr2_state.cycles_run); nkeynes@265: pvr2_state.cycles_run = nanosecs; nkeynes@265: while( pvr2_state.line_remainder >= pvr2_state.line_time_ns ) { nkeynes@265: pvr2_state.line_count ++; nkeynes@265: pvr2_state.line_remainder -= pvr2_state.line_time_ns; nkeynes@265: } nkeynes@265: nkeynes@265: if( pvr2_state.line_count >= pvr2_state.total_lines ) { nkeynes@265: pvr2_state.line_count -= pvr2_state.total_lines; nkeynes@265: if( pvr2_state.interlaced ) { nkeynes@265: pvr2_state.odd_even_field = !pvr2_state.odd_even_field; nkeynes@265: } nkeynes@265: } nkeynes@265: if( pvr2_state.line_count >= pvr2_state.retrace_end_line && nkeynes@265: (old_line_count < pvr2_state.retrace_end_line || nkeynes@265: old_line_count > pvr2_state.line_count) ) { nkeynes@265: pvr2_display_frame(); nkeynes@265: } nkeynes@265: } nkeynes@265: nkeynes@133: static uint32_t pvr2_run_slice( uint32_t nanosecs ) nkeynes@133: { nkeynes@265: pvr2_update_raster_posn( nanosecs ); nkeynes@265: pvr2_state.cycles_run = 0; nkeynes@133: return nanosecs; nkeynes@133: } nkeynes@133: nkeynes@133: int pvr2_get_frame_count() nkeynes@133: { nkeynes@133: return pvr2_state.frame_count; nkeynes@106: } nkeynes@106: nkeynes@103: /** nkeynes@1: * Display the next frame, copying the current contents of video ram to nkeynes@1: * the window. If the video configuration has changed, first recompute the nkeynes@1: * new frame size/depth. nkeynes@1: */ nkeynes@94: void pvr2_display_frame( void ) nkeynes@1: { nkeynes@197: uint32_t display_addr = MMIO_READ( PVR2, DISP_ADDR1 ); nkeynes@103: nkeynes@197: int dispsize = MMIO_READ( PVR2, DISP_SIZE ); nkeynes@197: int dispmode = MMIO_READ( PVR2, DISP_MODE ); nkeynes@261: int vidcfg = MMIO_READ( PVR2, DISP_SYNCCFG ); nkeynes@94: int vid_stride = ((dispsize & DISPSIZE_MODULO) >> 20) - 1; nkeynes@94: int vid_lpf = ((dispsize & DISPSIZE_LPF) >> 10) + 1; nkeynes@94: int vid_ppl = ((dispsize & DISPSIZE_PPL)) + 1; nkeynes@103: gboolean bEnabled = (dispmode & DISPMODE_DE) && (vidcfg & DISPCFG_VO ) ? TRUE : FALSE; nkeynes@103: gboolean interlaced = (vidcfg & DISPCFG_I ? TRUE : FALSE); nkeynes@161: video_buffer_t buffer = &video_buffer[video_buffer_idx]; nkeynes@161: video_buffer_idx = !video_buffer_idx; nkeynes@161: video_buffer_t last = &video_buffer[video_buffer_idx]; nkeynes@161: buffer->rowstride = (vid_ppl + vid_stride) << 2; nkeynes@197: buffer->data = video_base + MMIO_READ( PVR2, DISP_ADDR1 ); nkeynes@161: buffer->vres = vid_lpf; nkeynes@161: if( interlaced ) buffer->vres <<= 1; nkeynes@161: switch( (dispmode & DISPMODE_COL) >> 2 ) { nkeynes@161: case 0: nkeynes@161: buffer->colour_format = COLFMT_ARGB1555; nkeynes@161: buffer->hres = vid_ppl << 1; nkeynes@161: break; nkeynes@161: case 1: nkeynes@161: buffer->colour_format = COLFMT_RGB565; nkeynes@161: buffer->hres = vid_ppl << 1; nkeynes@161: break; nkeynes@161: case 2: nkeynes@161: buffer->colour_format = COLFMT_RGB888; nkeynes@161: buffer->hres = (vid_ppl << 2) / 3; nkeynes@161: break; nkeynes@161: case 3: nkeynes@161: buffer->colour_format = COLFMT_ARGB8888; nkeynes@161: buffer->hres = vid_ppl; nkeynes@161: break; nkeynes@161: } nkeynes@161: nkeynes@161: if( buffer->hres <=8 ) nkeynes@161: buffer->hres = 640; nkeynes@161: if( buffer->vres <=8 ) nkeynes@161: buffer->vres = 480; nkeynes@161: if( display_driver != NULL ) { nkeynes@161: if( buffer->hres != last->hres || nkeynes@161: buffer->vres != last->vres || nkeynes@161: buffer->colour_format != last->colour_format) { nkeynes@161: display_driver->set_display_format( buffer->hres, buffer->vres, nkeynes@161: buffer->colour_format ); nkeynes@94: } nkeynes@161: if( !bEnabled ) { nkeynes@161: display_driver->display_blank_frame( 0 ); nkeynes@197: } else if( MMIO_READ( PVR2, DISP_CFG2 ) & 0x08 ) { /* Blanked */ nkeynes@197: uint32_t colour = MMIO_READ( PVR2, DISP_BORDER ); nkeynes@161: display_driver->display_blank_frame( colour ); nkeynes@161: } else if( !pvr2_render_display_frame( PVR2_RAM_BASE + display_addr ) ) { nkeynes@161: display_driver->display_frame( buffer ); nkeynes@65: } nkeynes@1: } nkeynes@133: pvr2_state.frame_count++; nkeynes@1: } nkeynes@1: nkeynes@197: /** nkeynes@197: * This has to handle every single register individually as they all get masked nkeynes@197: * off differently (and its easier to do it at write time) nkeynes@197: */ nkeynes@1: void mmio_region_PVR2_write( uint32_t reg, uint32_t val ) nkeynes@1: { nkeynes@1: if( reg >= 0x200 && reg < 0x600 ) { /* Fog table */ nkeynes@1: MMIO_WRITE( PVR2, reg, val ); nkeynes@1: return; nkeynes@1: } nkeynes@1: nkeynes@1: switch(reg) { nkeynes@189: case PVRID: nkeynes@189: case PVRVER: nkeynes@261: case GUNPOS: /* Read only registers */ nkeynes@189: break; nkeynes@197: case PVRRESET: nkeynes@197: val &= 0x00000007; /* Do stuff? */ nkeynes@197: MMIO_WRITE( PVR2, reg, val ); nkeynes@197: break; nkeynes@191: case RENDER_START: nkeynes@261: if( val == 0xFFFFFFFF || val == 0x00000001 ) nkeynes@189: pvr2_render_scene(); nkeynes@189: break; nkeynes@191: case RENDER_POLYBASE: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x00F00000 ); nkeynes@191: break; nkeynes@191: case RENDER_TSPCFG: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x00010101 ); nkeynes@191: break; nkeynes@197: case DISP_BORDER: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x01FFFFFF ); nkeynes@191: break; nkeynes@197: case DISP_MODE: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x00FFFF7F ); nkeynes@191: break; nkeynes@191: case RENDER_MODE: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x00FFFF0F ); nkeynes@191: break; nkeynes@191: case RENDER_SIZE: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x000001FF ); nkeynes@191: break; nkeynes@197: case DISP_ADDR1: nkeynes@189: val &= 0x00FFFFFC; nkeynes@189: MMIO_WRITE( PVR2, reg, val ); nkeynes@265: pvr2_update_raster_posn(sh4r.slice_cycle); nkeynes@265: if( pvr2_state.line_count >= pvr2_state.retrace_start_line || nkeynes@265: pvr2_state.line_count < pvr2_state.retrace_end_line ) { nkeynes@108: pvr2_display_frame(); nkeynes@108: } nkeynes@108: break; nkeynes@197: case DISP_ADDR2: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x00FFFFFC ); nkeynes@191: break; nkeynes@197: case DISP_SIZE: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x3FFFFFFF ); nkeynes@191: break; nkeynes@191: case RENDER_ADDR1: nkeynes@191: case RENDER_ADDR2: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x01FFFFFC ); nkeynes@191: break; nkeynes@191: case RENDER_HCLIP: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x07FF07FF ); nkeynes@189: break; nkeynes@191: case RENDER_VCLIP: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x03FF03FF ); nkeynes@189: break; nkeynes@197: case DISP_HPOSIRQ: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x03FF33FF ); nkeynes@189: break; nkeynes@197: case DISP_VPOSIRQ: nkeynes@189: val = val & 0x03FF03FF; nkeynes@189: pvr2_state.irq_vpos1 = (val >> 16); nkeynes@133: pvr2_state.irq_vpos2 = val & 0x03FF; nkeynes@265: pvr2_update_raster_posn(sh4r.slice_cycle); nkeynes@274: pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 ); nkeynes@274: pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 ); nkeynes@189: MMIO_WRITE( PVR2, reg, val ); nkeynes@103: break; nkeynes@197: case RENDER_NEARCLIP: nkeynes@197: MMIO_WRITE( PVR2, reg, val & 0x7FFFFFFF ); nkeynes@197: break; nkeynes@191: case RENDER_SHADOW: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x000001FF ); nkeynes@191: break; nkeynes@191: case RENDER_OBJCFG: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x003FFFFF ); nkeynes@191: break; nkeynes@191: case RENDER_TSPCLIP: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x7FFFFFFF ); nkeynes@191: break; nkeynes@197: case RENDER_FARCLIP: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0xFFFFFFF0 ); nkeynes@197: break; nkeynes@191: case RENDER_BGPLANE: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF ); nkeynes@191: break; nkeynes@191: case RENDER_ISPCFG: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x00FFFFF9 ); nkeynes@191: break; nkeynes@197: case VRAM_CFG1: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x000000FF ); nkeynes@197: break; nkeynes@197: case VRAM_CFG2: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x003FFFFF ); nkeynes@197: break; nkeynes@197: case VRAM_CFG3: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x1FFFFFFF ); nkeynes@197: break; nkeynes@197: case RENDER_FOGTBLCOL: nkeynes@197: case RENDER_FOGVRTCOL: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x00FFFFFF ); nkeynes@197: break; nkeynes@197: case RENDER_FOGCOEFF: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x0000FFFF ); nkeynes@197: break; nkeynes@197: case RENDER_CLAMPHI: nkeynes@197: case RENDER_CLAMPLO: nkeynes@197: MMIO_WRITE( PVR2, reg, val ); nkeynes@197: break; nkeynes@261: case RENDER_TEXSIZE: nkeynes@261: MMIO_WRITE( PVR2, reg, val&0x00031F1F ); nkeynes@197: break; nkeynes@261: case RENDER_PALETTE: nkeynes@261: MMIO_WRITE( PVR2, reg, val&0x00000003 ); nkeynes@261: break; nkeynes@261: nkeynes@261: /********** CRTC registers *************/ nkeynes@197: case DISP_HBORDER: nkeynes@197: case DISP_VBORDER: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x03FF03FF ); nkeynes@197: break; nkeynes@261: case DISP_TOTAL: nkeynes@261: val = val & 0x03FF03FF; nkeynes@261: MMIO_WRITE( PVR2, reg, val ); nkeynes@265: pvr2_update_raster_posn(sh4r.slice_cycle); nkeynes@261: pvr2_state.total_lines = (val >> 16) + 1; nkeynes@261: pvr2_state.line_size = (val & 0x03FF) + 1; nkeynes@261: pvr2_state.line_time_ns = 1000000 * pvr2_state.line_size / pvr2_state.dot_clock; nkeynes@265: pvr2_state.retrace_end_line = 0x2A; nkeynes@265: pvr2_state.retrace_start_line = pvr2_state.total_lines - 6; nkeynes@265: pvr2_schedule_line_event( EVENT_RETRACE, 0 ); nkeynes@274: pvr2_schedule_scanline_event( EVENT_SCANLINE1, pvr2_state.irq_vpos1, 0 ); nkeynes@274: pvr2_schedule_scanline_event( EVENT_SCANLINE2, pvr2_state.irq_vpos2, 0 ); nkeynes@261: break; nkeynes@261: case DISP_SYNCCFG: nkeynes@261: MMIO_WRITE( PVR2, reg, val&0x000003FF ); nkeynes@261: pvr2_state.interlaced = (val & 0x0010) ? TRUE : FALSE; nkeynes@261: break; nkeynes@261: case DISP_SYNCTIME: nkeynes@261: pvr2_state.vsync_lines = (val >> 8) & 0x0F; nkeynes@269: pvr2_state.hsync_width_ns = ((val & 0x7F) + 1) * 2000000 / pvr2_state.dot_clock; nkeynes@197: MMIO_WRITE( PVR2, reg, val&0xFFFFFF7F ); nkeynes@197: break; nkeynes@197: case DISP_CFG2: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x003F01FF ); nkeynes@197: break; nkeynes@197: case DISP_HPOS: nkeynes@261: val = val & 0x03FF; nkeynes@261: pvr2_state.front_porch_ns = (val + 1) * 1000000 / pvr2_state.dot_clock; nkeynes@261: MMIO_WRITE( PVR2, reg, val ); nkeynes@197: break; nkeynes@197: case DISP_VPOS: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x03FF03FF ); nkeynes@197: break; nkeynes@261: nkeynes@261: /*********** Tile accelerator registers ***********/ nkeynes@261: case TA_POLYPOS: nkeynes@261: case TA_LISTPOS: nkeynes@261: /* Readonly registers */ nkeynes@197: break; nkeynes@189: case TA_TILEBASE: nkeynes@193: case TA_LISTEND: nkeynes@189: case TA_LISTBASE: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x00FFFFE0 ); nkeynes@189: break; nkeynes@191: case RENDER_TILEBASE: nkeynes@189: case TA_POLYBASE: nkeynes@189: case TA_POLYEND: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x00FFFFFC ); nkeynes@189: break; nkeynes@189: case TA_TILESIZE: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x000F003F ); nkeynes@189: break; nkeynes@189: case TA_TILECFG: nkeynes@191: MMIO_WRITE( PVR2, reg, val&0x00133333 ); nkeynes@189: break; nkeynes@261: case TA_INIT: nkeynes@261: if( val & 0x80000000 ) nkeynes@261: pvr2_ta_init(); nkeynes@261: break; nkeynes@261: case TA_REINIT: nkeynes@261: break; nkeynes@261: /**************** Scaler registers? ****************/ nkeynes@261: case SCALERCFG: nkeynes@269: /* KOS suggests bits as follows: nkeynes@269: * 0: enable vertical scaling nkeynes@269: * 10: ??? nkeynes@269: * 16: enable FSAA nkeynes@269: */ nkeynes@269: DEBUG( "Scaler config set to %08X", val ); nkeynes@261: MMIO_WRITE( PVR2, reg, val&0x0007FFFF ); nkeynes@261: break; nkeynes@261: nkeynes@197: case YUV_ADDR: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x00FFFFF8 ); nkeynes@197: break; nkeynes@197: case YUV_CFG: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x01013F3F ); nkeynes@197: break; nkeynes@261: nkeynes@261: nkeynes@261: /**************** Unknowns ***************/ nkeynes@261: case PVRUNK1: nkeynes@261: MMIO_WRITE( PVR2, reg, val&0x000007FF ); nkeynes@261: break; nkeynes@261: case PVRUNK2: nkeynes@261: MMIO_WRITE( PVR2, reg, val&0x00000007 ); nkeynes@100: break; nkeynes@261: case PVRUNK3: nkeynes@261: MMIO_WRITE( PVR2, reg, val&0x000FFF3F ); nkeynes@261: break; nkeynes@261: case PVRUNK5: nkeynes@261: MMIO_WRITE( PVR2, reg, val&0x0000FFFF ); nkeynes@261: break; nkeynes@261: case PVRUNK6: nkeynes@261: MMIO_WRITE( PVR2, reg, val&0x000000FF ); nkeynes@197: break; nkeynes@197: case PVRUNK7: nkeynes@197: MMIO_WRITE( PVR2, reg, val&0x00000001 ); nkeynes@197: break; nkeynes@1: } nkeynes@1: } nkeynes@1: nkeynes@261: /** nkeynes@261: * Calculate the current read value of the syncstat register, using nkeynes@261: * the current SH4 clock time as an offset from the last timeslice. nkeynes@261: * The register reads (LSB to MSB) as: nkeynes@261: * 0..9 Current scan line nkeynes@261: * 10 Odd/even field (1 = odd, 0 = even) nkeynes@261: * 11 Display active (including border and overscan) nkeynes@261: * 12 Horizontal sync off nkeynes@261: * 13 Vertical sync off nkeynes@261: * Note this method is probably incorrect for anything other than straight nkeynes@265: * interlaced PAL/NTSC, and needs further testing. nkeynes@261: */ nkeynes@261: uint32_t pvr2_get_sync_status() nkeynes@261: { nkeynes@265: pvr2_update_raster_posn(sh4r.slice_cycle); nkeynes@265: uint32_t result = pvr2_state.line_count; nkeynes@261: nkeynes@265: if( pvr2_state.odd_even_field ) { nkeynes@261: result |= 0x0400; nkeynes@261: } nkeynes@265: if( (pvr2_state.line_count & 0x01) == pvr2_state.odd_even_field ) { nkeynes@265: if( pvr2_state.line_remainder > pvr2_state.hsync_width_ns ) { nkeynes@261: result |= 0x1000; /* !HSYNC */ nkeynes@261: } nkeynes@265: if( pvr2_state.line_count >= pvr2_state.vsync_lines ) { nkeynes@265: if( pvr2_state.line_remainder > pvr2_state.front_porch_ns ) { nkeynes@261: result |= 0x2800; /* Display active */ nkeynes@261: } else { nkeynes@261: result |= 0x2000; /* Front porch */ nkeynes@261: } nkeynes@261: } nkeynes@261: } else { nkeynes@269: if( pvr2_state.line_count >= pvr2_state.vsync_lines ) { nkeynes@269: if( pvr2_state.line_remainder < (pvr2_state.line_time_ns - pvr2_state.back_porch_ns)) { nkeynes@269: result |= 0x3800; /* Display active */ nkeynes@269: } else { nkeynes@269: result |= 0x3000; nkeynes@269: } nkeynes@261: } else { nkeynes@261: result |= 0x1000; /* Back porch */ nkeynes@261: } nkeynes@261: } nkeynes@261: return result; nkeynes@261: } nkeynes@261: nkeynes@265: /** nkeynes@265: * Schedule an event for the start of the given line. If the line is actually nkeynes@265: * the current line, schedules it for the next field. nkeynes@265: * The raster position should be updated before calling this method. nkeynes@265: */ nkeynes@265: static void pvr2_schedule_line_event( int eventid, int line ) nkeynes@265: { nkeynes@265: uint32_t time; nkeynes@265: if( line <= pvr2_state.line_count ) { nkeynes@265: time = (pvr2_state.total_lines - pvr2_state.line_count + line) * pvr2_state.line_time_ns nkeynes@265: - pvr2_state.line_remainder; nkeynes@265: } else { nkeynes@265: time = (line - pvr2_state.line_count) * pvr2_state.line_time_ns - pvr2_state.line_remainder; nkeynes@265: } nkeynes@265: nkeynes@265: if( line < pvr2_state.total_lines ) { nkeynes@265: event_schedule( eventid, time ); nkeynes@265: } else { nkeynes@265: event_cancel( eventid ); nkeynes@265: } nkeynes@265: } nkeynes@265: nkeynes@265: /** nkeynes@265: * Schedule a "scanline" event. This actually goes off at nkeynes@265: * 2 * line in even fields and 2 * line + 1 in odd fields. nkeynes@265: * Otherwise this behaves as per pvr2_schedule_line_event(). nkeynes@265: * The raster position should be updated before calling this nkeynes@265: * method. nkeynes@265: */ nkeynes@274: static void pvr2_schedule_scanline_event( int eventid, int line, int minimum_lines ) nkeynes@265: { nkeynes@265: uint32_t field = pvr2_state.odd_even_field; nkeynes@265: if( line <= pvr2_state.line_count && pvr2_state.interlaced ) { nkeynes@265: field = !field; nkeynes@265: } nkeynes@265: nkeynes@265: line <<= 1; nkeynes@265: if( field ) { nkeynes@265: line += 1; nkeynes@265: } nkeynes@274: nkeynes@274: if( line < pvr2_state.total_lines ) { nkeynes@274: uint32_t lines; nkeynes@274: uint32_t time; nkeynes@274: if( line <= pvr2_state.line_count ) { nkeynes@274: lines = (pvr2_state.total_lines - pvr2_state.line_count + line); nkeynes@274: } else { nkeynes@274: lines = (line - pvr2_state.line_count); nkeynes@274: } nkeynes@274: if( lines <= minimum_lines ) { nkeynes@274: lines += pvr2_state.total_lines; nkeynes@274: } nkeynes@274: time = (lines * pvr2_state.line_time_ns) - pvr2_state.line_remainder; nkeynes@274: event_schedule( eventid, time ); nkeynes@274: } else { nkeynes@274: event_cancel( eventid ); nkeynes@274: } nkeynes@265: } nkeynes@265: nkeynes@1: MMIO_REGION_READ_FN( PVR2, reg ) nkeynes@1: { nkeynes@1: switch( reg ) { nkeynes@261: case DISP_SYNCSTAT: nkeynes@261: return pvr2_get_sync_status(); nkeynes@1: default: nkeynes@1: return MMIO_READ( PVR2, reg ); nkeynes@1: } nkeynes@1: } nkeynes@19: nkeynes@85: MMIO_REGION_DEFFNS( PVR2PAL ) nkeynes@85: nkeynes@19: void pvr2_set_base_address( uint32_t base ) nkeynes@19: { nkeynes@197: mmio_region_PVR2_write( DISP_ADDR1, base ); nkeynes@19: } nkeynes@56: nkeynes@56: nkeynes@65: nkeynes@98: nkeynes@56: int32_t mmio_region_PVR2TA_read( uint32_t reg ) nkeynes@56: { nkeynes@56: return 0xFFFFFFFF; nkeynes@56: } nkeynes@56: nkeynes@56: void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val ) nkeynes@56: { nkeynes@189: pvr2_ta_write( (char *)&val, sizeof(uint32_t) ); nkeynes@56: } nkeynes@56: nkeynes@85: nkeynes@103: void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length ) nkeynes@103: { nkeynes@103: int bank_flag = (destaddr & 0x04) >> 2; nkeynes@103: uint32_t *banks[2]; nkeynes@103: uint32_t *dwsrc; nkeynes@103: int i; nkeynes@65: nkeynes@103: destaddr = destaddr & 0x7FFFFF; nkeynes@103: if( destaddr + length > 0x800000 ) { nkeynes@103: length = 0x800000 - destaddr; nkeynes@103: } nkeynes@103: nkeynes@103: for( i=destaddr & 0xFFFFF000; i < destaddr + length; i+= PAGE_SIZE ) { nkeynes@103: texcache_invalidate_page( i ); nkeynes@103: } nkeynes@103: nkeynes@108: banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1))); nkeynes@103: banks[1] = banks[0] + 0x100000; nkeynes@108: if( bank_flag ) nkeynes@108: banks[0]++; nkeynes@103: nkeynes@103: /* Handle non-aligned start of source */ nkeynes@103: if( destaddr & 0x03 ) { nkeynes@103: char *dest = ((char *)banks[bank_flag]) + (destaddr & 0x03); nkeynes@103: for( i= destaddr & 0x03; i < 4 && length > 0; i++, length-- ) { nkeynes@103: *dest++ = *src++; nkeynes@103: } nkeynes@103: bank_flag = !bank_flag; nkeynes@103: } nkeynes@103: nkeynes@103: dwsrc = (uint32_t *)src; nkeynes@103: while( length >= 4 ) { nkeynes@103: *banks[bank_flag]++ = *dwsrc++; nkeynes@103: bank_flag = !bank_flag; nkeynes@103: length -= 4; nkeynes@103: } nkeynes@103: nkeynes@103: /* Handle non-aligned end of source */ nkeynes@103: if( length ) { nkeynes@103: src = (char *)dwsrc; nkeynes@103: char *dest = (char *)banks[bank_flag]; nkeynes@103: while( length-- > 0 ) { nkeynes@103: *dest++ = *src++; nkeynes@103: } nkeynes@103: } nkeynes@218: } nkeynes@103: nkeynes@282: /** nkeynes@282: * Write an image to 64-bit vram, with a line-stride different from the line-size. nkeynes@282: * The destaddr must be 32-bit aligned, and both line_bytes and line_stride_bytes nkeynes@282: * must be multiples of 4. nkeynes@282: */ nkeynes@282: void pvr2_vram64_write_stride( sh4addr_t destaddr, char *src, uint32_t line_bytes, nkeynes@282: uint32_t line_stride_bytes, uint32_t line_count ) nkeynes@282: { nkeynes@282: int bank_flag = (destaddr & 0x04) >> 2; nkeynes@282: uint32_t *banks[2]; nkeynes@282: uint32_t *dwsrc; nkeynes@282: uint32_t line_gap; nkeynes@282: int line_gap_flag; nkeynes@282: int i,j; nkeynes@282: nkeynes@282: destaddr = destaddr & 0x7FFFF8; nkeynes@282: i = line_stride_bytes - line_bytes; nkeynes@282: line_gap_flag = i & 0x04; nkeynes@282: line_gap = i >> 3; nkeynes@282: nkeynes@282: nkeynes@282: for( i=destaddr & 0xFFFFF000; i < destaddr + line_stride_bytes*line_count; i+= PAGE_SIZE ) { nkeynes@282: texcache_invalidate_page( i ); nkeynes@282: } nkeynes@282: nkeynes@282: banks[0] = (uint32_t *)(video_base + (destaddr >>1)); nkeynes@282: banks[1] = banks[0] + 0x100000; nkeynes@282: if( bank_flag ) nkeynes@282: banks[0]++; nkeynes@282: nkeynes@282: dwsrc = (uint32_t *)src; nkeynes@282: for( i=0; i= src ) { nkeynes@218: memcpy( dest, p, line_length ); nkeynes@218: p -= line_length; nkeynes@218: dest += line_length; nkeynes@218: } nkeynes@103: } nkeynes@103: nkeynes@103: void pvr2_vram64_read( char *dest, sh4addr_t srcaddr, uint32_t length ) nkeynes@103: { nkeynes@103: int bank_flag = (srcaddr & 0x04) >> 2; nkeynes@103: uint32_t *banks[2]; nkeynes@103: uint32_t *dwdest; nkeynes@103: int i; nkeynes@103: nkeynes@103: srcaddr = srcaddr & 0x7FFFFF; nkeynes@103: if( srcaddr + length > 0x800000 ) nkeynes@103: length = 0x800000 - srcaddr; nkeynes@103: nkeynes@108: banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1))); nkeynes@103: banks[1] = banks[0] + 0x100000; nkeynes@108: if( bank_flag ) nkeynes@108: banks[0]++; nkeynes@103: nkeynes@103: /* Handle non-aligned start of source */ nkeynes@103: if( srcaddr & 0x03 ) { nkeynes@103: char *src = ((char *)banks[bank_flag]) + (srcaddr & 0x03); nkeynes@103: for( i= srcaddr & 0x03; i < 4 && length > 0; i++, length-- ) { nkeynes@103: *dest++ = *src++; nkeynes@103: } nkeynes@103: bank_flag = !bank_flag; nkeynes@103: } nkeynes@103: nkeynes@103: dwdest = (uint32_t *)dest; nkeynes@103: while( length >= 4 ) { nkeynes@103: *dwdest++ = *banks[bank_flag]++; nkeynes@103: bank_flag = !bank_flag; nkeynes@103: length -= 4; nkeynes@103: } nkeynes@103: nkeynes@103: /* Handle non-aligned end of source */ nkeynes@103: if( length ) { nkeynes@103: dest = (char *)dwdest; nkeynes@103: char *src = (char *)banks[bank_flag]; nkeynes@103: while( length-- > 0 ) { nkeynes@103: *dest++ = *src++; nkeynes@103: } nkeynes@103: } nkeynes@103: } nkeynes@127: nkeynes@127: void pvr2_vram64_dump( sh4addr_t addr, uint32_t length, FILE *f ) nkeynes@127: { nkeynes@127: char tmp[length]; nkeynes@127: pvr2_vram64_read( tmp, addr, length ); nkeynes@127: fwrite_dump( tmp, length, f ); nkeynes@127: }