nkeynes@1: #include "dream.h"
nkeynes@1: #include "mem.h"
nkeynes@1: #include "sh4core.h"
nkeynes@1: #include "sh4mmio.h"
nkeynes@1: #define MMIO_IMPL
nkeynes@1: #include "sh4mmio.h"
nkeynes@1: 
nkeynes@1: /********************************* MMU *************************************/
nkeynes@1: 
nkeynes@1: MMIO_REGION_READ_STUBFN( MMU )
nkeynes@1: 
nkeynes@10: #define OCRAM_START (0x1C000000>>PAGE_BITS)
nkeynes@10: #define OCRAM_END   (0x20000000>>PAGE_BITS)
nkeynes@10: 
nkeynes@10: static char *cache = NULL;
nkeynes@10: 
nkeynes@1: void mmio_region_MMU_write( uint32_t reg, uint32_t val )
nkeynes@1: {
nkeynes@1:     switch(reg) {
nkeynes@1:         case CCR:
nkeynes@10:             mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
nkeynes@1:             INFO( "Cache mode set to %08X", val );
nkeynes@1:             break;
nkeynes@1:         default:
nkeynes@1:             break;
nkeynes@1:     }
nkeynes@1:     MMIO_WRITE( MMU, reg, val );
nkeynes@1: }
nkeynes@1: 
nkeynes@1: 
nkeynes@10: void mmu_init() 
nkeynes@10: {
nkeynes@10:   cache = mem_alloc_pages(2);
nkeynes@10: }
nkeynes@10: 
nkeynes@10: void mmu_set_cache_mode( int mode )
nkeynes@10: {
nkeynes@10:     uint32_t i;
nkeynes@10:     switch( mode ) {
nkeynes@10:         case MEM_OC_INDEX0: /* OIX=0 */
nkeynes@10:             for( i=OCRAM_START; i<OCRAM_END; i++ )
nkeynes@10:                 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
nkeynes@10:             break;
nkeynes@10:         case MEM_OC_INDEX1: /* OIX=1 */
nkeynes@10:             for( i=OCRAM_START; i<OCRAM_END; i++ )
nkeynes@10:                 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
nkeynes@10:             break;
nkeynes@10:         default: /* disabled */
nkeynes@10:             for( i=OCRAM_START; i<OCRAM_END; i++ )
nkeynes@10:                 page_map[i] = NULL;
nkeynes@10:             break;
nkeynes@10:     }
nkeynes@10: }
nkeynes@10: 
nkeynes@10: 
nkeynes@1: /********************************* BSC *************************************/
nkeynes@1: 
nkeynes@1: uint16_t bsc_output_mask_lo = 0, bsc_output_mask_hi = 0;
nkeynes@1: uint16_t bsc_input_mask_lo = 0, bsc_input_mask_hi = 0;
nkeynes@1: uint32_t bsc_output = 0, bsc_input = 0x0300;
nkeynes@1: 
nkeynes@1: void bsc_out( int output, int mask )
nkeynes@1: {
nkeynes@1:     /* Go figure... The BIOS won't start without this mess though */
nkeynes@1:     if( ((output | (~mask)) & 0x03) == 3 ) {
nkeynes@1:         bsc_output |= 0x03;
nkeynes@1:     } else {
nkeynes@1:         bsc_output &= ~0x03;
nkeynes@1:     }
nkeynes@1: }
nkeynes@1: 
nkeynes@1: void mmio_region_BSC_write( uint32_t reg, uint32_t val )
nkeynes@1: {
nkeynes@1:     int i;
nkeynes@1:     switch( reg ) {
nkeynes@1:         case PCTRA:
nkeynes@1:             bsc_input_mask_lo = bsc_output_mask_lo = 0;
nkeynes@1:             for( i=0; i<16; i++ ) {
nkeynes@1:                 int bits = (val >> (i<<1)) & 0x03;
nkeynes@1:                 if( bits == 2 ) bsc_input_mask_lo |= (1<<i);
nkeynes@1:                 else if( bits != 0 ) bsc_output_mask_lo |= (1<<i);
nkeynes@1:             }
nkeynes@1:             bsc_output = (bsc_output&0x000F0000) |
nkeynes@1:                 (MMIO_READ( BSC, PDTRA ) & bsc_output_mask_lo);
nkeynes@1:             bsc_out( MMIO_READ( BSC, PDTRA ) | ((MMIO_READ(BSC,PDTRB)<<16)),
nkeynes@1:                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
nkeynes@1:             break;
nkeynes@1:         case PCTRB:
nkeynes@1:             bsc_input_mask_hi = bsc_output_mask_hi = 0;
nkeynes@1:             for( i=0; i<4; i++ ) {
nkeynes@1:                 int bits = (val >> (i>>1)) & 0x03;
nkeynes@1:                 if( bits == 2 ) bsc_input_mask_hi |= (1<<i);
nkeynes@1:                 else if( bits != 0 ) bsc_output_mask_hi |= (1<<i);
nkeynes@1:             }
nkeynes@1:             bsc_output = (bsc_output&0xFFFF) |
nkeynes@1:                 ((MMIO_READ( BSC, PDTRA ) & bsc_output_mask_hi)<<16);
nkeynes@1:             break;
nkeynes@1:         case PDTRA:
nkeynes@1:             bsc_output = (bsc_output&0x000F0000) |
nkeynes@1:                 (val & bsc_output_mask_lo );
nkeynes@1:             bsc_out( val | ((MMIO_READ(BSC,PDTRB)<<16)),
nkeynes@1:                      bsc_output_mask_lo | (bsc_output_mask_hi<<16) );
nkeynes@1:             break;
nkeynes@1:         case PDTRB:
nkeynes@1:             bsc_output = (bsc_output&0xFFFF) |
nkeynes@1:                 ( (val & bsc_output_mask_hi)<<16 );
nkeynes@1:             break;
nkeynes@1:     }
nkeynes@1:     WARN( "Write to (mostly) unimplemented BSC (%03X <= %08X) [%s: %s]",
nkeynes@1:           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
nkeynes@1:     MMIO_WRITE( BSC, reg, val );
nkeynes@1: }
nkeynes@1: 
nkeynes@1: int32_t mmio_region_BSC_read( uint32_t reg )
nkeynes@1: {
nkeynes@1:     int32_t val;
nkeynes@1:     switch( reg ) {
nkeynes@1:         case PDTRA:
nkeynes@1:             val = (bsc_input & bsc_input_mask_lo) | (bsc_output&0xFFFF);
nkeynes@1:             break;
nkeynes@1:         case PDTRB:
nkeynes@1:             val = ((bsc_input>>16) & bsc_input_mask_hi) | (bsc_output>>16);
nkeynes@1:             break;
nkeynes@1:         default:
nkeynes@1:             val = MMIO_READ( BSC, reg );
nkeynes@1:     }
nkeynes@1:     WARN( "Read from (mostly) unimplemented BSC (%03X => %08X) [%s: %s]",
nkeynes@1:           reg, val, MMIO_REGID(BSC,reg), MMIO_REGDESC(BSC,reg) );
nkeynes@1:     return val;
nkeynes@1: }
nkeynes@1: 
nkeynes@1: /********************************* UBC *************************************/
nkeynes@1: 
nkeynes@1: MMIO_REGION_STUBFNS( UBC )
nkeynes@1: 
nkeynes@1: /********************************* CPG *************************************/
nkeynes@1: 
nkeynes@1: MMIO_REGION_STUBFNS( CPG )
nkeynes@1: 
nkeynes@1: /********************************* DMAC *************************************/
nkeynes@1: 
nkeynes@1: MMIO_REGION_STUBFNS( DMAC )
nkeynes@1: 
nkeynes@1: /********************************** RTC *************************************/
nkeynes@1: 
nkeynes@1: MMIO_REGION_STUBFNS( RTC )
nkeynes@1: 
nkeynes@1: /********************************** TMU *************************************/
nkeynes@1: 
nkeynes@1: int timer_divider[3] = {16,16,16};
nkeynes@1: MMIO_REGION_READ_DEFFN( TMU )
nkeynes@1: 
nkeynes@1: int get_timer_div( int val )
nkeynes@1: {
nkeynes@1:     switch( val & 0x07 ) {
nkeynes@1:         case 0: return 16; /* assume peripheral clock is IC/4 */
nkeynes@1:         case 1: return 64;
nkeynes@1:         case 2: return 256;
nkeynes@1:         case 3: return 1024;
nkeynes@1:         case 4: return 4096;
nkeynes@1:     }
nkeynes@1:     return 1;
nkeynes@1: }
nkeynes@1: 
nkeynes@1: void mmio_region_TMU_write( uint32_t reg, uint32_t val )
nkeynes@1: {
nkeynes@1:     switch( reg ) {
nkeynes@1:         case TCR0:
nkeynes@1:             timer_divider[0] = get_timer_div(val);
nkeynes@1:             break;
nkeynes@1:         case TCR1:
nkeynes@1:             timer_divider[1] = get_timer_div(val);
nkeynes@1:             break;
nkeynes@1:         case TCR2:
nkeynes@1:             timer_divider[2] = get_timer_div(val);
nkeynes@1:             break;
nkeynes@1:     }
nkeynes@1:     MMIO_WRITE( TMU, reg, val );
nkeynes@1: }
nkeynes@1: 
nkeynes@1: void run_timers( int cycles )
nkeynes@1: {
nkeynes@1:     int tcr = MMIO_READ( TMU, TSTR );
nkeynes@1:     cycles *= 16;
nkeynes@1:     if( tcr & 1 ) {
nkeynes@1:         int count = cycles / timer_divider[0];
nkeynes@1:         int *val = MMIO_REG( TMU, TCNT0 );
nkeynes@1:         if( *val < count ) {
nkeynes@1:             MMIO_READ( TMU, TCR0 ) |= 0x100;
nkeynes@1:             /* interrupt goes here */
nkeynes@1:             count -= *val;
nkeynes@1:             *val = MMIO_READ( TMU, TCOR0 ) - count;
nkeynes@1:         } else {
nkeynes@1:             *val -= count;
nkeynes@1:         }
nkeynes@1:     }
nkeynes@1: }
nkeynes@1: 
nkeynes@1: /********************************** SCI *************************************/
nkeynes@1: 
nkeynes@1: MMIO_REGION_STUBFNS( SCI )
nkeynes@1: 
nkeynes@1: /********************************* SCIF *************************************/
nkeynes@1: 
nkeynes@1: MMIO_REGION_STUBFNS( SCIF )
nkeynes@1: