nkeynes@10: /** nkeynes@391: * $Id: sh4core.h,v 1.24 2007-09-18 09:14:20 nkeynes Exp $ nkeynes@10: * nkeynes@54: * This file defines the internal functions exported/used by the SH4 core, nkeynes@54: * except for disassembly functions defined in sh4dasm.h nkeynes@10: * nkeynes@10: * Copyright (c) 2005 Nathan Keynes. nkeynes@10: * nkeynes@10: * This program is free software; you can redistribute it and/or modify nkeynes@10: * it under the terms of the GNU General Public License as published by nkeynes@10: * the Free Software Foundation; either version 2 of the License, or nkeynes@10: * (at your option) any later version. nkeynes@10: * nkeynes@10: * This program is distributed in the hope that it will be useful, nkeynes@10: * but WITHOUT ANY WARRANTY; without even the implied warranty of nkeynes@10: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the nkeynes@10: * GNU General Public License for more details. nkeynes@1: */ nkeynes@30: nkeynes@1: #ifndef sh4core_H nkeynes@1: #define sh4core_H 1 nkeynes@1: nkeynes@27: #include nkeynes@1: #include nkeynes@23: #include nkeynes@378: #include "mem.h" nkeynes@1: nkeynes@1: #ifdef __cplusplus nkeynes@1: extern "C" { nkeynes@1: #if 0 nkeynes@1: } nkeynes@1: #endif nkeynes@1: #endif nkeynes@1: nkeynes@27: nkeynes@27: /** nkeynes@27: * SH4 is running normally nkeynes@27: */ nkeynes@27: #define SH4_STATE_RUNNING 1 nkeynes@27: /** nkeynes@27: * SH4 is not executing instructions but all peripheral modules are still nkeynes@27: * running nkeynes@27: */ nkeynes@27: #define SH4_STATE_SLEEP 2 nkeynes@27: /** nkeynes@27: * SH4 is not executing instructions, DMAC is halted, but all other peripheral nkeynes@27: * modules are still running nkeynes@27: */ nkeynes@27: #define SH4_STATE_DEEP_SLEEP 3 nkeynes@27: /** nkeynes@27: * SH4 is not executing instructions and all peripheral modules are also nkeynes@27: * stopped. As close as you can get to powered-off without actually being nkeynes@27: * off. nkeynes@27: */ nkeynes@27: #define SH4_STATE_STANDBY 4 nkeynes@27: nkeynes@265: #define PENDING_IRQ 1 nkeynes@265: #define PENDING_EVENT 2 nkeynes@265: nkeynes@1: struct sh4_registers { nkeynes@1: uint32_t r[16]; nkeynes@374: uint32_t sr, pr, pc, fpscr; nkeynes@374: uint32_t t, m, q, s; /* really boolean - 0 or 1 */ nkeynes@374: int32_t fpul; nkeynes@374: float *fr_bank; nkeynes@374: float fr[2][16]; nkeynes@374: uint64_t mac; nkeynes@374: uint32_t gbr, ssr, spc, sgr, dbr, vbr; nkeynes@374: nkeynes@1: uint32_t r_bank[8]; /* hidden banked registers */ nkeynes@2: int32_t store_queue[16]; /* technically 2 banks of 32 bytes */ nkeynes@2: nkeynes@1: uint32_t new_pc; /* Not a real register, but used to handle delay slots */ nkeynes@265: uint32_t event_pending; /* slice cycle time of the next pending event, or FFFFFFFF nkeynes@265: when no events are pending */ nkeynes@265: uint32_t event_types; /* bit 0 = IRQ pending, bit 1 = general event pending */ nkeynes@2: int in_delay_slot; /* flag to indicate the current instruction is in nkeynes@2: * a delay slot (certain rules apply) */ nkeynes@302: uint32_t slice_cycle; /* Current nanosecond within the timeslice */ nkeynes@27: int sh4_state; /* Current power-on state (one of the SH4_STATE_* values ) */ nkeynes@1: }; nkeynes@1: nkeynes@1: extern struct sh4_registers sh4r; nkeynes@378: extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS]; nkeynes@378: extern int sh4_breakpoint_count; nkeynes@378: nkeynes@1: nkeynes@1: /* Public functions */ nkeynes@378: void sh4_set_use_xlat( gboolean use ); nkeynes@1: void sh4_init( void ); nkeynes@1: void sh4_reset( void ); nkeynes@1: void sh4_run( void ); nkeynes@1: void sh4_runto( uint32_t pc, uint32_t count ); nkeynes@1: void sh4_runfor( uint32_t count ); nkeynes@1: int sh4_isrunning( void ); nkeynes@1: void sh4_stop( void ); nkeynes@1: void sh4_set_pc( int ); nkeynes@378: nkeynes@27: gboolean sh4_execute_instruction( void ); nkeynes@246: gboolean sh4_raise_exception( int ); nkeynes@391: gboolean sh4_raise_trap( int ); nkeynes@246: gboolean sh4_raise_slot_exception( int, int ); nkeynes@246: gboolean sh4_raise_tlb_exception( int ); nkeynes@23: void sh4_set_breakpoint( uint32_t pc, int type ); nkeynes@43: gboolean sh4_clear_breakpoint( uint32_t pc, int type ); nkeynes@43: int sh4_get_breakpoint( uint32_t pc ); nkeynes@378: void sh4_accept_interrupt( void ); nkeynes@23: nkeynes@23: #define BREAK_ONESHOT 1 nkeynes@23: #define BREAK_PERM 2 nkeynes@1: nkeynes@10: /* SH4 Memory */ nkeynes@10: int32_t sh4_read_long( uint32_t addr ); nkeynes@10: int32_t sh4_read_word( uint32_t addr ); nkeynes@10: int32_t sh4_read_byte( uint32_t addr ); nkeynes@10: void sh4_write_long( uint32_t addr, uint32_t val ); nkeynes@10: void sh4_write_word( uint32_t addr, uint32_t val ); nkeynes@10: void sh4_write_byte( uint32_t addr, uint32_t val ); nkeynes@10: int32_t sh4_read_phys_word( uint32_t addr ); nkeynes@369: void sh4_flush_store_queue( uint32_t addr ); nkeynes@10: nkeynes@374: /* SH4 Support methods */ nkeynes@374: uint32_t sh4_read_sr(void); nkeynes@374: void sh4_write_sr(uint32_t val); nkeynes@374: nkeynes@23: /* Peripheral functions */ nkeynes@260: void CPG_reset( void ); nkeynes@30: void TMU_run_slice( uint32_t ); nkeynes@53: void TMU_update_clocks( void ); nkeynes@53: void TMU_reset( void ); nkeynes@53: void TMU_save_state( FILE * ); nkeynes@53: int TMU_load_state( FILE * ); nkeynes@54: void DMAC_reset( void ); nkeynes@54: void DMAC_run_slice( uint32_t ); nkeynes@54: void DMAC_save_state( FILE * ); nkeynes@54: int DMAC_load_state( FILE * ); nkeynes@32: void SCIF_reset( void ); nkeynes@30: void SCIF_run_slice( uint32_t ); nkeynes@23: void SCIF_save_state( FILE *f ); nkeynes@23: int SCIF_load_state( FILE *f ); nkeynes@157: void INTC_reset( void ); nkeynes@157: void INTC_save_state( FILE *f ); nkeynes@157: int INTC_load_state( FILE *f ); nkeynes@312: void MMU_init( void ); nkeynes@312: void MMU_reset( void ); nkeynes@312: void MMU_save_state( FILE *f ); nkeynes@312: int MMU_load_state( FILE *f ); nkeynes@1: nkeynes@1: #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28) nkeynes@1: #define SIGNEXT8(n) ((int32_t)((int8_t)(n))) nkeynes@1: #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20) nkeynes@1: #define SIGNEXT16(n) ((int32_t)((int16_t)(n))) nkeynes@1: #define SIGNEXT32(n) ((int64_t)((int32_t)(n))) nkeynes@1: #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16) nkeynes@1: nkeynes@1: /* Status Register (SR) bits */ nkeynes@1: #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ nkeynes@1: #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */ nkeynes@1: #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */ nkeynes@1: #define SR_FD 0x00008000 /* FPU disable */ nkeynes@1: #define SR_M 0x00000200 nkeynes@1: #define SR_Q 0x00000100 nkeynes@1: #define SR_IMASK 0x000000F0 /* Interrupt mask level */ nkeynes@1: #define SR_S 0x00000002 /* Saturation operation for MAC instructions */ nkeynes@1: #define SR_T 0x00000001 /* True/false or carry/borrow */ nkeynes@1: #define SR_MASK 0x700083F3 nkeynes@1: #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */ nkeynes@1: nkeynes@1: #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD) nkeynes@1: #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4) nkeynes@265: #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot) nkeynes@1: nkeynes@1: #define FPSCR_FR 0x00200000 /* FPU register bank */ nkeynes@1: #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */ nkeynes@1: #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */ nkeynes@1: #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */ nkeynes@1: #define FPSCR_CAUSE 0x0003F000 nkeynes@1: #define FPSCR_ENABLE 0x00000F80 nkeynes@1: #define FPSCR_FLAG 0x0000007C nkeynes@1: #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */ nkeynes@1: nkeynes@1: #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR) nkeynes@1: #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ) nkeynes@1: #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0) nkeynes@1: nkeynes@374: #define FR(x) sh4r.fr_bank[(x)^1] nkeynes@374: #define DRF(x) ((double *)sh4r.fr_bank)[x] nkeynes@84: #define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1] nkeynes@95: #define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x] nkeynes@95: #define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x] nkeynes@359: #define DR(x) DRb((x>>1), (x&1)) nkeynes@359: #define FPULf *((float *)&sh4r.fpul) nkeynes@359: #define FPULi (sh4r.fpul) nkeynes@359: nkeynes@367: /* CPU-generated exception code/vector pairs */ nkeynes@367: #define EXC_POWER_RESET 0x000 /* vector special */ nkeynes@367: #define EXC_MANUAL_RESET 0x020 nkeynes@367: #define EXC_DATA_ADDR_READ 0x0E0 nkeynes@367: #define EXC_DATA_ADDR_WRITE 0x100 nkeynes@367: #define EXC_SLOT_ILLEGAL 0x1A0 nkeynes@367: #define EXC_ILLEGAL 0x180 nkeynes@367: #define EXC_TRAP 0x160 nkeynes@367: #define EXC_FPU_DISABLED 0x800 nkeynes@367: #define EXC_SLOT_FPU_DISABLED 0x820 nkeynes@367: nkeynes@1: /* Exceptions (for use with sh4_raise_exception) */ nkeynes@1: nkeynes@1: #define EX_ILLEGAL_INSTRUCTION 0x180, 0x100 nkeynes@1: #define EX_SLOT_ILLEGAL 0x1A0, 0x100 nkeynes@1: #define EX_TLB_MISS_READ 0x040, 0x400 nkeynes@1: #define EX_TLB_MISS_WRITE 0x060, 0x400 nkeynes@1: #define EX_INIT_PAGE_WRITE 0x080, 0x100 nkeynes@1: #define EX_TLB_PROT_READ 0x0A0, 0x100 nkeynes@1: #define EX_TLB_PROT_WRITE 0x0C0, 0x100 nkeynes@1: #define EX_DATA_ADDR_READ 0x0E0, 0x100 nkeynes@1: #define EX_DATA_ADDR_WRITE 0x100, 0x100 nkeynes@1: #define EX_FPU_EXCEPTION 0x120, 0x100 nkeynes@1: #define EX_TRAPA 0x160, 0x100 nkeynes@1: #define EX_BREAKPOINT 0x1E0, 0x100 nkeynes@1: #define EX_FPU_DISABLED 0x800, 0x100 nkeynes@1: #define EX_SLOT_FPU_DISABLED 0x820, 0x100 nkeynes@1: nkeynes@2: #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val; nkeynes@1: nkeynes@1: #ifdef __cplusplus nkeynes@1: } nkeynes@1: #endif nkeynes@1: #endif nkeynes@359: