nkeynes@30: /** nkeynes@35: * $Id: armcore.c,v 1.6 2005-12-26 03:54:55 nkeynes Exp $ nkeynes@30: * nkeynes@30: * ARM7TDMI CPU emulation core. nkeynes@30: * nkeynes@30: * Copyright (c) 2005 Nathan Keynes. nkeynes@30: * nkeynes@30: * This program is free software; you can redistribute it and/or modify nkeynes@30: * it under the terms of the GNU General Public License as published by nkeynes@30: * the Free Software Foundation; either version 2 of the License, or nkeynes@30: * (at your option) any later version. nkeynes@30: * nkeynes@30: * This program is distributed in the hope that it will be useful, nkeynes@30: * but WITHOUT ANY WARRANTY; without even the implied warranty of nkeynes@30: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the nkeynes@30: * GNU General Public License for more details. nkeynes@30: */ nkeynes@2: nkeynes@7: #include "aica/armcore.h" nkeynes@2: nkeynes@2: struct arm_registers armr; nkeynes@2: nkeynes@35: void arm_set_mode( int mode ); nkeynes@35: nkeynes@35: uint32_t arm_exceptions[][2] = {{ MODE_SVC, 0x00000000 }, nkeynes@35: { MODE_UND, 0x00000004 }, nkeynes@35: { MODE_SVC, 0x00000008 }, nkeynes@35: { MODE_ABT, 0x0000000C }, nkeynes@35: { MODE_ABT, 0x00000010 }, nkeynes@35: { MODE_IRQ, 0x00000018 }, nkeynes@35: { MODE_FIQ, 0x0000001C } }; nkeynes@35: nkeynes@35: #define EXC_RESET 0 nkeynes@35: #define EXC_UNDEFINED 1 nkeynes@35: #define EXC_SOFTWARE 2 nkeynes@35: #define EXC_PREFETCH_ABORT 3 nkeynes@35: #define EXC_DATA_ABORT 4 nkeynes@35: #define EXC_IRQ 5 nkeynes@35: #define EXC_FAST_IRQ 6 nkeynes@35: nkeynes@35: uint32_t arm_cpu_freq = ARM_BASE_RATE; nkeynes@35: uint32_t arm_cpu_period = 1000 / ARM_BASE_RATE; nkeynes@35: nkeynes@35: uint32_t arm_run_slice( uint32_t nanosecs ) nkeynes@35: { nkeynes@35: uint32_t target = armr.icount + nanosecs / arm_cpu_period; nkeynes@35: uint32_t start = armr.icount; nkeynes@35: while( armr.icount < target ) { nkeynes@35: armr.icount++; nkeynes@35: if( !arm_execute_instruction() ) nkeynes@35: break; nkeynes@35: } nkeynes@35: nkeynes@35: if( target != armr.icount ) { nkeynes@35: /* Halted - compute time actually executed */ nkeynes@35: nanosecs = (armr.icount - start) * arm_cpu_period; nkeynes@35: } nkeynes@35: return nanosecs; nkeynes@35: } nkeynes@35: nkeynes@35: void arm_save_state( FILE *f ) nkeynes@35: { nkeynes@35: fwrite( &armr, sizeof(armr), 1, f ); nkeynes@35: } nkeynes@35: nkeynes@35: int arm_load_state( FILE *f ) nkeynes@35: { nkeynes@35: fread( &armr, sizeof(armr), 1, f ); nkeynes@35: return 0; nkeynes@35: } nkeynes@35: nkeynes@35: /* Exceptions */ nkeynes@35: void arm_reset( void ) nkeynes@35: { nkeynes@35: /* Wipe all processor state */ nkeynes@35: memset( &armr, 0, sizeof(armr) ); nkeynes@35: nkeynes@35: armr.cpsr = MODE_SVC | CPSR_I | CPSR_F; nkeynes@35: armr.r[15] = 0x00000000; nkeynes@35: } nkeynes@35: nkeynes@35: /** nkeynes@35: * Raise an ARM exception (other than reset, which uses arm_reset(). nkeynes@35: * @param exception one of the EXC_* exception codes defined above. nkeynes@35: */ nkeynes@35: void arm_raise_exception( int exception ) nkeynes@35: { nkeynes@35: int mode = arm_exceptions[exception][0]; nkeynes@35: arm_set_mode( mode ); nkeynes@35: armr.spsr = armr.cpsr; nkeynes@35: armr.r[14] = armr.r[15]; nkeynes@35: armr.cpsr = (armr.cpsr & (~CPSR_T)) | CPSR_I; nkeynes@35: if( mode == MODE_FIQ ) nkeynes@35: armr.cpsr |= CPSR_F; nkeynes@35: armr.r[15] = arm_exceptions[exception][1]; nkeynes@35: } nkeynes@35: nkeynes@35: /** nkeynes@35: * Restore CPSR from SPSR, effectively (under most circumstances) executing nkeynes@35: * a return-from-exception. nkeynes@35: */ nkeynes@35: void arm_restore_cpsr() nkeynes@35: { nkeynes@35: int spsr = armr.spsr; nkeynes@35: int mode = spsr & CPSR_MODE; nkeynes@35: nkeynes@35: arm_set_mode( mode ); nkeynes@35: armr.cpsr = spsr; nkeynes@35: } nkeynes@35: nkeynes@35: nkeynes@35: nkeynes@35: /** nkeynes@35: * Change the current executing ARM mode to the requested mode. nkeynes@35: * Saves any required registers to banks and restores those for the nkeynes@35: * correct mode. (Note does not actually update CPSR at the moment). nkeynes@35: */ nkeynes@35: void arm_set_mode( int targetMode ) nkeynes@35: { nkeynes@35: int currentMode = armr.cpsr & CPSR_MODE; nkeynes@35: if( currentMode == targetMode ) nkeynes@35: return; nkeynes@35: nkeynes@35: switch( currentMode ) { nkeynes@35: case MODE_USER: nkeynes@35: case MODE_SYS: nkeynes@35: armr.user_r[5] = armr.r[13]; nkeynes@35: armr.user_r[6] = armr.r[14]; nkeynes@35: break; nkeynes@35: case MODE_SVC: nkeynes@35: armr.svc_r[0] = armr.r[13]; nkeynes@35: armr.svc_r[1] = armr.r[14]; nkeynes@35: armr.svc_r[2] = armr.spsr; nkeynes@35: break; nkeynes@35: case MODE_ABT: nkeynes@35: armr.abt_r[0] = armr.r[13]; nkeynes@35: armr.abt_r[1] = armr.r[14]; nkeynes@35: armr.abt_r[2] = armr.spsr; nkeynes@35: break; nkeynes@35: case MODE_UND: nkeynes@35: armr.und_r[0] = armr.r[13]; nkeynes@35: armr.und_r[1] = armr.r[14]; nkeynes@35: armr.und_r[2] = armr.spsr; nkeynes@35: break; nkeynes@35: case MODE_IRQ: nkeynes@35: armr.irq_r[0] = armr.r[13]; nkeynes@35: armr.irq_r[1] = armr.r[14]; nkeynes@35: armr.irq_r[2] = armr.spsr; nkeynes@35: break; nkeynes@35: case MODE_FIQ: nkeynes@35: armr.fiq_r[0] = armr.r[8]; nkeynes@35: armr.fiq_r[1] = armr.r[9]; nkeynes@35: armr.fiq_r[2] = armr.r[10]; nkeynes@35: armr.fiq_r[3] = armr.r[11]; nkeynes@35: armr.fiq_r[4] = armr.r[12]; nkeynes@35: armr.fiq_r[5] = armr.r[13]; nkeynes@35: armr.fiq_r[6] = armr.r[14]; nkeynes@35: armr.fiq_r[7] = armr.spsr; nkeynes@35: armr.r[8] = armr.user_r[0]; nkeynes@35: armr.r[9] = armr.user_r[1]; nkeynes@35: armr.r[10] = armr.user_r[2]; nkeynes@35: armr.r[11] = armr.user_r[3]; nkeynes@35: armr.r[12] = armr.user_r[4]; nkeynes@35: break; nkeynes@35: } nkeynes@35: nkeynes@35: switch( targetMode ) { nkeynes@35: case MODE_USER: nkeynes@35: case MODE_SYS: nkeynes@35: armr.r[13] = armr.user_r[5]; nkeynes@35: armr.r[14] = armr.user_r[6]; nkeynes@35: break; nkeynes@35: case MODE_SVC: nkeynes@35: armr.r[13] = armr.svc_r[0]; nkeynes@35: armr.r[14] = armr.svc_r[1]; nkeynes@35: armr.spsr = armr.svc_r[2]; nkeynes@35: break; nkeynes@35: case MODE_ABT: nkeynes@35: armr.r[13] = armr.abt_r[0]; nkeynes@35: armr.r[14] = armr.abt_r[1]; nkeynes@35: armr.spsr = armr.abt_r[2]; nkeynes@35: break; nkeynes@35: case MODE_UND: nkeynes@35: armr.r[13] = armr.und_r[0]; nkeynes@35: armr.r[14] = armr.und_r[1]; nkeynes@35: armr.spsr = armr.und_r[2]; nkeynes@35: break; nkeynes@35: case MODE_IRQ: nkeynes@35: armr.r[13] = armr.irq_r[0]; nkeynes@35: armr.r[14] = armr.irq_r[1]; nkeynes@35: armr.spsr = armr.irq_r[2]; nkeynes@35: break; nkeynes@35: case MODE_FIQ: nkeynes@35: armr.user_r[0] = armr.r[8]; nkeynes@35: armr.user_r[1] = armr.r[9]; nkeynes@35: armr.user_r[2] = armr.r[10]; nkeynes@35: armr.user_r[3] = armr.r[11]; nkeynes@35: armr.user_r[4] = armr.r[12]; nkeynes@35: armr.r[8] = armr.fiq_r[0]; nkeynes@35: armr.r[9] = armr.fiq_r[1]; nkeynes@35: armr.r[10] = armr.fiq_r[2]; nkeynes@35: armr.r[11] = armr.fiq_r[3]; nkeynes@35: armr.r[12] = armr.fiq_r[4]; nkeynes@35: armr.r[13] = armr.fiq_r[5]; nkeynes@35: armr.r[14] = armr.fiq_r[6]; nkeynes@35: armr.spsr = armr.fiq_r[7]; nkeynes@35: break; nkeynes@35: } nkeynes@35: } nkeynes@35: nkeynes@5: /* Page references are as per ARM DDI 0100E (June 2000) */ nkeynes@2: nkeynes@11: #define MEM_READ_BYTE( addr ) arm_read_byte(addr) nkeynes@11: #define MEM_READ_WORD( addr ) arm_read_word(addr) nkeynes@11: #define MEM_READ_LONG( addr ) arm_read_long(addr) nkeynes@11: #define MEM_WRITE_BYTE( addr, val ) arm_write_byte(addr, val) nkeynes@11: #define MEM_WRITE_WORD( addr, val ) arm_write_word(addr, val) nkeynes@11: #define MEM_WRITE_LONG( addr, val ) arm_write_long(addr, val) nkeynes@2: nkeynes@5: nkeynes@5: #define IS_NOTBORROW( result, op1, op2 ) (op2 > op1 ? 0 : 1) nkeynes@5: #define IS_CARRY( result, op1, op2 ) (result < op1 ? 1 : 0) nkeynes@5: #define IS_SUBOVERFLOW( result, op1, op2 ) (((op1^op2) & (result^op1)) >> 31) nkeynes@5: #define IS_ADDOVERFLOW( result, op1, op2 ) (((op1&op2) & (result^op1)) >> 31) nkeynes@5: nkeynes@7: #define PC armr.r[15] nkeynes@2: nkeynes@5: /* Instruction fields */ nkeynes@5: #define COND(ir) (ir>>28) nkeynes@5: #define GRP(ir) ((ir>>26)&0x03) nkeynes@5: #define OPCODE(ir) ((ir>>20)&0x1F) nkeynes@5: #define IFLAG(ir) (ir&0x02000000) nkeynes@5: #define SFLAG(ir) (ir&0x00100000) nkeynes@5: #define PFLAG(ir) (ir&0x01000000) nkeynes@5: #define UFLAG(ir) (ir&0x00800000) nkeynes@5: #define BFLAG(ir) (ir&0x00400000) nkeynes@5: #define WFLAG(ir) (IR&0x00200000) nkeynes@5: #define LFLAG(ir) SFLAG(ir) nkeynes@5: #define RN(ir) (armr.r[((ir>>16)&0x0F)] + (((ir>>16)&0x0F) == 0x0F ? 4 : 0)) nkeynes@5: #define RD(ir) (armr.r[((ir>>12)&0x0F)] + (((ir>>16)&0x0F) == 0x0F ? 4 : 0)) nkeynes@5: #define RDn(ir) ((ir>>12)&0x0F) nkeynes@5: #define RS(ir) (armr.r[((ir>>8)&0x0F)] + (((ir>>16)&0x0F) == 0x0F ? 4 : 0)) nkeynes@5: #define RM(ir) (armr.r[(ir&0x0F)] + (((ir>>16)&0x0F) == 0x0F ? 4 : 0)) nkeynes@5: #define LRN(ir) armr.r[((ir>>16)&0x0F)] nkeynes@5: #define LRD(ir) armr.r[((ir>>12)&0x0F)] nkeynes@5: #define LRS(ir) armr.r[((ir>>8)&0x0F)] nkeynes@5: #define LRM(ir) armr.r[(ir&0x0F)] nkeynes@5: nkeynes@5: #define IMM8(ir) (ir&0xFF) nkeynes@5: #define IMM12(ir) (ir&0xFFF) nkeynes@7: #define SHIFTIMM(ir) ((ir>>7)&0x1F) nkeynes@7: #define IMMROT(ir) ((ir>>7)&0x1E) nkeynes@5: #define SHIFT(ir) ((ir>>4)&0x07) nkeynes@5: #define DISP24(ir) ((ir&0x00FFFFFF)) nkeynes@30: #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", PC, ir ); return TRUE; } while(0) nkeynes@30: #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", PC, ir ); return FALSE; }while(0) nkeynes@7: nkeynes@5: static uint32_t arm_get_shift_operand( uint32_t ir ) nkeynes@5: { nkeynes@5: uint32_t operand, tmp; nkeynes@5: if( IFLAG(ir) == 0 ) { nkeynes@5: operand = RM(ir); nkeynes@5: switch(SHIFT(ir)) { nkeynes@5: case 0: /* (Rm << imm) */ nkeynes@5: operand = operand << SHIFTIMM(ir); nkeynes@5: break; nkeynes@5: case 1: /* (Rm << Rs) */ nkeynes@5: tmp = RS(ir)&0xFF; nkeynes@5: if( tmp > 31 ) operand = 0; nkeynes@5: else operand = operand << tmp; nkeynes@5: break; nkeynes@5: case 2: /* (Rm >> imm) */ nkeynes@5: operand = operand >> SHIFTIMM(ir); nkeynes@5: break; nkeynes@5: case 3: /* (Rm >> Rs) */ nkeynes@5: tmp = RS(ir) & 0xFF; nkeynes@5: if( tmp > 31 ) operand = 0; nkeynes@5: else operand = operand >> ir; nkeynes@5: break; nkeynes@5: case 4: /* (Rm >>> imm) */ nkeynes@5: tmp = SHIFTIMM(ir); nkeynes@5: if( tmp == 0 ) operand = ((int32_t)operand) >> 31; nkeynes@5: else operand = ((int32_t)operand) >> tmp; nkeynes@5: break; nkeynes@5: case 5: /* (Rm >>> Rs) */ nkeynes@5: tmp = RS(ir) & 0xFF; nkeynes@5: if( tmp > 31 ) operand = ((int32_t)operand) >> 31; nkeynes@5: else operand = ((int32_t)operand) >> tmp; nkeynes@5: break; nkeynes@5: case 6: nkeynes@5: tmp = SHIFTIMM(ir); nkeynes@5: if( tmp == 0 ) /* RRX aka rotate with carry */ nkeynes@7: operand = (operand >> 1) | (armr.c<<31); nkeynes@5: else nkeynes@5: operand = ROTATE_RIGHT_LONG(operand,tmp); nkeynes@5: break; nkeynes@5: case 7: nkeynes@5: tmp = RS(ir)&0x1F; nkeynes@5: operand = ROTATE_RIGHT_LONG(operand,tmp); nkeynes@5: break; nkeynes@5: } nkeynes@5: } else { nkeynes@5: operand = IMM8(ir); nkeynes@5: tmp = IMMROT(ir); nkeynes@5: operand = ROTATE_RIGHT_LONG(operand, tmp); nkeynes@5: } nkeynes@5: return operand; nkeynes@5: } nkeynes@5: nkeynes@5: /** nkeynes@5: * Compute the "shift operand" of the instruction for the data processing nkeynes@5: * instructions. This variant also sets armr.shift_c (carry result for shifter) nkeynes@5: * Reason for the variants is that most cases don't actually need the shift_c. nkeynes@5: */ nkeynes@5: static uint32_t arm_get_shift_operand_s( uint32_t ir ) nkeynes@5: { nkeynes@5: uint32_t operand, tmp; nkeynes@5: if( IFLAG(ir) == 0 ) { nkeynes@5: operand = RM(ir); nkeynes@5: switch(SHIFT(ir)) { nkeynes@5: case 0: /* (Rm << imm) */ nkeynes@5: tmp = SHIFTIMM(ir); nkeynes@5: if( tmp == 0 ) { /* Rm */ nkeynes@5: armr.shift_c = armr.c; nkeynes@5: } else { /* Rm << imm */ nkeynes@5: armr.shift_c = (operand >> (32-tmp)) & 0x01; nkeynes@5: operand = operand << tmp; nkeynes@5: } nkeynes@5: break; nkeynes@5: case 1: /* (Rm << Rs) */ nkeynes@5: tmp = RS(ir)&0xFF; nkeynes@5: if( tmp == 0 ) { nkeynes@5: armr.shift_c = armr.c; nkeynes@5: } else { nkeynes@5: if( tmp <= 32 ) nkeynes@5: armr.shift_c = (operand >> (32-tmp)) & 0x01; nkeynes@5: else armr.shift_c = 0; nkeynes@5: if( tmp < 32 ) nkeynes@5: operand = operand << tmp; nkeynes@5: else operand = 0; nkeynes@5: } nkeynes@5: break; nkeynes@5: case 2: /* (Rm >> imm) */ nkeynes@5: tmp = SHIFTIMM(ir); nkeynes@5: if( tmp == 0 ) { nkeynes@5: armr.shift_c = operand >> 31; nkeynes@5: operand = 0; nkeynes@5: } else { nkeynes@5: armr.shift_c = (operand >> (tmp-1)) & 0x01; nkeynes@5: operand = RM(ir) >> tmp; nkeynes@5: } nkeynes@5: break; nkeynes@5: case 3: /* (Rm >> Rs) */ nkeynes@5: tmp = RS(ir) & 0xFF; nkeynes@5: if( tmp == 0 ) { nkeynes@5: armr.shift_c = armr.c; nkeynes@5: } else { nkeynes@5: if( tmp <= 32 ) nkeynes@5: armr.shift_c = (operand >> (tmp-1))&0x01; nkeynes@5: else armr.shift_c = 0; nkeynes@5: if( tmp < 32 ) nkeynes@5: operand = operand >> tmp; nkeynes@5: else operand = 0; nkeynes@5: } nkeynes@5: break; nkeynes@5: case 4: /* (Rm >>> imm) */ nkeynes@5: tmp = SHIFTIMM(ir); nkeynes@5: if( tmp == 0 ) { nkeynes@5: armr.shift_c = operand >> 31; nkeynes@5: operand = -armr.shift_c; nkeynes@5: } else { nkeynes@5: armr.shift_c = (operand >> (tmp-1)) & 0x01; nkeynes@5: operand = ((int32_t)operand) >> tmp; nkeynes@5: } nkeynes@5: break; nkeynes@5: case 5: /* (Rm >>> Rs) */ nkeynes@5: tmp = RS(ir) & 0xFF; nkeynes@5: if( tmp == 0 ) { nkeynes@5: armr.shift_c = armr.c; nkeynes@5: } else { nkeynes@5: if( tmp < 32 ) { nkeynes@5: armr.shift_c = (operand >> (tmp-1))&0x01; nkeynes@5: operand = ((int32_t)operand) >> tmp; nkeynes@5: } else { nkeynes@5: armr.shift_c = operand >> 31; nkeynes@5: operand = ((int32_t)operand) >> 31; nkeynes@5: } nkeynes@5: } nkeynes@5: break; nkeynes@5: case 6: nkeynes@5: tmp = SHIFTIMM(ir); nkeynes@5: if( tmp == 0 ) { /* RRX aka rotate with carry */ nkeynes@5: armr.shift_c = operand&0x01; nkeynes@7: operand = (operand >> 1) | (armr.c<<31); nkeynes@5: } else { nkeynes@5: armr.shift_c = operand>>(tmp-1); nkeynes@5: operand = ROTATE_RIGHT_LONG(operand,tmp); nkeynes@5: } nkeynes@5: break; nkeynes@5: case 7: nkeynes@5: tmp = RS(ir)&0xFF; nkeynes@5: if( tmp == 0 ) { nkeynes@5: armr.shift_c = armr.c; nkeynes@5: } else { nkeynes@5: tmp &= 0x1F; nkeynes@5: if( tmp == 0 ) { nkeynes@5: armr.shift_c = operand>>31; nkeynes@5: } else { nkeynes@5: armr.shift_c = (operand>>(tmp-1))&0x1; nkeynes@5: operand = ROTATE_RIGHT_LONG(operand,tmp); nkeynes@5: } nkeynes@5: } nkeynes@5: break; nkeynes@5: } nkeynes@5: } else { nkeynes@5: operand = IMM8(ir); nkeynes@5: tmp = IMMROT(ir); nkeynes@5: if( tmp == 0 ) { nkeynes@5: armr.shift_c = armr.c; nkeynes@5: } else { nkeynes@5: operand = ROTATE_RIGHT_LONG(operand, tmp); nkeynes@5: armr.shift_c = operand>>31; nkeynes@5: } nkeynes@5: } nkeynes@5: return operand; nkeynes@5: } nkeynes@5: nkeynes@5: /** nkeynes@5: * Another variant of the shifter code for index-based memory addressing. nkeynes@5: * Distinguished by the fact that it doesn't support register shifts, and nkeynes@5: * ignores the I flag (WTF do the load/store instructions use the I flag to nkeynes@5: * mean the _exact opposite_ of what it means for the data processing nkeynes@5: * instructions ???) nkeynes@5: */ nkeynes@5: static uint32_t arm_get_address_index( uint32_t ir ) nkeynes@5: { nkeynes@5: uint32_t operand = RM(ir); nkeynes@7: uint32_t tmp; nkeynes@7: nkeynes@5: switch(SHIFT(ir)) { nkeynes@5: case 0: /* (Rm << imm) */ nkeynes@5: operand = operand << SHIFTIMM(ir); nkeynes@5: break; nkeynes@5: case 2: /* (Rm >> imm) */ nkeynes@5: operand = operand >> SHIFTIMM(ir); nkeynes@5: break; nkeynes@5: case 4: /* (Rm >>> imm) */ nkeynes@5: tmp = SHIFTIMM(ir); nkeynes@5: if( tmp == 0 ) operand = ((int32_t)operand) >> 31; nkeynes@5: else operand = ((int32_t)operand) >> tmp; nkeynes@5: break; nkeynes@5: case 6: nkeynes@5: tmp = SHIFTIMM(ir); nkeynes@5: if( tmp == 0 ) /* RRX aka rotate with carry */ nkeynes@7: operand = (operand >> 1) | (armr.c<<31); nkeynes@5: else nkeynes@5: operand = ROTATE_RIGHT_LONG(operand,tmp); nkeynes@5: break; nkeynes@5: default: UNIMP(ir); nkeynes@5: } nkeynes@5: return operand; nkeynes@5: } nkeynes@5: nkeynes@5: static uint32_t arm_get_address_operand( uint32_t ir ) nkeynes@5: { nkeynes@5: uint32_t addr; nkeynes@5: nkeynes@5: /* I P U . W */ nkeynes@5: switch( (ir>>21)&0x1D ) { nkeynes@5: case 0: /* Rn -= imm offset (post-indexed) [5.2.8 A5-28] */ nkeynes@5: case 1: nkeynes@5: addr = RN(ir); nkeynes@7: LRN(ir) = addr - IMM12(ir); nkeynes@5: break; nkeynes@5: case 4: /* Rn += imm offsett (post-indexed) [5.2.8 A5-28] */ nkeynes@5: case 5: nkeynes@5: addr = RN(ir); nkeynes@7: LRN(ir) = addr + IMM12(ir); nkeynes@5: break; nkeynes@5: case 8: /* Rn - imm offset [5.2.2 A5-20] */ nkeynes@5: addr = RN(ir) - IMM12(ir); nkeynes@5: break; nkeynes@5: case 9: /* Rn -= imm offset (pre-indexed) [5.2.5 A5-24] */ nkeynes@5: addr = RN(ir) - IMM12(ir); nkeynes@7: LRN(ir) = addr; nkeynes@5: break; nkeynes@5: case 12: /* Rn + imm offset [5.2.2 A5-20] */ nkeynes@5: addr = RN(ir) + IMM12(ir); nkeynes@5: break; nkeynes@5: case 13: /* Rn += imm offset [5.2.5 A5-24 ] */ nkeynes@5: addr = RN(ir) + IMM12(ir); nkeynes@7: LRN(ir) = addr; nkeynes@5: break; nkeynes@5: case 16: /* Rn -= Rm (post-indexed) [5.2.10 A5-32 ] */ nkeynes@5: case 17: nkeynes@5: addr = RN(ir); nkeynes@7: LRN(ir) = addr - arm_get_address_index(ir); nkeynes@5: break; nkeynes@5: case 20: /* Rn += Rm (post-indexed) [5.2.10 A5-32 ] */ nkeynes@5: case 21: nkeynes@5: addr = RN(ir); nkeynes@7: LRN(ir) = addr - arm_get_address_index(ir); nkeynes@5: break; nkeynes@5: case 24: /* Rn - Rm [5.2.4 A5-23] */ nkeynes@5: addr = RN(ir) - arm_get_address_index(ir); nkeynes@5: break; nkeynes@5: case 25: /* RN -= Rm (pre-indexed) [5.2.7 A5-26] */ nkeynes@5: addr = RN(ir) - arm_get_address_index(ir); nkeynes@7: LRN(ir) = addr; nkeynes@5: break; nkeynes@5: case 28: /* Rn + Rm [5.2.4 A5-23] */ nkeynes@5: addr = RN(ir) + arm_get_address_index(ir); nkeynes@5: break; nkeynes@5: case 29: /* RN += Rm (pre-indexed) [5.2.7 A5-26] */ nkeynes@5: addr = RN(ir) + arm_get_address_index(ir); nkeynes@7: LRN(ir) = addr; nkeynes@5: break; nkeynes@5: default: nkeynes@5: UNIMP(ir); /* Unreachable */ nkeynes@5: } nkeynes@5: return addr; nkeynes@5: } nkeynes@5: nkeynes@30: gboolean arm_execute_instruction( void ) nkeynes@2: { nkeynes@5: uint32_t pc = PC; nkeynes@7: uint32_t ir = MEM_READ_LONG(pc); nkeynes@7: uint32_t operand, operand2, tmp, cond; nkeynes@2: nkeynes@5: pc += 4; nkeynes@5: PC = pc; nkeynes@2: nkeynes@5: switch( COND(ir) ) { nkeynes@5: case 0: /* EQ */ nkeynes@5: cond = armr.z; nkeynes@5: break; nkeynes@5: case 1: /* NE */ nkeynes@5: cond = !armr.z; nkeynes@5: break; nkeynes@5: case 2: /* CS/HS */ nkeynes@5: cond = armr.c; nkeynes@5: break; nkeynes@5: case 3: /* CC/LO */ nkeynes@5: cond = !armr.c; nkeynes@5: break; nkeynes@5: case 4: /* MI */ nkeynes@5: cond = armr.n; nkeynes@5: break; nkeynes@5: case 5: /* PL */ nkeynes@5: cond = !armr.n; nkeynes@5: break; nkeynes@5: case 6: /* VS */ nkeynes@5: cond = armr.v; nkeynes@5: break; nkeynes@5: case 7: /* VC */ nkeynes@5: cond = !armr.v; nkeynes@5: break; nkeynes@5: case 8: /* HI */ nkeynes@5: cond = armr.c && !armr.z; nkeynes@5: break; nkeynes@5: case 9: /* LS */ nkeynes@5: cond = (!armr.c) || armr.z; nkeynes@5: break; nkeynes@5: case 10: /* GE */ nkeynes@5: cond = (armr.n == armr.v); nkeynes@5: break; nkeynes@5: case 11: /* LT */ nkeynes@5: cond = (armr.n != armr.v); nkeynes@5: break; nkeynes@5: case 12: /* GT */ nkeynes@5: cond = (!armr.z) && (armr.n == armr.v); nkeynes@5: break; nkeynes@5: case 13: /* LE */ nkeynes@5: cond = armr.z || (armr.n != armr.v); nkeynes@5: break; nkeynes@5: case 14: /* AL */ nkeynes@5: cond = 1; nkeynes@5: break; nkeynes@5: case 15: /* (NV) */ nkeynes@5: cond = 0; nkeynes@5: UNDEF(ir); nkeynes@5: } nkeynes@5: nkeynes@5: switch( GRP(ir) ) { nkeynes@5: case 0: nkeynes@5: if( (ir & 0x0D900000) == 0x01000000 ) { nkeynes@5: /* Instructions that aren't actual data processing */ nkeynes@5: switch( ir & 0x0FF000F0 ) { nkeynes@5: case 0x01200010: /* BX */ nkeynes@5: break; nkeynes@5: case 0x01000000: /* MRS Rd, CPSR */ nkeynes@5: break; nkeynes@5: case 0x01400000: /* MRS Rd, SPSR */ nkeynes@5: break; nkeynes@5: case 0x01200000: /* MSR CPSR, Rd */ nkeynes@5: break; nkeynes@5: case 0x01600000: /* MSR SPSR, Rd */ nkeynes@5: break; nkeynes@5: case 0x03200000: /* MSR CPSR, imm */ nkeynes@5: break; nkeynes@5: case 0x03600000: /* MSR SPSR, imm */ nkeynes@5: break; nkeynes@5: default: nkeynes@7: UNIMP(ir); nkeynes@5: } nkeynes@5: } else if( (ir & 0x0E000090) == 0x00000090 ) { nkeynes@5: /* Neither are these */ nkeynes@5: switch( (ir>>5)&0x03 ) { nkeynes@5: case 0: nkeynes@5: /* Arithmetic extension area */ nkeynes@5: switch(OPCODE(ir)) { nkeynes@5: case 0: /* MUL */ nkeynes@5: break; nkeynes@5: case 1: /* MULS */ nkeynes@5: break; nkeynes@5: case 2: /* MLA */ nkeynes@5: break; nkeynes@5: case 3: /* MLAS */ nkeynes@5: break; nkeynes@5: case 8: /* UMULL */ nkeynes@5: break; nkeynes@5: case 9: /* UMULLS */ nkeynes@5: break; nkeynes@5: case 10: /* UMLAL */ nkeynes@5: break; nkeynes@5: case 11: /* UMLALS */ nkeynes@5: break; nkeynes@5: case 12: /* SMULL */ nkeynes@5: break; nkeynes@5: case 13: /* SMULLS */ nkeynes@5: break; nkeynes@5: case 14: /* SMLAL */ nkeynes@5: break; nkeynes@5: case 15: /* SMLALS */ nkeynes@5: break; nkeynes@5: case 16: /* SWP */ nkeynes@5: break; nkeynes@5: case 20: /* SWPB */ nkeynes@5: break; nkeynes@5: default: nkeynes@5: UNIMP(ir); nkeynes@5: } nkeynes@5: break; nkeynes@5: case 1: nkeynes@5: if( LFLAG(ir) ) { nkeynes@5: /* LDRH */ nkeynes@5: } else { nkeynes@5: /* STRH */ nkeynes@5: } nkeynes@5: break; nkeynes@5: case 2: nkeynes@5: if( LFLAG(ir) ) { nkeynes@5: /* LDRSB */ nkeynes@5: } else { nkeynes@5: UNIMP(ir); nkeynes@5: } nkeynes@5: break; nkeynes@5: case 3: nkeynes@5: if( LFLAG(ir) ) { nkeynes@5: /* LDRSH */ nkeynes@5: } else { nkeynes@5: UNIMP(ir); nkeynes@5: } nkeynes@5: break; nkeynes@5: } nkeynes@5: } else { nkeynes@5: /* Data processing */ nkeynes@5: nkeynes@5: switch(OPCODE(ir)) { nkeynes@5: case 0: /* AND Rd, Rn, operand */ nkeynes@7: LRD(ir) = RN(ir) & arm_get_shift_operand(ir); nkeynes@5: break; nkeynes@5: case 1: /* ANDS Rd, Rn, operand */ nkeynes@5: operand = arm_get_shift_operand_s(ir) & RN(ir); nkeynes@7: LRD(ir) = operand; nkeynes@5: if( RDn(ir) == 15 ) { nkeynes@5: arm_restore_cpsr(); nkeynes@5: } else { nkeynes@5: armr.n = operand>>31; nkeynes@5: armr.z = (operand == 0); nkeynes@5: armr.c = armr.shift_c; nkeynes@5: } nkeynes@5: break; nkeynes@5: case 2: /* EOR Rd, Rn, operand */ nkeynes@7: LRD(ir) = RN(ir) ^ arm_get_shift_operand(ir); nkeynes@5: break; nkeynes@5: case 3: /* EORS Rd, Rn, operand */ nkeynes@5: operand = arm_get_shift_operand_s(ir) ^ RN(ir); nkeynes@7: LRD(ir) = operand; nkeynes@5: if( RDn(ir) == 15 ) { nkeynes@5: arm_restore_cpsr(); nkeynes@5: } else { nkeynes@5: armr.n = operand>>31; nkeynes@5: armr.z = (operand == 0); nkeynes@5: armr.c = armr.shift_c; nkeynes@5: } nkeynes@5: break; nkeynes@5: case 4: /* SUB Rd, Rn, operand */ nkeynes@7: LRD(ir) = RN(ir) - arm_get_shift_operand(ir); nkeynes@5: break; nkeynes@5: case 5: /* SUBS Rd, Rn, operand */ nkeynes@5: operand = RN(ir); nkeynes@7: operand2 = arm_get_shift_operand(ir); nkeynes@5: tmp = operand - operand2; nkeynes@7: LRD(ir) = tmp; nkeynes@5: if( RDn(ir) == 15 ) { nkeynes@5: arm_restore_cpsr(); nkeynes@5: } else { nkeynes@5: armr.n = tmp>>31; nkeynes@5: armr.z = (tmp == 0); nkeynes@5: armr.c = IS_NOTBORROW(tmp,operand,operand2); nkeynes@5: armr.v = IS_SUBOVERFLOW(tmp,operand,operand2); nkeynes@5: } nkeynes@5: break; nkeynes@5: case 6: /* RSB Rd, operand, Rn */ nkeynes@7: LRD(ir) = arm_get_shift_operand(ir) - RN(ir); nkeynes@5: break; nkeynes@5: case 7: /* RSBS Rd, operand, Rn */ nkeynes@5: operand = arm_get_shift_operand(ir); nkeynes@5: operand2 = RN(ir); nkeynes@5: tmp = operand - operand2; nkeynes@7: LRD(ir) = tmp; nkeynes@5: if( RDn(ir) == 15 ) { nkeynes@5: arm_restore_cpsr(); nkeynes@5: } else { nkeynes@5: armr.n = tmp>>31; nkeynes@5: armr.z = (tmp == 0); nkeynes@5: armr.c = IS_NOTBORROW(tmp,operand,operand2); nkeynes@5: armr.v = IS_SUBOVERFLOW(tmp,operand,operand2); nkeynes@5: } nkeynes@5: break; nkeynes@5: case 8: /* ADD Rd, Rn, operand */ nkeynes@7: LRD(ir) = RN(ir) + arm_get_shift_operand(ir); nkeynes@5: break; nkeynes@5: case 9: /* ADDS Rd, Rn, operand */ nkeynes@5: operand = arm_get_shift_operand(ir); nkeynes@5: operand2 = RN(ir); nkeynes@7: tmp = operand + operand2; nkeynes@7: LRD(ir) = tmp; nkeynes@5: if( RDn(ir) == 15 ) { nkeynes@5: arm_restore_cpsr(); nkeynes@5: } else { nkeynes@5: armr.n = tmp>>31; nkeynes@5: armr.z = (tmp == 0); nkeynes@5: armr.c = IS_CARRY(tmp,operand,operand2); nkeynes@5: armr.v = IS_ADDOVERFLOW(tmp,operand,operand2); nkeynes@5: } nkeynes@5: break; nkeynes@5: case 10: /* ADC */ nkeynes@5: case 11: /* ADCS */ nkeynes@5: case 12: /* SBC */ nkeynes@5: case 13: /* SBCS */ nkeynes@5: case 14: /* RSC */ nkeynes@5: case 15: /* RSCS */ nkeynes@5: break; nkeynes@5: case 17: /* TST Rn, operand */ nkeynes@5: operand = arm_get_shift_operand_s(ir) & RN(ir); nkeynes@5: armr.n = operand>>31; nkeynes@5: armr.z = (operand == 0); nkeynes@5: armr.c = armr.shift_c; nkeynes@5: break; nkeynes@5: case 19: /* TEQ Rn, operand */ nkeynes@5: operand = arm_get_shift_operand_s(ir) ^ RN(ir); nkeynes@5: armr.n = operand>>31; nkeynes@5: armr.z = (operand == 0); nkeynes@5: armr.c = armr.shift_c; nkeynes@5: break; nkeynes@5: case 21: /* CMP Rn, operand */ nkeynes@5: operand = RN(ir); nkeynes@7: operand2 = arm_get_shift_operand(ir); nkeynes@5: tmp = operand - operand2; nkeynes@5: armr.n = tmp>>31; nkeynes@5: armr.z = (tmp == 0); nkeynes@5: armr.c = IS_NOTBORROW(tmp,operand,operand2); nkeynes@5: armr.v = IS_SUBOVERFLOW(tmp,operand,operand2); nkeynes@5: break; nkeynes@5: case 23: /* CMN Rn, operand */ nkeynes@5: operand = RN(ir); nkeynes@7: operand2 = arm_get_shift_operand(ir); nkeynes@5: tmp = operand + operand2; nkeynes@5: armr.n = tmp>>31; nkeynes@5: armr.z = (tmp == 0); nkeynes@5: armr.c = IS_CARRY(tmp,operand,operand2); nkeynes@5: armr.v = IS_ADDOVERFLOW(tmp,operand,operand2); nkeynes@5: break; nkeynes@5: case 24: /* ORR Rd, Rn, operand */ nkeynes@7: LRD(ir) = RN(ir) | arm_get_shift_operand(ir); nkeynes@5: break; nkeynes@5: case 25: /* ORRS Rd, Rn, operand */ nkeynes@5: operand = arm_get_shift_operand_s(ir) | RN(ir); nkeynes@7: LRD(ir) = operand; nkeynes@5: if( RDn(ir) == 15 ) { nkeynes@5: arm_restore_cpsr(); nkeynes@5: } else { nkeynes@5: armr.n = operand>>31; nkeynes@5: armr.z = (operand == 0); nkeynes@5: armr.c = armr.shift_c; nkeynes@5: } nkeynes@5: break; nkeynes@5: case 26: /* MOV Rd, operand */ nkeynes@7: LRD(ir) = arm_get_shift_operand(ir); nkeynes@5: break; nkeynes@5: case 27: /* MOVS Rd, operand */ nkeynes@5: operand = arm_get_shift_operand_s(ir); nkeynes@7: LRD(ir) = operand; nkeynes@5: if( RDn(ir) == 15 ) { nkeynes@5: arm_restore_cpsr(); nkeynes@5: } else { nkeynes@5: armr.n = operand>>31; nkeynes@5: armr.z = (operand == 0); nkeynes@5: armr.c = armr.shift_c; nkeynes@5: } nkeynes@5: break; nkeynes@5: case 28: /* BIC Rd, Rn, operand */ nkeynes@7: LRD(ir) = RN(ir) & (~arm_get_shift_operand(ir)); nkeynes@5: break; nkeynes@5: case 29: /* BICS Rd, Rn, operand */ nkeynes@5: operand = RN(ir) & (~arm_get_shift_operand_s(ir)); nkeynes@7: LRD(ir) = operand; nkeynes@5: if( RDn(ir) == 15 ) { nkeynes@5: arm_restore_cpsr(); nkeynes@5: } else { nkeynes@5: armr.n = operand>>31; nkeynes@5: armr.z = (operand == 0); nkeynes@5: armr.c = armr.shift_c; nkeynes@5: } nkeynes@5: break; nkeynes@5: case 30: /* MVN Rd, operand */ nkeynes@7: LRD(ir) = ~arm_get_shift_operand(ir); nkeynes@5: break; nkeynes@5: case 31: /* MVNS Rd, operand */ nkeynes@5: operand = ~arm_get_shift_operand_s(ir); nkeynes@7: LRD(ir) = operand; nkeynes@5: if( RDn(ir) == 15 ) { nkeynes@5: arm_restore_cpsr(); nkeynes@5: } else { nkeynes@5: armr.n = operand>>31; nkeynes@5: armr.z = (operand == 0); nkeynes@5: armr.c = armr.shift_c; nkeynes@5: } nkeynes@5: break; nkeynes@5: default: nkeynes@5: UNIMP(ir); nkeynes@5: } nkeynes@5: } nkeynes@5: break; nkeynes@5: case 1: /* Load/store */ nkeynes@5: break; nkeynes@5: case 2: /* Load/store multiple, branch*/ nkeynes@5: break; nkeynes@5: case 3: /* Copro */ nkeynes@5: break; nkeynes@5: } nkeynes@30: return TRUE; nkeynes@2: }