nkeynes@30: /** nkeynes@561: * $Id$ nkeynes@30: * nkeynes@30: * MMIO region and supporting function declarations. Private to the sh4 nkeynes@30: * module. nkeynes@30: * nkeynes@30: * Copyright (c) 2005 Nathan Keynes. nkeynes@30: * nkeynes@30: * This program is free software; you can redistribute it and/or modify nkeynes@30: * it under the terms of the GNU General Public License as published by nkeynes@30: * the Free Software Foundation; either version 2 of the License, or nkeynes@30: * (at your option) any later version. nkeynes@30: * nkeynes@30: * This program is distributed in the hope that it will be useful, nkeynes@30: * but WITHOUT ANY WARRANTY; without even the implied warranty of nkeynes@30: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the nkeynes@30: * GNU General Public License for more details. nkeynes@30: */ nkeynes@30: nkeynes@550: #include "lxdream.h" nkeynes@1: #include "mmio.h" nkeynes@1: nkeynes@1: #if (defined(MMIO_IMPL) && !defined(SH4MMIO_IMPL)) || \ nkeynes@1: (!defined(MMIO_IMPL) && !defined(SH4MMIO_IFACE)) nkeynes@1: nkeynes@736: #ifdef __cplusplus nkeynes@736: extern "C" { nkeynes@736: #endif nkeynes@736: nkeynes@1: #ifdef MMIO_IMPL nkeynes@1: #define SH4MMIO_IMPL nkeynes@1: #else nkeynes@1: #define SH4MMIO_IFACE nkeynes@1: #endif nkeynes@1: /* SH7750 onchip mmio devices */ nkeynes@1: nkeynes@1: MMIO_REGION_BEGIN( 0xFF000000, MMU, "MMU Registers" ) nkeynes@1: LONG_PORT( 0x000, PTEH, PORT_MRW, UNDEFINED, "Page table entry high" ) nkeynes@1: LONG_PORT( 0x004, PTEL, PORT_MRW, UNDEFINED, "Page table entry low" ) nkeynes@1: LONG_PORT( 0x008, TTB, PORT_MRW, UNDEFINED, "Translation table base" ) nkeynes@1: LONG_PORT( 0x00C, TEA, PORT_MRW, UNDEFINED, "TLB exception address" ) nkeynes@1: LONG_PORT( 0x010, MMUCR,PORT_MRW, 0, "MMU control register" ) nkeynes@550: BYTE_PORT( 0x014, BASRA, PORT_MRW, UNDEFINED, "Break ASID A" ) /* UBC */ nkeynes@550: BYTE_PORT( 0x018, BASRB, PORT_MRW, UNDEFINED, "Break ASID B" ) /* UBC */ nkeynes@1: LONG_PORT( 0x01C, CCR, PORT_MRW, 0, "Cache control register" ) nkeynes@1: LONG_PORT( 0x020, TRA, PORT_MRW, UNDEFINED, "TRAPA exception register" ) nkeynes@1: LONG_PORT( 0x024, EXPEVT,PORT_MRW, 0, "Exception event register" ) nkeynes@1: LONG_PORT( 0x028, INTEVT,PORT_MRW, UNDEFINED, "Interrupt event register" ) nkeynes@818: LONG_PORT( 0x030, SH4VER, PORT_MRW, 0x040205C1, "SH4 version register (PVR)" ) /* Renamed to avoid naming conflict */ nkeynes@1: LONG_PORT( 0x034, PTEA, PORT_MRW, UNDEFINED, "Page table entry assistance" ) nkeynes@1: LONG_PORT( 0x038, QACR0,PORT_MRW, UNDEFINED, "Queue address control 0" ) nkeynes@1: LONG_PORT( 0x03C, QACR1,PORT_MRW, UNDEFINED, "Queue address control 1" ) nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@1: /* User Break Controller (Page 717 [757] of sh7750h manual) */ nkeynes@1: MMIO_REGION_BEGIN( 0xFF200000, UBC, "User Break Controller" ) nkeynes@1: LONG_PORT( 0x000, BARA, PORT_MRW, UNDEFINED, "Break address A" ) nkeynes@1: BYTE_PORT( 0x004, BAMRA, PORT_MRW, UNDEFINED, "Break address mask A" ) nkeynes@1: WORD_PORT( 0x008, BBRA, PORT_MRW, 0, "Break bus cycle A" ) nkeynes@1: LONG_PORT( 0x00C, BARB, PORT_MRW, UNDEFINED, "Break address B" ) nkeynes@1: BYTE_PORT( 0x010, BAMRB, PORT_MRW, UNDEFINED, "Break address mask B" ) nkeynes@1: WORD_PORT( 0x014, BBRB, PORT_MRW, 0, "Break bus cycle B" ) nkeynes@1: LONG_PORT( 0x018, BDRB, PORT_MRW, UNDEFINED, "Break data B" ) nkeynes@1: LONG_PORT( 0x01C, BDMRB, PORT_MRW, UNDEFINED, "Break data mask B" ) nkeynes@1: WORD_PORT( 0x020, BRCR, PORT_MRW, 0, "Break control" ) nkeynes@1: MMIO_REGION_END nkeynes@1: /* Bus State Controller (Page 293 [333] of sh7750h manual) nkeynes@1: * I/O Ports */ nkeynes@1: MMIO_REGION_BEGIN( 0xFF800000, BSC, "Bus State Controller" ) nkeynes@1: LONG_PORT( 0x000, BCR1, PORT_MRW, 0, "Bus control 1" ) nkeynes@1: WORD_PORT( 0x004, BCR2, PORT_MRW, 0x3FFC, "Bus control 2" ) nkeynes@1: LONG_PORT( 0x008, WCR1, PORT_MRW, 0x77777777, "Wait state control 1" ) nkeynes@1: LONG_PORT( 0x00C, WCR2, PORT_MRW, 0xFFFEEFFF, "Wait state control 2" ) nkeynes@1: LONG_PORT( 0x010, WCR3, PORT_MRW, 0x07777777, "Wait state control 3" ) nkeynes@1: LONG_PORT( 0x014, MCR, PORT_MRW, 0, "Memory control register" ) nkeynes@1: WORD_PORT( 0x018, PCR, PORT_MRW, 0, "PCMCIA control register" ) nkeynes@1: WORD_PORT( 0x01C, RTCSR, PORT_MRW, 0, "Refresh timer control/status" ) nkeynes@1: WORD_PORT( 0x020, RTCNT, PORT_MRW, 0, "Refresh timer counter" ) nkeynes@1: WORD_PORT( 0x024, RTCOR, PORT_MRW, 0, "Refresh timer constant" ) nkeynes@1: WORD_PORT( 0x028, RFCR, PORT_MRW, 0, "Refresh count" ) nkeynes@1: LONG_PORT( 0x02C, PCTRA, PORT_MRW, 0, "Port control register A" ) nkeynes@1: WORD_PORT( 0x030, PDTRA, PORT_RW, UNDEFINED, "Port data register A" ) nkeynes@1: LONG_PORT( 0x040, PCTRB, PORT_MRW, 0, "Port control register B" ) nkeynes@1: WORD_PORT( 0x044, PDTRB, PORT_RW, UNDEFINED, "Port data register B" ) nkeynes@1: WORD_PORT( 0x048, GPIOIC, PORT_MRW, 0, "GPIO interrupt control register" ) nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@1: /* DMA Controller (Page 457 [497] of sh7750h manual) */ nkeynes@1: MMIO_REGION_BEGIN( 0xFFA00000, DMAC, "DMA Controller" ) nkeynes@1: LONG_PORT( 0x000, SAR0, PORT_MRW, UNDEFINED, "DMA source address 0" ) nkeynes@1: LONG_PORT( 0x004, DAR0, PORT_MRW, UNDEFINED, "DMA destination address 0" ) nkeynes@1: LONG_PORT( 0x008, DMATCR0, PORT_MRW, UNDEFINED, "DMA transfer count 0" ) nkeynes@1: LONG_PORT( 0x00C, CHCR0, PORT_MRW, 0, "DMA channel control 0" ) nkeynes@1: LONG_PORT( 0x010, SAR1, PORT_MRW, UNDEFINED, "DMA source address 1" ) nkeynes@1: LONG_PORT( 0x014, DAR1, PORT_MRW, UNDEFINED, "DMA destination address 1" ) nkeynes@1: LONG_PORT( 0x018, DMATCR1, PORT_MRW, UNDEFINED, "DMA transfer count 1" ) nkeynes@1: LONG_PORT( 0x01C, CHCR1, PORT_MRW, 0, "DMA channel control 1" ) nkeynes@1: LONG_PORT( 0x020, SAR2, PORT_MRW, UNDEFINED, "DMA source address 2" ) nkeynes@1: LONG_PORT( 0x024, DAR2, PORT_MRW, UNDEFINED, "DMA destination address 2" ) nkeynes@1: LONG_PORT( 0x028, DMATCR2, PORT_MRW, UNDEFINED, "DMA transfer count 2" ) nkeynes@1: LONG_PORT( 0x02C, CHCR2, PORT_MRW, 0, "DMA channel control 2" ) nkeynes@1: LONG_PORT( 0x030, SAR3, PORT_MRW, UNDEFINED, "DMA source address 3" ) nkeynes@1: LONG_PORT( 0x034, DAR3, PORT_MRW, UNDEFINED, "DMA destination address 3" ) nkeynes@1: LONG_PORT( 0x038, DMATCR3, PORT_MRW, UNDEFINED, "DMA transfer count 3" ) nkeynes@1: LONG_PORT( 0x03C, CHCR3, PORT_MRW, 0, "DMA channel control 3" ) nkeynes@1: LONG_PORT( 0x040, DMAOR, PORT_MRW, 0, "DMA operation register" ) nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@1: /* Clock Pulse Generator (page 233 [273] of sh7750h manual) */ nkeynes@1: MMIO_REGION_BEGIN( 0xFFC00000, CPG, "Clock Pulse Generator" ) nkeynes@1: WORD_PORT( 0x000, FRQCR, PORT_MRW, UNDEFINED, "Frequency control" ) nkeynes@1: BYTE_PORT( 0x004, STBCR, PORT_MRW, 0, "Standby control" ) nkeynes@1: BYTE_PORT( 0x008, WTCNT, PORT_MRW, 0, "Watchdog timer counter" ) nkeynes@1: BYTE_PORT( 0x00C, WTCSR, PORT_MRW, 0, "Watchdog timer control/status" ) nkeynes@1: BYTE_PORT( 0x010, STBCR2, PORT_MRW, 0, "Standby control 2" ) nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@1: /* Real time clock (Page 253 [293] of sh7750h manual) */ nkeynes@1: MMIO_REGION_BEGIN( 0xFFC80000, RTC, "Realtime Clock" ) nkeynes@1: BYTE_PORT( 0x000, R64CNT, PORT_R, UNDEFINED, "64 Hz counter" ) nkeynes@1: BYTE_PORT( 0x004, RSECCNT, PORT_MRW, UNDEFINED, "Second counter" ) nkeynes@1: /* ... */ nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@1: /* Interrupt controller (Page 699 [739] of sh7750h manual) */ nkeynes@1: MMIO_REGION_BEGIN( 0xFFD00000, INTC, "Interrupt Controller" ) nkeynes@1: WORD_PORT( 0x000, ICR, PORT_MRW, 0x0000, "Interrupt control register" ) nkeynes@1: WORD_PORT( 0x004, IPRA, PORT_MRW, 0x0000, "Interrupt priority register A" ) nkeynes@1: WORD_PORT( 0x008, IPRB, PORT_MRW, 0x0000, "Interrupt priority register B" ) nkeynes@1: WORD_PORT( 0x00C, IPRC, PORT_MRW, 0x0000, "Interrupt priority register C" ) nkeynes@1: WORD_PORT( 0x010, IPRD, PORT_MRW, 0xDA74, "Interrupt priority register D" ) nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@1: /* Timer unit (Page 277 [317] of sh7750h manual) */ nkeynes@1: MMIO_REGION_BEGIN( 0xFFD80000, TMU, "Timer Unit" ) nkeynes@1: BYTE_PORT( 0x000, TOCR, PORT_MRW, 0x00, "Timer output control register" ) nkeynes@1: BYTE_PORT( 0x004, TSTR, PORT_MRW, 0x00, "Timer start register" ) nkeynes@1: LONG_PORT( 0x008, TCOR0, PORT_MRW, 0xFFFFFFFF, "Timer constant 0" ) nkeynes@1: LONG_PORT( 0x00C, TCNT0, PORT_MRW, 0xFFFFFFFF, "Timer counter 0" ) nkeynes@1: WORD_PORT( 0x010, TCR0, PORT_MRW, 0x0000, "Timer control 0" ) nkeynes@1: LONG_PORT( 0x014, TCOR1, PORT_MRW, 0xFFFFFFFF, "Timer constant 1" ) nkeynes@1: LONG_PORT( 0x018, TCNT1, PORT_MRW, 0xFFFFFFFF, "Timer counter 1" ) nkeynes@1: WORD_PORT( 0x01C, TCR1, PORT_MRW, 0x0000, "Timer control 1" ) nkeynes@1: LONG_PORT( 0x020, TCOR2, PORT_MRW, 0xFFFFFFFF, "Timer constant 2" ) nkeynes@1: LONG_PORT( 0x024, TCNT2, PORT_MRW, 0xFFFFFFFF, "Timer counter 2" ) nkeynes@1: WORD_PORT( 0x028, TCR2, PORT_MRW, 0x0000, "Timer control 2" ) nkeynes@1: LONG_PORT( 0x02C, TCPR2, PORT_R, UNDEFINED, "Input capture register" ) nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@1: /* Serial channel (page 541 [581] of sh7750h manual) */ nkeynes@1: MMIO_REGION_BEGIN( 0xFFE00000, SCI, "Serial Communication Interface" ) nkeynes@1: BYTE_PORT( 0x000, SCSMR1, PORT_MRW, 0x00, "Serial mode register" ) nkeynes@1: BYTE_PORT( 0x004, SCBRR1, PORT_MRW, 0xFF, "Bit rate register" ) nkeynes@1: BYTE_PORT( 0x008, SCSCR1, PORT_MRW, 0x00, "Serial control register" ) nkeynes@1: BYTE_PORT( 0x00C, SCTDR1, PORT_MRW, 0xFF, "Transmit data register" ) nkeynes@1: BYTE_PORT( 0x010, SCSSR1, PORT_MRW, 0x84, "Serial status register" ) nkeynes@1: BYTE_PORT( 0x014, SCRDR1, PORT_R, 0x00, "Receive data register" ) nkeynes@1: BYTE_PORT( 0x01C, SCSPTR1, PORT_MRW, 0x00, "Serial port register" ) nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@1: MMIO_REGION_BEGIN( 0xFFE80000, SCIF, "Serial Controller (FIFO) Registers" ) nkeynes@1: WORD_PORT( 0x000, SCSMR2, PORT_MRW, 0x0000, "Serial mode register (FIFO)" ) nkeynes@19: BYTE_PORT( 0x004, SCBRR2, PORT_MRW, 0xFF, "Bit rate register (FIFO)" ) nkeynes@19: WORD_PORT( 0x008, SCSCR2, PORT_MRW, 0x0000, "Serial control register" ) nkeynes@19: BYTE_PORT( 0x00C, SCFTDR2, PORT_W, UNDEFINED, "Transmit FIFO data register" ) nkeynes@19: WORD_PORT( 0x010, SCFSR2, PORT_MRW, 0x0060, "Serial status register (FIFO)") nkeynes@19: BYTE_PORT( 0x014, SCFRDR2, PORT_R, UNDEFINED, "Receive FIFO data register" ) nkeynes@19: WORD_PORT( 0x018, SCFCR2, PORT_MRW, 0x0000, "FIFO control register" ) nkeynes@19: WORD_PORT( 0x01C, SCFDR2, PORT_MR, 0x0000, "FIFO data count register" ) nkeynes@19: WORD_PORT( 0x020, SCSPTR2, PORT_MRW, 0x0000, "Serial port register (FIFO)" ) nkeynes@19: WORD_PORT( 0x024, SCLSR2, PORT_MRW, 0x0000, "Line status register (FIFO)" ) nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@1: MMIO_REGION_LIST_BEGIN( sh4mmio ) nkeynes@1: MMIO_REGION( MMU ) nkeynes@1: MMIO_REGION( UBC ) nkeynes@1: MMIO_REGION( BSC ) nkeynes@1: MMIO_REGION( DMAC ) nkeynes@1: MMIO_REGION( CPG ) nkeynes@1: MMIO_REGION( RTC ) nkeynes@1: MMIO_REGION( INTC ) nkeynes@1: MMIO_REGION( TMU ) nkeynes@1: MMIO_REGION( SCI ) nkeynes@1: MMIO_REGION( SCIF ) nkeynes@1: MMIO_REGION_LIST_END nkeynes@1: nkeynes@10: /* mmucr register bits */ nkeynes@10: #define MMUCR_AT 0x00000001 /* Address Translation enabled */ nkeynes@10: #define MMUCR_TI 0x00000004 /* TLB invalidate (always read as 0) */ nkeynes@10: #define MMUCR_SV 0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */ nkeynes@10: #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */ nkeynes@10: #define MMUCR_URC 0x0000FC00 /* UTLB access counter */ nkeynes@10: #define MMUCR_URB 0x00FC0000 /* UTLB entry boundary */ nkeynes@10: #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */ nkeynes@10: #define MMUCR_MASK 0xFCFCFF05 nkeynes@10: #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */ nkeynes@10: nkeynes@10: #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT) nkeynes@10: nkeynes@10: /* ccr register bits */ nkeynes@10: #define CCR_IIX 0x00008000 /* IC index enable */ nkeynes@10: #define CCR_ICI 0x00000800 /* IC invalidation (always read as 0) */ nkeynes@10: #define CCR_ICE 0x00000100 /* IC enable */ nkeynes@10: #define CCR_OIX 0x00000080 /* OC index enable */ nkeynes@10: #define CCR_ORA 0x00000020 /* OC RAM enable */ nkeynes@10: #define CCR_OCI 0x00000008 /* OC invalidation (always read as 0) */ nkeynes@10: #define CCR_CB 0x00000004 /* Copy-back (P1 area cache write mode) */ nkeynes@10: #define CCR_WT 0x00000002 /* Write-through (P0,U0,P3 write mode) */ nkeynes@10: #define CCR_OCE 0x00000001 /* OC enable */ nkeynes@10: #define CCR_MASK 0x000089AF nkeynes@10: #define CCR_RMASK 0x000081A7 /* Read mask */ nkeynes@10: nkeynes@817: #define MEM_OC_INDEX0 (CCR_ORA|CCR_OCE) nkeynes@817: #define MEM_OC_INDEX1 (CCR_ORA|CCR_OIX|CCR_OCE) nkeynes@10: nkeynes@550: /* MMU functions */ nkeynes@10: void mmu_init(void); nkeynes@10: void mmu_set_cache_mode( int ); nkeynes@550: void mmu_ldtlb(void); nkeynes@10: nkeynes@550: int32_t mmu_icache_addr_read( sh4addr_t addr ); nkeynes@550: int32_t mmu_icache_data_read( sh4addr_t addr ); nkeynes@550: int32_t mmu_itlb_addr_read( sh4addr_t addr ); nkeynes@550: int32_t mmu_itlb_data_read( sh4addr_t addr ); nkeynes@550: int32_t mmu_ocache_addr_read( sh4addr_t addr ); nkeynes@550: int32_t mmu_ocache_data_read( sh4addr_t addr ); nkeynes@550: int32_t mmu_utlb_addr_read( sh4addr_t addr ); nkeynes@550: int32_t mmu_utlb_data_read( sh4addr_t addr ); nkeynes@550: void mmu_icache_addr_write( sh4addr_t addr, uint32_t val ); nkeynes@550: void mmu_icache_data_write( sh4addr_t addr, uint32_t val ); nkeynes@550: void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val ); nkeynes@550: void mmu_itlb_data_write( sh4addr_t addr, uint32_t val ); nkeynes@550: void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val ); nkeynes@550: void mmu_ocache_data_write( sh4addr_t addr, uint32_t val ); nkeynes@550: void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val ); nkeynes@550: void mmu_utlb_data_write( sh4addr_t addr, uint32_t val ); nkeynes@736: nkeynes@736: nkeynes@736: #ifdef __cplusplus nkeynes@736: } nkeynes@1: #endif nkeynes@736: nkeynes@736: #endif