nkeynes@1: #ifndef dream_sh4_mem_H
nkeynes@1: #define dream_sh4_mem_H
nkeynes@1: 
nkeynes@1: #include <stdint.h>
nkeynes@1: #include "sh4mmio.h"
nkeynes@1: 
nkeynes@1: #ifdef __cplusplus
nkeynes@1: extern "C" {
nkeynes@1: #if 0
nkeynes@1: }
nkeynes@1: #endif
nkeynes@1: #endif
nkeynes@1: 
nkeynes@2: typedef struct mem_region {
nkeynes@1:     uint32_t base;
nkeynes@1:     uint32_t size;
nkeynes@1:     char *name;
nkeynes@1:     char *mem;
nkeynes@1:     int flags;
nkeynes@2: } *mem_region_t;
nkeynes@1: 
nkeynes@1: #define MAX_IO_REGIONS 24
nkeynes@1: #define MAX_MEM_REGIONS 8
nkeynes@1: 
nkeynes@1: #define MEM_REGION_MAIN "System RAM"
nkeynes@1: #define MEM_REGION_VIDEO "Video RAM"
nkeynes@1: #define MEM_REGION_AUDIO "Audio RAM"
nkeynes@1: #define MEM_REGION_AUDIO_SCRATCH "Audio Scratch RAM"
nkeynes@1: 
nkeynes@1: #define MB * (1024 * 1024)
nkeynes@1: #define KB * 1024
nkeynes@1: 
nkeynes@1: int32_t mem_read_long( uint32_t addr );
nkeynes@1: int32_t mem_read_word( uint32_t addr );
nkeynes@1: int32_t mem_read_byte( uint32_t addr );
nkeynes@1: void mem_write_long( uint32_t addr, uint32_t val );
nkeynes@1: void mem_write_word( uint32_t addr, uint32_t val );
nkeynes@1: void mem_write_byte( uint32_t addr, uint32_t val );
nkeynes@1: 
nkeynes@1: int32_t mem_read_phys_word( uint32_t addr );
nkeynes@1: void *mem_create_ram_region( uint32_t base, uint32_t size, char *name );
nkeynes@1: void *mem_load_rom( char *name, uint32_t base, uint32_t size, uint32_t crc );
nkeynes@1: char *mem_get_region( uint32_t addr );
nkeynes@1: char *mem_get_region_by_name( char *name );
nkeynes@1: void mem_set_cache_mode( int );
nkeynes@1: int mem_has_page( uint32_t addr );
nkeynes@1: 
nkeynes@1: void mem_init( void );
nkeynes@1: void mem_reset( void );
nkeynes@1: 
nkeynes@2: #define ENABLE_WATCH 1
nkeynes@2: 
nkeynes@2: #define WATCH_WRITE 1
nkeynes@2: #define WATCH_READ  2
nkeynes@2: #define WATCH_EXEC  3  /* AKA Breakpoint :) */
nkeynes@2: 
nkeynes@2: typedef struct watch_point *watch_point_t;
nkeynes@2: 
nkeynes@2: watch_point_t mem_new_watch( uint32_t start, uint32_t end, int flags );
nkeynes@2: void mem_delete_watch( watch_point_t watch );
nkeynes@2: watch_point_t mem_is_watched( uint32_t addr, int size, int op );
nkeynes@1: 
nkeynes@1: /* mmucr register bits */
nkeynes@1: #define MMUCR_AT   0x00000001 /* Address Translation enabled */
nkeynes@1: #define MMUCR_TI   0x00000004 /* TLB invalidate (always read as 0) */
nkeynes@1: #define MMUCR_SV   0x00000100 /* Single Virtual mode=1 / multiple virtual=0 */
nkeynes@1: #define MMUCR_SQMD 0x00000200 /* Store queue mode bit (0=user, 1=priv only) */
nkeynes@1: #define MMUCR_URC  0x0000FC00 /* UTLB access counter */
nkeynes@1: #define MMUCR_URB  0x00FC0000 /* UTLB entry boundary */
nkeynes@1: #define MMUCR_LRUI 0xFC000000 /* Least recently used ITLB */
nkeynes@1: #define MMUCR_MASK 0xFCFCFF05
nkeynes@1: #define MMUCR_RMASK 0xFCFCFF01 /* Read mask */
nkeynes@1: 
nkeynes@1: #define IS_MMU_ENABLED() (MMIO_READ(MMU, MMUCR)&MMUCR_AT)
nkeynes@1: 
nkeynes@1: /* ccr register bits */
nkeynes@1: #define CCR_IIX    0x00008000 /* IC index enable */
nkeynes@1: #define CCR_ICI    0x00000800 /* IC invalidation (always read as 0) */
nkeynes@1: #define CCR_ICE    0x00000100 /* IC enable */
nkeynes@1: #define CCR_OIX    0x00000080 /* OC index enable */
nkeynes@1: #define CCR_ORA    0x00000020 /* OC RAM enable */
nkeynes@1: #define CCR_OCI    0x00000008 /* OC invalidation (always read as 0) */
nkeynes@1: #define CCR_CB     0x00000004 /* Copy-back (P1 area cache write mode) */
nkeynes@1: #define CCR_WT     0x00000002 /* Write-through (P0,U0,P3 write mode) */
nkeynes@1: #define CCR_OCE    0x00000001 /* OC enable */
nkeynes@1: #define CCR_MASK   0x000089AF
nkeynes@1: #define CCR_RMASK  0x000081A7 /* Read mask */
nkeynes@1: 
nkeynes@1: #define MEM_OC_DISABLED 0
nkeynes@1: #define MEM_OC_INDEX0   CCR_ORA
nkeynes@1: #define MEM_OC_INDEX1   CCR_ORA|CCR_OIX
nkeynes@1: 
nkeynes@1: #ifdef __cplusplus
nkeynes@1: }
nkeynes@1: #endif
nkeynes@1: #endif