nkeynes@31: /** nkeynes@265: * $Id: asic.h,v 1.15 2007-01-06 04:06:36 nkeynes Exp $ nkeynes@31: * nkeynes@31: * Support for the miscellaneous ASIC functions (Primarily event multiplexing, nkeynes@31: * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions, nkeynes@31: * although some functions (maple, ide) are implemented elsewhere. nkeynes@31: * nkeynes@31: * Copyright (c) 2005 Nathan Keynes. nkeynes@31: * nkeynes@31: * This program is free software; you can redistribute it and/or modify nkeynes@31: * it under the terms of the GNU General Public License as published by nkeynes@31: * the Free Software Foundation; either version 2 of the License, or nkeynes@31: * (at your option) any later version. nkeynes@31: * nkeynes@31: * This program is distributed in the hope that it will be useful, nkeynes@31: * but WITHOUT ANY WARRANTY; without even the implied warranty of nkeynes@31: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the nkeynes@31: * GNU General Public License for more details. nkeynes@31: */ nkeynes@31: nkeynes@1: #include "mmio.h" nkeynes@1: nkeynes@1: /** nkeynes@1: * ASIC interrupts are mappable to any (or all of) 3 actual CPU IRQ lines. nkeynes@1: * events selected for IRQA trigger IRQ 13, IRQB => 11 and IRQC => 9. nkeynes@1: */ nkeynes@1: nkeynes@1: MMIO_REGION_BEGIN( 0x005F6000, ASIC, "System ASIC" ) nkeynes@56: LONG_PORT( 0x800, PVRDMADEST, PORT_MRW, 0, "PVR DMA Dest Address" ) nkeynes@56: LONG_PORT( 0x804, PVRDMACNT, PORT_MRW, 0, "PVR DMA Byte Count" ) nkeynes@56: LONG_PORT( 0x808, PVRDMACTL, PORT_MRW, 0, "PVR DMA Control" ) nkeynes@147: LONG_PORT( 0x810, ASICUNK1, PORT_MRW, 0, "ASIC " ) nkeynes@147: LONG_PORT( 0x814, ASICUNK2, PORT_MRW, 0, "ASIC " ) nkeynes@56: LONG_PORT( 0x818, ASICUNK3, PORT_MRW, 0, "ASIC " ) nkeynes@56: LONG_PORT( 0x81C, ASICUNK4, PORT_MRW, 0, "ASIC " ) nkeynes@147: LONG_PORT( 0x820, ASICUNKF, PORT_MRW, 0, "ASIC " ) nkeynes@147: LONG_PORT( 0x840, ASICUNK5, PORT_MRW, 0, "ASIC " ) nkeynes@147: LONG_PORT( 0x844, ASICUNK6, PORT_MRW, 0, "ASIC " ) nkeynes@147: LONG_PORT( 0x848, ASICUNK7, PORT_MRW, 0, "ASIC " ) nkeynes@147: LONG_PORT( 0x84C, ASICUNK8, PORT_MRW, 0, "ASIC " ) nkeynes@184: LONG_PORT( 0x884, PVRDMARGN, PORT_MRW, 0, "PVR DMA Dest region" ) nkeynes@147: LONG_PORT( 0x888, ASICUNKA, PORT_MRW, 0, "ASIC " ) nkeynes@172: LONG_PORT( 0x88C, G2STATUS, PORT_MR|PORT_NOTRACE, 0, "G2 Bus status" ) nkeynes@244: LONG_PORT( 0x890, SYSRESET, PORT_W, 0, "System reset port" ) nkeynes@147: LONG_PORT( 0x89C, ASICUNKB, PORT_MRW, 0xB, "Unknown, always 0xB?" ) nkeynes@147: LONG_PORT( 0x8A0, ASICUNKC, PORT_MRW, 0, "ASIC " ) nkeynes@147: LONG_PORT( 0x8A4, ASICUNKD, PORT_MRW, 0, "ASIC " ) nkeynes@147: LONG_PORT( 0x8AC, ASICUNKE, PORT_MRW, 0, "ASIC " ) nkeynes@172: LONG_PORT( 0x900, PIRQ0, PORT_MRW|PORT_NOTRACE, 0, "Pending interrupts 0" ) nkeynes@1: LONG_PORT( 0x904, PIRQ1, PORT_MRW, 0, "Pending interrupts 1" ) nkeynes@1: LONG_PORT( 0x908, PIRQ2, PORT_MRW, 0, "Pending interrupts 2" ) nkeynes@1: LONG_PORT( 0x910, IRQA0, PORT_MRW, 0, "IRQ A event map 0" ) nkeynes@1: LONG_PORT( 0x914, IRQA1, PORT_MRW, 0, "IRQ A event map 1" ) nkeynes@1: LONG_PORT( 0x918, IRQA2, PORT_MRW, 0, "IRQ A event map 2" ) nkeynes@1: LONG_PORT( 0x920, IRQB0, PORT_MRW, 0, "IRQ B event map 0" ) nkeynes@1: LONG_PORT( 0x924, IRQB1, PORT_MRW, 0, "IRQ B event map 1" ) nkeynes@1: LONG_PORT( 0x928, IRQB2, PORT_MRW, 0, "IRQ B event map 2" ) nkeynes@1: LONG_PORT( 0x930, IRQC0, PORT_MRW, 0, "IRQ C event map 0" ) nkeynes@1: LONG_PORT( 0x934, IRQC1, PORT_MRW, 0, "IRQ C event map 1" ) nkeynes@1: LONG_PORT( 0x938, IRQC2, PORT_MRW, 0, "IRQ C event map 2" ) nkeynes@2: LONG_PORT( 0x940, ASIC9UNK1, PORT_MRW, 0, "Unknown 1" ) nkeynes@2: LONG_PORT( 0x944, ASIC9UNK2, PORT_MRW, 0, "Unknown 2" ) nkeynes@2: LONG_PORT( 0x950, ASIC9UNK3, PORT_MRW, 0, "Unknown 3" ) nkeynes@2: LONG_PORT( 0x954, ASIC9UNK4, PORT_MRW, 0, "Unknown 4" ) nkeynes@2: /* ASIC events repeats at 0x980..0x9FF, then the whole region 800..9ff nkeynes@2: * repeats at 000..1ff, 200..3ff, 400..5ff, 600..7ff, a00..bff. nkeynes@2: * The whole region 800..8ff is long-readable, but since I so far have no idea nkeynes@2: * what any of it means (nor have I seen any of it accessed), they're not nkeynes@2: * listed above. nkeynes@2: */ nkeynes@56: nkeynes@1: nkeynes@1: LONG_PORT( 0xC04, MAPLE_DMA, PORT_MRW, UNDEFINED, "Maple DMA Address" ) nkeynes@1: LONG_PORT( 0xC10, MAPLE_RESET2, PORT_MRW, UNDEFINED, "Maple Reset 2" ) nkeynes@1: LONG_PORT( 0xC14, MAPLE_ENABLE, PORT_MRW, UNDEFINED, "Maple Enable" ) nkeynes@1: LONG_PORT( 0xC18, MAPLE_STATE, PORT_MRW, 0, "Maple State" ) nkeynes@2: LONG_PORT( 0xC70, MAPLE_UNK1, PORT_MRW, 0, "Maple unknown 1" ) nkeynes@2: LONG_PORT( 0xC74, MAPLE_UNK2, PORT_MRW, 0, "Maple unknown 2" ) nkeynes@2: LONG_PORT( 0xC78, MAPLE_UNK3, PORT_MRW, 0, "Maple unknown 3" ) nkeynes@2: LONG_PORT( 0xC7C, MAPLE_UNK4, PORT_MRW, 0, "Maple unknown 4" ) nkeynes@1: LONG_PORT( 0xC80, MAPLE_SPEED, PORT_MRW, UNDEFINED, "Maple Speed" ) nkeynes@2: LONG_PORT( 0xC84, MAPLE_UNK5, PORT_MRW, 0, "Maple unknown 5" ) nkeynes@1: LONG_PORT( 0xC8C, MAPLE_RESET1, PORT_MRW, UNDEFINED, "Maple Reset 1" ) nkeynes@2: LONG_PORT( 0xCE8, MAPLE_UNK6, PORT_MRW, 0, "Maple unknown 6" ) nkeynes@2: LONG_PORT( 0xCF4, MAPLE_SRC, PORT_MRW, 0, "Maple current source" ) nkeynes@2: LONG_PORT( 0xCF8, MAPLE_DEST1, PORT_MRW, 0, "Maple current destination" ) nkeynes@2: LONG_PORT( 0xCFC, MAPLE_DEST2, PORT_MRW, 0, "Maple current destination 2?" ) nkeynes@2: /* Note: Maple registers repeat at 0xD00..0xDFF, nkeynes@2: * 0xE00..0xEFF and 0xF00..0xFFF */ nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@1: MMIO_REGION_BEGIN( 0x005F7000, EXTDMA, "ASIC External DMA" ) nkeynes@2: BYTE_PORT( 0x018, IDEALTSTATUS, PORT_RW, 0, "IDE Device Control / Alt-status" ) /* 10110 */ nkeynes@2: BYTE_PORT( 0x01C, IDEUNK1, PORT_MRW, 0, "IDE Unknown" ) nkeynes@2: WORD_PORT( 0x080, IDEDATA, PORT_RW, 0, "IDE Data" ) nkeynes@2: BYTE_PORT( 0x084, IDEFEAT, PORT_RW, 0, "IDE Feature / Error" ) nkeynes@2: BYTE_PORT( 0x088, IDECOUNT, PORT_RW, 0, "IDE Sector Count" ) nkeynes@2: BYTE_PORT( 0x08C, IDELBA0, PORT_RW, 0, "IDE LBA lo" ) /* AKA sector */ nkeynes@2: BYTE_PORT( 0x090, IDELBA1, PORT_RW, 0, "IDE LBA mid" ) /* AKA Cyl lo */ nkeynes@2: BYTE_PORT( 0x094, IDELBA2, PORT_RW, 0, "IDE LBA hi" ) /* AKA Cyl hi */ nkeynes@2: BYTE_PORT( 0x098, IDEDEV, PORT_RW, 0, "IDE Device" ) nkeynes@2: BYTE_PORT( 0x09C, IDECMD, PORT_RW, 0, "IDE Command/Status" ) nkeynes@125: LONG_PORT( 0x404, IDEDMASH4, PORT_MRW, 0, "IDE DMA SH4 address" ) nkeynes@125: LONG_PORT( 0x408, IDEDMASIZ, PORT_MRW, 0, "IDE DMA Size" ) nkeynes@125: LONG_PORT( 0x40C, IDEDMADIR, PORT_MRW, 0, "IDE DMA Direction" ) nkeynes@125: LONG_PORT( 0x414, IDEDMACTL1, PORT_MRW, 0, "IDE DMA Control 1" ) nkeynes@125: LONG_PORT( 0x418, IDEDMACTL2, PORT_MRW, 0, "IDE DMA Control 2" ) nkeynes@1: WORD_PORT( 0x480, EXTDMAUNK0, PORT_MRW, 0, "Ext DMA " ) nkeynes@1: LONG_PORT( 0x484, EXTDMAUNK1, PORT_MRW, 0, "Ext DMA " ) nkeynes@1: LONG_PORT( 0x488, EXTDMAUNK2, PORT_MRW, 0, "Ext DMA " ) nkeynes@1: LONG_PORT( 0x48C, EXTDMAUNK3, PORT_MRW, 0, "Ext DMA " ) nkeynes@1: LONG_PORT( 0x490, EXTDMAUNK4, PORT_MRW, 0, "Ext DMA " ) nkeynes@1: LONG_PORT( 0x494, EXTDMAUNK5, PORT_MRW, 0, "Ext DMA " ) nkeynes@1: LONG_PORT( 0x4A0, EXTDMAUNK6, PORT_MRW, 0, "Ext DMA " ) nkeynes@1: LONG_PORT( 0x4A4, EXTDMAUNK7, PORT_MRW, 0, "Ext DMA " ) nkeynes@1: LONG_PORT( 0x4B4, EXTDMAUNK8, PORT_MRW, 0, "Ext DMA " ) nkeynes@172: LONG_PORT( 0x4B8, IDEDMACFG, PORT_MRW, 0, "IDE DMA Config" ) /* 88437F00 */ nkeynes@2: LONG_PORT( 0x4E4, IDEACTIVATE, PORT_MRW, 0, "IDE activate" ) nkeynes@158: LONG_PORT( 0x4F8, IDEDMATXSIZ, PORT_MRW, 0, "IDE DMA transfered size" ) nkeynes@1: LONG_PORT( 0x800, SPUDMA0EXT, PORT_MRW, 0, "SPU DMA0 External address" ) nkeynes@1: LONG_PORT( 0x804, SPUDMA0SH4, PORT_MRW, 0, "SPU DMA0 SH4-based address" ) nkeynes@1: LONG_PORT( 0x808, SPUDMA0SIZ, PORT_MRW, 0, "SPU DMA0 Size" ) nkeynes@1: LONG_PORT( 0x80C, SPUDMA0DIR, PORT_MRW, 0, "SPU DMA0 Direction" ) nkeynes@1: LONG_PORT( 0x810, SPUDMA0MOD, PORT_MRW, 0, "SPU DMA0 Mode" ) nkeynes@1: LONG_PORT( 0x814, SPUDMA0CTL1, PORT_MRW, 0, "SPU DMA0 Control 1" ) nkeynes@1: LONG_PORT( 0x818, SPUDMA0CTL2, PORT_MRW, 0, "SPU DMA0 Control 2" ) nkeynes@1: LONG_PORT( 0x81C, SPUDMA0UN1, PORT_MRW, 0, "SPU DMA0 " ) nkeynes@1: LONG_PORT( 0x820, SPUDMA1EXT, PORT_MRW, 0, "SPU DMA1 External address" ) nkeynes@1: LONG_PORT( 0x824, SPUDMA1SH4, PORT_MRW, 0, "SPU DMA1 SH4-based address" ) nkeynes@1: LONG_PORT( 0x828, SPUDMA1SIZ, PORT_MRW, 0, "SPU DMA1 Size" ) nkeynes@1: LONG_PORT( 0x82C, SPUDMA1DIR, PORT_MRW, 0, "SPU DMA1 Direction" ) nkeynes@1: LONG_PORT( 0x830, SPUDMA1MOD, PORT_MRW, 0, "SPU DMA1 Mode" ) nkeynes@1: LONG_PORT( 0x834, SPUDMA1CTL1, PORT_MRW, 0, "SPU DMA1 Control 1" ) nkeynes@1: LONG_PORT( 0x838, SPUDMA1CTL2, PORT_MRW, 0, "SPU DMA1 Control 2" ) nkeynes@1: LONG_PORT( 0x83C, SPUDMA1UN1, PORT_MRW, 0, "SPU DMA1 " ) nkeynes@1: LONG_PORT( 0x840, SPUDMA2EXT, PORT_MRW, 0, "SPU DMA2 External address" ) nkeynes@1: LONG_PORT( 0x844, SPUDMA2SH4, PORT_MRW, 0, "SPU DMA2 SH4-based address" ) nkeynes@1: LONG_PORT( 0x848, SPUDMA2SIZ, PORT_MRW, 0, "SPU DMA2 Size" ) nkeynes@1: LONG_PORT( 0x84C, SPUDMA2DIR, PORT_MRW, 0, "SPU DMA2 Direction" ) nkeynes@1: LONG_PORT( 0x850, SPUDMA2MOD, PORT_MRW, 0, "SPU DMA2 Mode" ) nkeynes@1: LONG_PORT( 0x854, SPUDMA2CTL1, PORT_MRW, 0, "SPU DMA2 Control 1" ) nkeynes@1: LONG_PORT( 0x858, SPUDMA2CTL2, PORT_MRW, 0, "SPU DMA2 Control 2" ) nkeynes@1: LONG_PORT( 0x85C, SPUDMA2UN1, PORT_MRW, 0, "SPU DMA2 " ) nkeynes@1: LONG_PORT( 0x860, SPUDMA3EXT, PORT_MRW, 0, "SPU DMA3 External address" ) nkeynes@1: LONG_PORT( 0x864, SPUDMA3SH4, PORT_MRW, 0, "SPU DMA3 SH4-based address" ) nkeynes@1: LONG_PORT( 0x868, SPUDMA3SIZ, PORT_MRW, 0, "SPU DMA3 Size" ) nkeynes@1: LONG_PORT( 0x86C, SPUDMA3DIR, PORT_MRW, 0, "SPU DMA3 Direction" ) nkeynes@1: LONG_PORT( 0x870, SPUDMA3MOD, PORT_MRW, 0, "SPU DMA3 Mode" ) nkeynes@1: LONG_PORT( 0x874, SPUDMA3CTL1, PORT_MRW, 0, "SPU DMA3 Control 1" ) nkeynes@1: LONG_PORT( 0x878, SPUDMA3CTL2, PORT_MRW, 0, "SPU DMA3 Control 2" ) nkeynes@1: LONG_PORT( 0x87C, SPUDMA3UN1, PORT_MRW, 0, "SPU DMA3 " ) nkeynes@1: LONG_PORT( 0x890, SPUDMAWAIT, PORT_MRW, 0, "SPU DMA wait states (?)" ) nkeynes@1: LONG_PORT( 0x894, SPUDMAUN1, PORT_MRW, 0, "SPU DMA " ) nkeynes@1: LONG_PORT( 0x898, SPUDMAUN2, PORT_MRW, 0, "SPU DMA " ) nkeynes@1: LONG_PORT( 0x89C, SPUDMAUN3, PORT_MRW, 0, "SPU DMA " ) nkeynes@1: LONG_PORT( 0x8A0, SPUDMAUN4, PORT_MRW, 0, "SPU DMA " ) nkeynes@1: LONG_PORT( 0x8A4, SPUDMAUN5, PORT_MRW, 0, "SPU DMA " ) nkeynes@1: LONG_PORT( 0x8A8, SPUDMAUN6, PORT_MRW, 0, "SPU DMA " ) nkeynes@1: LONG_PORT( 0x8AC, SPUDMAUN7, PORT_MRW, 0, "SPU DMA " ) nkeynes@1: LONG_PORT( 0x8B0, SPUDMAUN8, PORT_MRW, 0, "SPU DMA " ) nkeynes@1: LONG_PORT( 0x8B4, SPUDMAUN9, PORT_MRW, 0, "SPU DMA " ) nkeynes@1: LONG_PORT( 0x8B8, SPUDMAUN10, PORT_MRW, 0, "SPU DMA " ) nkeynes@172: LONG_PORT( 0x8BC, SPUDMACFG, PORT_MRW, 0, "SPU DMA Config" ) /* 46597F00 */ nkeynes@56: LONG_PORT( 0xC00, PVRDMA2EXT, PORT_MRW, 0, "PVR DMA External address" ) nkeynes@56: LONG_PORT( 0xC04, PVRDMA2SH4, PORT_MRW, 0, "PVR DMA SH4 address" ) nkeynes@56: LONG_PORT( 0xC08, PVRDMA2SIZ, PORT_MRW, 0, "PVR DMA Size" ) nkeynes@56: LONG_PORT( 0xC0C, PVRDMA2DIR, PORT_MRW, 0, "PVR DMA Direction" ) nkeynes@56: LONG_PORT( 0xC10, PVRDMA2MOD, PORT_MRW, 0, "PVR DMA Mode" ) nkeynes@56: LONG_PORT( 0xC14, PVRDMA2CTL1, PORT_MRW, 0, "PVR DMA Control 1" ) nkeynes@56: LONG_PORT( 0xC18, PVRDMA2CTL2, PORT_MRW, 0, "PVR DMA Control 2" ) nkeynes@172: LONG_PORT( 0xC80, PVRDMA2CFG, PORT_MRW, 0, "PVR DMA Config" ) /* 67027F00 */ nkeynes@1: nkeynes@1: MMIO_REGION_END nkeynes@1: nkeynes@56: #define EVENT_PVR_RENDER_DONE 2 nkeynes@265: #define EVENT_SCANLINE2 3 nkeynes@265: #define EVENT_SCANLINE1 4 nkeynes@1: #define EVENT_RETRACE 5 nkeynes@65: #define EVENT_PVR_UNK 6 nkeynes@56: #define EVENT_PVR_OPAQUE_DONE 7 nkeynes@56: #define EVENT_PVR_OPAQUEMOD_DONE 8 nkeynes@56: #define EVENT_PVR_TRANS_DONE 9 nkeynes@65: #define EVENT_PVR_TRANSMOD_DONE 10 nkeynes@1: #define EVENT_MAPLE_DMA 12 nkeynes@1: #define EVENT_MAPLE_ERR 13 /* ??? */ nkeynes@125: #define EVENT_IDE_DMA 14 nkeynes@56: #define EVENT_SPU_DMA0 15 nkeynes@1: #define EVENT_SPU_DMA1 16 nkeynes@1: #define EVENT_SPU_DMA2 17 nkeynes@1: #define EVENT_SPU_DMA3 18 nkeynes@56: #define EVENT_PVR_DMA 19 nkeynes@56: #define EVENT_PVR_PUNCHOUT_DONE 21 nkeynes@56: nkeynes@189: #define EVENT_TA_ERROR 31 nkeynes@125: #define EVENT_IDE 32 nkeynes@1: #define EVENT_AICA 33 nkeynes@1: nkeynes@184: #define EVENT_PVR_PRIM_ALLOC_FAIL 66 nkeynes@184: #define EVENT_PVR_MATRIX_ALLOC_FAIL 67 nkeynes@189: #define EVENT_PVR_BAD_INPUT 68 nkeynes@184: nkeynes@244: #define IS_IDE_REGISTER(x) ( (x) <= IDEDMACTL2 ) nkeynes@244: nkeynes@125: /** nkeynes@125: * Raise an ASIC event nkeynes@125: */ nkeynes@1: void asic_event( int event ); nkeynes@125: nkeynes@125: /** nkeynes@125: * Clear an ASIC event. Currently only the IDE controller is known to use nkeynes@125: * this functionality. nkeynes@125: */ nkeynes@125: void asic_clear_event( int event ); nkeynes@125: nkeynes@137: void asic_g2_write_word( );