nkeynes@2: 
nkeynes@2: #ifndef dream_armcore_H
nkeynes@2: #define dream_armcore_H 1
nkeynes@2: 
nkeynes@2: #include "dream.h"
nkeynes@2: #include <stdint.h>
nkeynes@2: 
nkeynes@2: 
nkeynes@2: 
nkeynes@2: struct arm_registers {
nkeynes@2:   uint32_t r[16]; /* Current register bank */
nkeynes@2: 
nkeynes@2:   uint32_t cpsr;
nkeynes@2:   uint32_t spsr;
nkeynes@2: 
nkeynes@2:   /* Various banked versions of the registers. */
nkeynes@2:   uint32_t fiq_r[7]; /* FIQ bank 8..14 */
nkeynes@2:   uint32_t irq_r[2]; /* IRQ bank 13..14 */
nkeynes@2:   uint32_t und_r[2]; /* UND bank 13..14 */
nkeynes@2:   uint32_t abt_r[2]; /* ABT bank 13..14 */
nkeynes@2:   uint32_t svc_r[2]; /* SVC bank 13..14 */
nkeynes@2:   uint32_t user_r[7]; /* User/System bank 8..14 */
nkeynes@2: 
nkeynes@5:   uint32_t c,n,z,v,t;
nkeynes@5:   
nkeynes@5:   /* "fake" registers */
nkeynes@5:   uint32_t shift_c;  /* used for temporary storage of shifter results */
nkeynes@2: };
nkeynes@2: 
nkeynes@2: #define CPSR_N 0x80000000 /* Negative flag */
nkeynes@2: #define CPSR_Z 0x40000000 /* Zero flag */
nkeynes@2: #define CPSR_C 0x20000000 /* Carry flag */
nkeynes@2: #define CPSR_V 0x10000000 /* Overflow flag */
nkeynes@2: #define CPSR_I 0x00000080 /* Interrupt disable bit */ 
nkeynes@2: #define CPSR_F 0x00000040 /* Fast interrupt disable bit */
nkeynes@2: #define CPSR_T 0x00000020 /* Thumb mode */
nkeynes@2: #define CPSR_MODE 0x0000001F /* Current execution mode */
nkeynes@2: 
nkeynes@2: #define MODE_USER 0x00 /* User mode */
nkeynes@2: #define MODE_FIQ   0x01 /* Fast IRQ mode */
nkeynes@2: #define MODE_IRQ  0x02 /* IRQ mode */
nkeynes@2: #define MODE_SV   0x03 /* Supervisor mode */
nkeynes@2: #define MODE_ABT 0x07 /* Abort mode */
nkeynes@2: #define MODE_UND 0x0B /* Undefined mode */
nkeynes@2: #define MODE_SYS 0x0F /* System mode */
nkeynes@2: 
nkeynes@2: extern struct arm_registers armr;
nkeynes@2: 
nkeynes@5: #define CARRY_FLAG (armr.cpsr&CPSR_C)
nkeynes@2: 
nkeynes@2: #endif /* !dream_armcore_H */