nkeynes@378: /**
nkeynes@586:  * $Id$
nkeynes@378:  * 
nkeynes@378:  * SH4 parent module for all CPU modes and SH4 peripheral
nkeynes@378:  * modules.
nkeynes@378:  *
nkeynes@378:  * Copyright (c) 2005 Nathan Keynes.
nkeynes@378:  *
nkeynes@378:  * This program is free software; you can redistribute it and/or modify
nkeynes@378:  * it under the terms of the GNU General Public License as published by
nkeynes@378:  * the Free Software Foundation; either version 2 of the License, or
nkeynes@378:  * (at your option) any later version.
nkeynes@378:  *
nkeynes@378:  * This program is distributed in the hope that it will be useful,
nkeynes@378:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@378:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@378:  * GNU General Public License for more details.
nkeynes@378:  */
nkeynes@378: 
nkeynes@378: #define MODULE sh4_module
nkeynes@378: #include <math.h>
nkeynes@740: #include <setjmp.h>
nkeynes@617: #include <assert.h>
nkeynes@671: #include "lxdream.h"
nkeynes@422: #include "dreamcast.h"
nkeynes@669: #include "mem.h"
nkeynes@669: #include "clock.h"
nkeynes@669: #include "eventq.h"
nkeynes@669: #include "syscall.h"
nkeynes@669: #include "sh4/intc.h"
nkeynes@968: #include "sh4/mmu.h"
nkeynes@378: #include "sh4/sh4core.h"
nkeynes@378: #include "sh4/sh4mmio.h"
nkeynes@422: #include "sh4/sh4stat.h"
nkeynes@617: #include "sh4/sh4trans.h"
nkeynes@669: #include "sh4/xltcache.h"
nkeynes@378: 
nkeynes@378: void sh4_init( void );
nkeynes@526: void sh4_xlat_init( void );
nkeynes@953: void sh4_poweron_reset( void );
nkeynes@378: void sh4_start( void );
nkeynes@378: void sh4_stop( void );
nkeynes@378: void sh4_save_state( FILE *f );
nkeynes@378: int sh4_load_state( FILE *f );
nkeynes@378: 
nkeynes@378: uint32_t sh4_run_slice( uint32_t );
nkeynes@378: uint32_t sh4_xlat_run_slice( uint32_t );
nkeynes@378: 
nkeynes@953: struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_poweron_reset, 
nkeynes@736:         sh4_start, sh4_run_slice, sh4_stop,
nkeynes@736:         sh4_save_state, sh4_load_state };
nkeynes@378: 
nkeynes@903: struct sh4_registers sh4r __attribute__((aligned(16)));
nkeynes@378: struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
nkeynes@378: int sh4_breakpoint_count = 0;
nkeynes@953: 
nkeynes@591: gboolean sh4_starting = FALSE;
nkeynes@526: static gboolean sh4_use_translator = FALSE;
nkeynes@740: static jmp_buf sh4_exit_jmp_buf;
nkeynes@740: static gboolean sh4_running = FALSE;
nkeynes@586: struct sh4_icache_struct sh4_icache = { NULL, -1, -1, 0 };
nkeynes@378: 
nkeynes@740: void sh4_translate_set_enabled( gboolean use )
nkeynes@378: {
nkeynes@736:     // No-op if the translator was not built
nkeynes@526: #ifdef SH4_TRANSLATOR
nkeynes@378:     if( use ) {
nkeynes@736:         sh4_translate_init();
nkeynes@378:     }
nkeynes@526:     sh4_use_translator = use;
nkeynes@526: #endif
nkeynes@378: }
nkeynes@378: 
nkeynes@740: gboolean sh4_translate_is_enabled()
nkeynes@586: {
nkeynes@586:     return sh4_use_translator;
nkeynes@586: }
nkeynes@586: 
nkeynes@378: void sh4_init(void)
nkeynes@378: {
nkeynes@378:     register_io_regions( mmio_list_sh4mmio );
nkeynes@378:     MMU_init();
nkeynes@619:     TMU_init();
nkeynes@953:     xlat_cache_init();
nkeynes@953:     sh4_poweron_reset();
nkeynes@671: #ifdef ENABLE_SH4STATS
nkeynes@671:     sh4_stats_reset();
nkeynes@671: #endif
nkeynes@378: }
nkeynes@378: 
nkeynes@591: void sh4_start(void)
nkeynes@591: {
nkeynes@591:     sh4_starting = TRUE;
nkeynes@591: }
nkeynes@591: 
nkeynes@953: void sh4_poweron_reset(void)
nkeynes@378: {
nkeynes@953:     /* zero everything out, for the sake of having a consistent state. */
nkeynes@953:     memset( &sh4r, 0, sizeof(sh4r) );
nkeynes@526:     if(	sh4_use_translator ) {
nkeynes@736:         xlat_flush_cache();
nkeynes@472:     }
nkeynes@472: 
nkeynes@378:     /* Resume running if we were halted */
nkeynes@378:     sh4r.sh4_state = SH4_STATE_RUNNING;
nkeynes@378: 
nkeynes@378:     sh4r.pc    = 0xA0000000;
nkeynes@378:     sh4r.new_pc= 0xA0000002;
nkeynes@378:     sh4r.vbr   = 0x00000000;
nkeynes@378:     sh4r.fpscr = 0x00040001;
nkeynes@953:     sh4_write_sr(0x700000F0);
nkeynes@378: 
nkeynes@378:     /* Mem reset will do this, but if we want to reset _just_ the SH4... */
nkeynes@378:     MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET );
nkeynes@378: 
nkeynes@378:     /* Peripheral modules */
nkeynes@378:     CPG_reset();
nkeynes@378:     INTC_reset();
nkeynes@841:     PMM_reset();
nkeynes@378:     TMU_reset();
nkeynes@378:     SCIF_reset();
nkeynes@953:     MMU_reset();
nkeynes@378: }
nkeynes@378: 
nkeynes@378: void sh4_stop(void)
nkeynes@378: {
nkeynes@526:     if(	sh4_use_translator ) {
nkeynes@736:         /* If we were running with the translator, update new_pc and in_delay_slot */
nkeynes@736:         sh4r.new_pc = sh4r.pc+2;
nkeynes@736:         sh4r.in_delay_slot = FALSE;
nkeynes@502:     }
nkeynes@378: 
nkeynes@378: }
nkeynes@378: 
nkeynes@740: /**
nkeynes@740:  * Execute a timeslice using translated code only (ie translate/execute loop)
nkeynes@740:  */
nkeynes@740: uint32_t sh4_run_slice( uint32_t nanosecs ) 
nkeynes@740: {
nkeynes@740:     sh4r.slice_cycle = 0;
nkeynes@740: 
nkeynes@740:     if( sh4r.sh4_state != SH4_STATE_RUNNING ) {
nkeynes@740:         sh4_sleep_run_slice(nanosecs);
nkeynes@740:     }
nkeynes@740: 
nkeynes@740:     /* Setup for sudden vm exits */
nkeynes@740:     switch( setjmp(sh4_exit_jmp_buf) ) {
nkeynes@740:     case CORE_EXIT_BREAKPOINT:
nkeynes@740:         sh4_clear_breakpoint( sh4r.pc, BREAK_ONESHOT );
nkeynes@740:         /* fallthrough */
nkeynes@740:     case CORE_EXIT_HALT:
nkeynes@740:         if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
nkeynes@740:             TMU_run_slice( sh4r.slice_cycle );
nkeynes@740:             SCIF_run_slice( sh4r.slice_cycle );
nkeynes@841:             PMM_run_slice( sh4r.slice_cycle );
nkeynes@740:             dreamcast_stop();
nkeynes@740:             return sh4r.slice_cycle;
nkeynes@740:         }
nkeynes@740:     case CORE_EXIT_SYSRESET:
nkeynes@740:         dreamcast_reset();
nkeynes@740:         break;
nkeynes@740:     case CORE_EXIT_SLEEP:
nkeynes@740:         sh4_sleep_run_slice(nanosecs);
nkeynes@740:         break;  
nkeynes@740:     case CORE_EXIT_FLUSH_ICACHE:
nkeynes@740:         xlat_flush_cache();
nkeynes@740:         break;
nkeynes@740:     }
nkeynes@740: 
nkeynes@740:     sh4_running = TRUE;
nkeynes@740:     
nkeynes@740:     /* Execute the core's real slice */
nkeynes@740: #ifdef SH4_TRANSLATOR
nkeynes@740:     if( sh4_use_translator ) {
nkeynes@740:         sh4_translate_run_slice(nanosecs);
nkeynes@740:     } else {
nkeynes@740:         sh4_emulate_run_slice(nanosecs);
nkeynes@740:     }
nkeynes@740: #else
nkeynes@740:     sh4_emulate_run_slice(nanosecs);
nkeynes@740: #endif
nkeynes@740:     
nkeynes@740:     /* And finish off the peripherals afterwards */
nkeynes@740: 
nkeynes@740:     sh4_running = FALSE;
nkeynes@740:     sh4_starting = FALSE;
nkeynes@740:     sh4r.slice_cycle = nanosecs;
nkeynes@740:     if( sh4r.sh4_state != SH4_STATE_STANDBY ) {
nkeynes@740:         TMU_run_slice( nanosecs );
nkeynes@740:         SCIF_run_slice( nanosecs );
nkeynes@841:         PMM_run_slice( sh4r.slice_cycle );
nkeynes@740:     }
nkeynes@740:     return nanosecs;   
nkeynes@740: }
nkeynes@740: 
nkeynes@740: void sh4_core_exit( int exit_code )
nkeynes@740: {
nkeynes@740:     if( sh4_running ) {
nkeynes@740: #ifdef SH4_TRANSLATOR
nkeynes@740:         if( sh4_use_translator ) {
nkeynes@953:             if( exit_code == CORE_EXIT_EXCEPTION ) {
nkeynes@953:                 sh4_translate_exception_exit_recover();
nkeynes@953:             } else {
nkeynes@953:                 sh4_translate_exit_recover();
nkeynes@953:             }
nkeynes@740:         }
nkeynes@740: #endif
nkeynes@953:         if( exit_code != CORE_EXIT_EXCEPTION ) {
nkeynes@953:             sh4_finalize_instruction();
nkeynes@953:         }
nkeynes@740:         // longjmp back into sh4_run_slice
nkeynes@740:         sh4_running = FALSE;
nkeynes@740:         longjmp(sh4_exit_jmp_buf, exit_code);
nkeynes@740:     }
nkeynes@740: }
nkeynes@740: 
nkeynes@378: void sh4_save_state( FILE *f )
nkeynes@378: {
nkeynes@526:     if(	sh4_use_translator ) {
nkeynes@736:         /* If we were running with the translator, update new_pc and in_delay_slot */
nkeynes@736:         sh4r.new_pc = sh4r.pc+2;
nkeynes@736:         sh4r.in_delay_slot = FALSE;
nkeynes@401:     }
nkeynes@401: 
nkeynes@953:     fwrite( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
nkeynes@378:     MMU_save_state( f );
nkeynes@953:     CCN_save_state( f );
nkeynes@841:     PMM_save_state( f );
nkeynes@378:     INTC_save_state( f );
nkeynes@378:     TMU_save_state( f );
nkeynes@378:     SCIF_save_state( f );
nkeynes@378: }
nkeynes@378: 
nkeynes@378: int sh4_load_state( FILE * f )
nkeynes@378: {
nkeynes@526:     if(	sh4_use_translator ) {
nkeynes@736:         xlat_flush_cache();
nkeynes@472:     }
nkeynes@953:     fread( &sh4r, offsetof(struct sh4_registers, xlat_sh4_mode), 1, f );
nkeynes@953:     sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
nkeynes@378:     MMU_load_state( f );
nkeynes@953:     CCN_load_state( f );
nkeynes@841:     PMM_load_state( f );
nkeynes@378:     INTC_load_state( f );
nkeynes@378:     TMU_load_state( f );
nkeynes@378:     return SCIF_load_state( f );
nkeynes@378: }
nkeynes@378: 
nkeynes@586: void sh4_set_breakpoint( uint32_t pc, breakpoint_type_t type )
nkeynes@378: {
nkeynes@378:     sh4_breakpoints[sh4_breakpoint_count].address = pc;
nkeynes@378:     sh4_breakpoints[sh4_breakpoint_count].type = type;
nkeynes@586:     if( sh4_use_translator ) {
nkeynes@736:         xlat_invalidate_word( pc );
nkeynes@586:     }
nkeynes@378:     sh4_breakpoint_count++;
nkeynes@378: }
nkeynes@378: 
nkeynes@586: gboolean sh4_clear_breakpoint( uint32_t pc, breakpoint_type_t type )
nkeynes@378: {
nkeynes@378:     int i;
nkeynes@378: 
nkeynes@378:     for( i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@736:         if( sh4_breakpoints[i].address == pc && 
nkeynes@736:                 sh4_breakpoints[i].type == type ) {
nkeynes@736:             while( ++i < sh4_breakpoint_count ) {
nkeynes@736:                 sh4_breakpoints[i-1].address = sh4_breakpoints[i].address;
nkeynes@736:                 sh4_breakpoints[i-1].type = sh4_breakpoints[i].type;
nkeynes@736:             }
nkeynes@736:             if( sh4_use_translator ) {
nkeynes@736:                 xlat_invalidate_word( pc );
nkeynes@736:             }
nkeynes@736:             sh4_breakpoint_count--;
nkeynes@736:             return TRUE;
nkeynes@736:         }
nkeynes@378:     }
nkeynes@378:     return FALSE;
nkeynes@378: }
nkeynes@378: 
nkeynes@378: int sh4_get_breakpoint( uint32_t pc )
nkeynes@378: {
nkeynes@378:     int i;
nkeynes@378:     for( i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@736:         if( sh4_breakpoints[i].address == pc )
nkeynes@736:             return sh4_breakpoints[i].type;
nkeynes@378:     }
nkeynes@378:     return 0;
nkeynes@378: }
nkeynes@378: 
nkeynes@401: void sh4_set_pc( int pc )
nkeynes@401: {
nkeynes@401:     sh4r.pc = pc;
nkeynes@401:     sh4r.new_pc = pc+2;
nkeynes@401: }
nkeynes@401: 
nkeynes@401: 
nkeynes@401: /******************************* Support methods ***************************/
nkeynes@401: 
nkeynes@401: static void sh4_switch_banks( )
nkeynes@401: {
nkeynes@401:     uint32_t tmp[8];
nkeynes@401: 
nkeynes@401:     memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 );
nkeynes@401:     memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 );
nkeynes@401:     memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
nkeynes@401: }
nkeynes@401: 
nkeynes@905: void FASTCALL sh4_switch_fr_banks()
nkeynes@669: {
nkeynes@669:     int i;
nkeynes@669:     for( i=0; i<16; i++ ) {
nkeynes@736:         float tmp = sh4r.fr[0][i];
nkeynes@736:         sh4r.fr[0][i] = sh4r.fr[1][i];
nkeynes@736:         sh4r.fr[1][i] = tmp;
nkeynes@669:     }
nkeynes@669: }
nkeynes@669: 
nkeynes@905: void FASTCALL sh4_write_sr( uint32_t newval )
nkeynes@401: {
nkeynes@586:     int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
nkeynes@586:     int newbank = (newval&SR_MDRB) == SR_MDRB;
nkeynes@586:     if( oldbank != newbank )
nkeynes@401:         sh4_switch_banks();
nkeynes@822:     sh4r.sr = newval & SR_MASK;
nkeynes@401:     sh4r.t = (newval&SR_T) ? 1 : 0;
nkeynes@401:     sh4r.s = (newval&SR_S) ? 1 : 0;
nkeynes@401:     sh4r.m = (newval&SR_M) ? 1 : 0;
nkeynes@401:     sh4r.q = (newval&SR_Q) ? 1 : 0;
nkeynes@953:     sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
nkeynes@401:     intc_mask_changed();
nkeynes@401: }
nkeynes@401: 
nkeynes@905: void FASTCALL sh4_write_fpscr( uint32_t newval )
nkeynes@669: {
nkeynes@669:     if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
nkeynes@736:         sh4_switch_fr_banks();
nkeynes@669:     }
nkeynes@823:     sh4r.fpscr = newval & FPSCR_MASK;
nkeynes@953:     sh4r.xlat_sh4_mode = (sh4r.sr & SR_MD) | (sh4r.fpscr & (FPSCR_SZ|FPSCR_PR));
nkeynes@669: }
nkeynes@669: 
nkeynes@905: uint32_t FASTCALL sh4_read_sr( void )
nkeynes@401: {
nkeynes@401:     /* synchronize sh4r.sr with the various bitflags */
nkeynes@401:     sh4r.sr &= SR_MQSTMASK;
nkeynes@401:     if( sh4r.t ) sh4r.sr |= SR_T;
nkeynes@401:     if( sh4r.s ) sh4r.sr |= SR_S;
nkeynes@401:     if( sh4r.m ) sh4r.sr |= SR_M;
nkeynes@401:     if( sh4r.q ) sh4r.sr |= SR_Q;
nkeynes@401:     return sh4r.sr;
nkeynes@401: }
nkeynes@401: 
nkeynes@953: /**
nkeynes@953:  * Raise a CPU reset exception with the specified exception code.
nkeynes@953:  */
nkeynes@953: void FASTCALL sh4_raise_reset( int code )
nkeynes@953: {
nkeynes@953:     MMIO_WRITE(MMU,EXPEVT,code);
nkeynes@953:     sh4r.vbr = 0x00000000;
nkeynes@953:     sh4r.pc = 0xA0000000;
nkeynes@953:     sh4r.new_pc = sh4r.pc + 2;
nkeynes@953:     sh4r.in_delay_slot = 0;
nkeynes@953:     sh4_write_sr( (sh4r.sr|SR_MD|SR_BL|SR_RB|SR_IMASK)&(~SR_FD) );
nkeynes@953:     
nkeynes@953:     /* Peripheral manual reset (FIXME: incomplete) */
nkeynes@953:     INTC_reset();
nkeynes@953:     SCIF_reset();
nkeynes@953:     MMU_reset();
nkeynes@953: }
nkeynes@401: 
nkeynes@953: void FASTCALL sh4_raise_tlb_multihit( sh4vma_t vpn )
nkeynes@953: {
nkeynes@953:     MMIO_WRITE( MMU, TEA, vpn );
nkeynes@953:     MMIO_WRITE( MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)) );
nkeynes@953:     sh4_raise_reset( EXC_TLB_MULTI_HIT );
nkeynes@953: }
nkeynes@401: 
nkeynes@401: /**
nkeynes@401:  * Raise a general CPU exception for the specified exception code.
nkeynes@401:  * (NOT for TRAPA or TLB exceptions)
nkeynes@401:  */
nkeynes@953: void FASTCALL sh4_raise_exception( int code )
nkeynes@401: {
nkeynes@953:     if( sh4r.sr & SR_BL ) {
nkeynes@953:         sh4_raise_reset( EXC_MANUAL_RESET );
nkeynes@401:     } else {
nkeynes@953:         sh4r.spc = sh4r.pc;
nkeynes@953:         sh4r.ssr = sh4_read_sr();
nkeynes@953:         sh4r.sgr = sh4r.r[15];
nkeynes@953:         MMIO_WRITE(MMU,EXPEVT, code);
nkeynes@953:         sh4r.pc = sh4r.vbr + EXV_EXCEPTION;
nkeynes@953:         sh4r.new_pc = sh4r.pc + 2;
nkeynes@953:         sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB );
nkeynes@953:         sh4r.in_delay_slot = 0;
nkeynes@401:     }
nkeynes@401: }
nkeynes@401: 
nkeynes@953: void FASTCALL sh4_raise_trap( int trap )
nkeynes@401: {
nkeynes@953:     MMIO_WRITE( MMU, TRA, trap<<2 );
nkeynes@953:     MMIO_WRITE( MMU, EXPEVT, EXC_TRAP );
nkeynes@953:     sh4r.spc = sh4r.pc;
nkeynes@953:     sh4r.ssr = sh4_read_sr();
nkeynes@953:     sh4r.sgr = sh4r.r[15];
nkeynes@953:     sh4r.pc = sh4r.vbr + EXV_EXCEPTION;
nkeynes@953:     sh4r.new_pc = sh4r.pc + 2;
nkeynes@953:     sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB );
nkeynes@953:     sh4r.in_delay_slot = 0;
nkeynes@953: }
nkeynes@953: 
nkeynes@953: void FASTCALL sh4_raise_tlb_exception( int code, sh4vma_t vpn )
nkeynes@953: {
nkeynes@953:     MMIO_WRITE( MMU, TEA, vpn );
nkeynes@953:     MMIO_WRITE( MMU, PTEH, ((MMIO_READ(MMU, PTEH) & 0x000003FF) | (vpn&0xFFFFFC00)) );
nkeynes@953:     MMIO_WRITE( MMU, EXPEVT, code );
nkeynes@953:     sh4r.spc = sh4r.pc;
nkeynes@953:     sh4r.ssr = sh4_read_sr();
nkeynes@953:     sh4r.sgr = sh4r.r[15];
nkeynes@953:     sh4r.pc = sh4r.vbr + EXV_TLBMISS;
nkeynes@953:     sh4r.new_pc = sh4r.pc + 2;
nkeynes@953:     sh4_write_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB );
nkeynes@953:     sh4r.in_delay_slot = 0;
nkeynes@401: }
nkeynes@401: 
nkeynes@905: void FASTCALL sh4_accept_interrupt( void )
nkeynes@401: {
nkeynes@401:     uint32_t code = intc_accept_interrupt();
nkeynes@953:     MMIO_WRITE( MMU, INTEVT, code );
nkeynes@401:     sh4r.ssr = sh4_read_sr();
nkeynes@401:     sh4r.spc = sh4r.pc;
nkeynes@401:     sh4r.sgr = sh4r.r[15];
nkeynes@401:     sh4_write_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB );
nkeynes@401:     sh4r.pc = sh4r.vbr + 0x600;
nkeynes@401:     sh4r.new_pc = sh4r.pc + 2;
nkeynes@401: }
nkeynes@401: 
nkeynes@905: void FASTCALL signsat48( void )
nkeynes@401: {
nkeynes@401:     if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
nkeynes@736:         sh4r.mac = 0xFFFF800000000000LL;
nkeynes@401:     else if( ((int64_t)sh4r.mac) > (int64_t)0x00007FFFFFFFFFFFLL )
nkeynes@736:         sh4r.mac = 0x00007FFFFFFFFFFFLL;
nkeynes@401: }
nkeynes@401: 
nkeynes@905: void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
nkeynes@401: {
nkeynes@401:     float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
nkeynes@401:     *fr++ = cosf(angle);
nkeynes@401:     *fr = sinf(angle);
nkeynes@401: }
nkeynes@401: 
nkeynes@617: /**
nkeynes@617:  * Enter sleep mode (eg by executing a SLEEP instruction).
nkeynes@617:  * Sets sh4_state appropriately and ensures any stopping peripheral modules
nkeynes@617:  * are up to date.
nkeynes@617:  */
nkeynes@905: void FASTCALL sh4_sleep(void)
nkeynes@401: {
nkeynes@401:     if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
nkeynes@736:         sh4r.sh4_state = SH4_STATE_STANDBY;
nkeynes@736:         /* Bring all running peripheral modules up to date, and then halt them. */
nkeynes@736:         TMU_run_slice( sh4r.slice_cycle );
nkeynes@736:         SCIF_run_slice( sh4r.slice_cycle );
nkeynes@841:         PMM_run_slice( sh4r.slice_cycle );
nkeynes@401:     } else {
nkeynes@736:         if( MMIO_READ( CPG, STBCR2 ) & 0x80 ) {
nkeynes@736:             sh4r.sh4_state = SH4_STATE_DEEP_SLEEP;
nkeynes@736:             /* Halt DMAC but other peripherals still running */
nkeynes@736: 
nkeynes@736:         } else {
nkeynes@736:             sh4r.sh4_state = SH4_STATE_SLEEP;
nkeynes@736:         }
nkeynes@617:     }
nkeynes@740:     sh4_core_exit( CORE_EXIT_SLEEP );
nkeynes@401: }
nkeynes@401: 
nkeynes@401: /**
nkeynes@617:  * Wakeup following sleep mode (IRQ or reset). Sets state back to running,
nkeynes@617:  * and restarts any peripheral devices that were stopped.
nkeynes@617:  */
nkeynes@617: void sh4_wakeup(void)
nkeynes@617: {
nkeynes@617:     switch( sh4r.sh4_state ) {
nkeynes@617:     case SH4_STATE_STANDBY:
nkeynes@736:         break;
nkeynes@617:     case SH4_STATE_DEEP_SLEEP:
nkeynes@736:         break;
nkeynes@617:     case SH4_STATE_SLEEP:
nkeynes@736:         break;
nkeynes@617:     }
nkeynes@617:     sh4r.sh4_state = SH4_STATE_RUNNING;
nkeynes@617: }
nkeynes@617: 
nkeynes@617: /**
nkeynes@617:  * Run a time slice (or portion of a timeslice) while the SH4 is sleeping.
nkeynes@617:  * Returns when either the SH4 wakes up (interrupt received) or the end of
nkeynes@617:  * the slice is reached. Updates sh4.slice_cycle with the exit time and
nkeynes@617:  * returns the same value.
nkeynes@617:  */
nkeynes@617: uint32_t sh4_sleep_run_slice( uint32_t nanosecs )
nkeynes@617: {
nkeynes@617:     int sleep_state = sh4r.sh4_state;
nkeynes@617:     assert( sleep_state != SH4_STATE_RUNNING );
nkeynes@736: 
nkeynes@617:     while( sh4r.event_pending < nanosecs ) {
nkeynes@736:         sh4r.slice_cycle = sh4r.event_pending;
nkeynes@736:         if( sh4r.event_types & PENDING_EVENT ) {
nkeynes@736:             event_execute();
nkeynes@736:         }
nkeynes@736:         if( sh4r.event_types & PENDING_IRQ ) {
nkeynes@736:             sh4_wakeup();
nkeynes@736:             return sh4r.slice_cycle;
nkeynes@736:         }
nkeynes@617:     }
nkeynes@617:     sh4r.slice_cycle = nanosecs;
nkeynes@617:     return sh4r.slice_cycle;
nkeynes@617: }
nkeynes@617: 
nkeynes@617: 
nkeynes@617: /**
nkeynes@401:  * Compute the matrix tranform of fv given the matrix xf.
nkeynes@401:  * Both fv and xf are word-swapped as per the sh4r.fr banks
nkeynes@401:  */
nkeynes@905: void FASTCALL sh4_ftrv( float *target )
nkeynes@401: {
nkeynes@401:     float fv[4] = { target[1], target[0], target[3], target[2] };
nkeynes@669:     target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +
nkeynes@736:     sh4r.fr[1][9]*fv[2] + sh4r.fr[1][13]*fv[3];
nkeynes@669:     target[0] = sh4r.fr[1][0] * fv[0] + sh4r.fr[1][4]*fv[1] +
nkeynes@736:     sh4r.fr[1][8]*fv[2] + sh4r.fr[1][12]*fv[3];
nkeynes@669:     target[3] = sh4r.fr[1][3] * fv[0] + sh4r.fr[1][7]*fv[1] +
nkeynes@736:     sh4r.fr[1][11]*fv[2] + sh4r.fr[1][15]*fv[3];
nkeynes@669:     target[2] = sh4r.fr[1][2] * fv[0] + sh4r.fr[1][6]*fv[1] +
nkeynes@736:     sh4r.fr[1][10]*fv[2] + sh4r.fr[1][14]*fv[3];
nkeynes@401: }
nkeynes@401: 
nkeynes@597: gboolean sh4_has_page( sh4vma_t vma )
nkeynes@597: {
nkeynes@597:     sh4addr_t addr = mmu_vma_to_phys_disasm(vma);
nkeynes@597:     return addr != MMU_VMA_ERROR && mem_has_page(addr);
nkeynes@597: }