nkeynes@550: /**
nkeynes@550:  * $Id: mmu.c,v 1.15 2007-11-08 11:54:16 nkeynes Exp $
nkeynes@550:  * 
nkeynes@550:  * MMU implementation
nkeynes@550:  *
nkeynes@550:  * Copyright (c) 2005 Nathan Keynes.
nkeynes@550:  *
nkeynes@550:  * This program is free software; you can redistribute it and/or modify
nkeynes@550:  * it under the terms of the GNU General Public License as published by
nkeynes@550:  * the Free Software Foundation; either version 2 of the License, or
nkeynes@550:  * (at your option) any later version.
nkeynes@550:  *
nkeynes@550:  * This program is distributed in the hope that it will be useful,
nkeynes@550:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@550:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@550:  * GNU General Public License for more details.
nkeynes@550:  */
nkeynes@550: #define MODULE sh4_module
nkeynes@550: 
nkeynes@550: #include <stdio.h>
nkeynes@550: #include "sh4/sh4mmio.h"
nkeynes@550: #include "sh4/sh4core.h"
nkeynes@550: #include "mem.h"
nkeynes@550: 
nkeynes@550: #define OCRAM_START (0x1C000000>>PAGE_BITS)
nkeynes@550: #define OCRAM_END   (0x20000000>>PAGE_BITS)
nkeynes@550: 
nkeynes@550: #define ITLB_ENTRY_COUNT 4
nkeynes@550: #define UTLB_ENTRY_COUNT 64
nkeynes@550: 
nkeynes@550: /* Entry address */
nkeynes@550: #define TLB_VALID     0x00000100
nkeynes@550: #define TLB_USERMODE  0x00000040
nkeynes@550: #define TLB_WRITABLE  0x00000020
nkeynes@550: #define TLB_SIZE_MASK 0x00000090
nkeynes@550: #define TLB_SIZE_1K   0x00000000
nkeynes@550: #define TLB_SIZE_4K   0x00000010
nkeynes@550: #define TLB_SIZE_64K  0x00000080
nkeynes@550: #define TLB_SIZE_1M   0x00000090
nkeynes@550: #define TLB_CACHEABLE 0x00000008
nkeynes@550: #define TLB_DIRTY     0x00000004
nkeynes@550: #define TLB_SHARE     0x00000002
nkeynes@550: #define TLB_WRITETHRU 0x00000001
nkeynes@550: 
nkeynes@550: 
nkeynes@550: struct itlb_entry {
nkeynes@550:     sh4addr_t vpn; // Virtual Page Number
nkeynes@550:     uint32_t asid; // Process ID
nkeynes@550:     sh4addr_t ppn; // Physical Page Number
nkeynes@550:     uint32_t flags;
nkeynes@550: };
nkeynes@550: 
nkeynes@550: struct utlb_entry {
nkeynes@550:     sh4addr_t vpn; // Virtual Page Number
nkeynes@550:     uint32_t asid; // Process ID
nkeynes@550:     sh4addr_t ppn; // Physical Page Number
nkeynes@550:     uint32_t flags;
nkeynes@550:     uint32_t pcmcia; // extra pcmcia data - not used
nkeynes@550: };
nkeynes@550: 
nkeynes@550: static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
nkeynes@550: static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
nkeynes@550: static uint32_t mmu_urc;
nkeynes@550: static uint32_t mmu_urb;
nkeynes@550: static uint32_t mmu_lrui;
nkeynes@550: 
nkeynes@550: static sh4ptr_t cache = NULL;
nkeynes@550: 
nkeynes@550: static void mmu_invalidate_tlb();
nkeynes@550: 
nkeynes@550: 
nkeynes@550: int32_t mmio_region_MMU_read( uint32_t reg )
nkeynes@550: {
nkeynes@550:     switch( reg ) {
nkeynes@550:     case MMUCR:
nkeynes@550: 	return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26);
nkeynes@550:     default:
nkeynes@550: 	return MMIO_READ( MMU, reg );
nkeynes@550:     }
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void mmio_region_MMU_write( uint32_t reg, uint32_t val )
nkeynes@550: {
nkeynes@550:     switch(reg) {
nkeynes@550:     case PTEH:
nkeynes@550: 	val &= 0xFFFFFCFF;
nkeynes@550: 	break;
nkeynes@550:     case PTEL:
nkeynes@550: 	val &= 0x1FFFFDFF;
nkeynes@550: 	break;
nkeynes@550:     case PTEA:
nkeynes@550: 	val &= 0x0000000F;
nkeynes@550: 	break;
nkeynes@550:     case MMUCR:
nkeynes@550: 	if( val & MMUCR_TI ) {
nkeynes@550: 	    mmu_invalidate_tlb();
nkeynes@550: 	}
nkeynes@550: 	mmu_urc = (val >> 10) & 0x3F;
nkeynes@550: 	mmu_urb = (val >> 18) & 0x3F;
nkeynes@550: 	mmu_lrui = (val >> 26) & 0x3F;
nkeynes@550: 	val &= 0x00000301;
nkeynes@550: 	break;
nkeynes@550:     case CCR:
nkeynes@550: 	mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) );
nkeynes@550: 	break;
nkeynes@550:     default:
nkeynes@550: 	break;
nkeynes@550:     }
nkeynes@550:     MMIO_WRITE( MMU, reg, val );
nkeynes@550: }
nkeynes@550: 
nkeynes@550: 
nkeynes@550: void MMU_init() 
nkeynes@550: {
nkeynes@550:     cache = mem_alloc_pages(2);
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void MMU_reset()
nkeynes@550: {
nkeynes@550:     mmio_region_MMU_write( CCR, 0 );
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void MMU_save_state( FILE *f )
nkeynes@550: {
nkeynes@550:     fwrite( cache, 4096, 2, f );
nkeynes@550:     fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
nkeynes@550:     fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
nkeynes@550: }
nkeynes@550: 
nkeynes@550: int MMU_load_state( FILE *f )
nkeynes@550: {
nkeynes@550:     /* Setup the cache mode according to the saved register value
nkeynes@550:      * (mem_load runs before this point to load all MMIO data)
nkeynes@550:      */
nkeynes@550:     mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
nkeynes@550:     if( fread( cache, 4096, 2, f ) != 2 ) {
nkeynes@550: 	return 1;
nkeynes@550:     }
nkeynes@550:     if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
nkeynes@550: 	return 1;
nkeynes@550:     }
nkeynes@550:     if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) {
nkeynes@550: 	return 1;
nkeynes@550:     }
nkeynes@550:     return 0;
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void mmu_set_cache_mode( int mode )
nkeynes@550: {
nkeynes@550:     uint32_t i;
nkeynes@550:     switch( mode ) {
nkeynes@550:         case MEM_OC_INDEX0: /* OIX=0 */
nkeynes@550:             for( i=OCRAM_START; i<OCRAM_END; i++ )
nkeynes@550:                 page_map[i] = cache + ((i&0x02)<<(PAGE_BITS-1));
nkeynes@550:             break;
nkeynes@550:         case MEM_OC_INDEX1: /* OIX=1 */
nkeynes@550:             for( i=OCRAM_START; i<OCRAM_END; i++ )
nkeynes@550:                 page_map[i] = cache + ((i&0x02000000)>>(25-PAGE_BITS));
nkeynes@550:             break;
nkeynes@550:         default: /* disabled */
nkeynes@550:             for( i=OCRAM_START; i<OCRAM_END; i++ )
nkeynes@550:                 page_map[i] = NULL;
nkeynes@550:             break;
nkeynes@550:     }
nkeynes@550: }
nkeynes@550: 
nkeynes@550: /* TLB maintanence */
nkeynes@550: 
nkeynes@550: /**
nkeynes@550:  * LDTLB instruction implementation. Copies PTEH, PTEL and PTEA into the UTLB
nkeynes@550:  * entry identified by MMUCR.URC. Does not modify MMUCR or the ITLB.
nkeynes@550:  */
nkeynes@550: void MMU_ldtlb()
nkeynes@550: {
nkeynes@550:     mmu_utlb[mmu_urc].vpn = MMIO_READ(MMU, PTEH) & 0xFFFFFC00;
nkeynes@550:     mmu_utlb[mmu_urc].asid = MMIO_READ(MMU, PTEH) & 0x000000FF;
nkeynes@550:     mmu_utlb[mmu_urc].ppn = MMIO_READ(MMU, PTEL) & 0x1FFFFC00;
nkeynes@550:     mmu_utlb[mmu_urc].flags = MMIO_READ(MMU, PTEL) & 0x00001FF;
nkeynes@550:     mmu_utlb[mmu_urc].pcmcia = MMIO_READ(MMU, PTEA);
nkeynes@550: }
nkeynes@550: 
nkeynes@550: uint64_t mmu_translate_read( sh4addr_t addr )
nkeynes@550: {
nkeynes@550:     uint32_t mmucr = MMIO_READ(MMU,MMUCR);
nkeynes@550:     if( IS_SH4_PRIVMODE() ) {
nkeynes@550: 	switch( addr & 0xE0000000 ) {
nkeynes@550: 	case 0x80000000: case 0xA0000000:
nkeynes@550: 	    /* Non-translated read P1,P2 */
nkeynes@550: 	    break;
nkeynes@550: 	case 0xE0000000:
nkeynes@550: 	    /* Non-translated read P4 */
nkeynes@550: 	    break;
nkeynes@550: 	default:
nkeynes@550: 	    if( mmucr&MMUCR_AT ) {
nkeynes@550: 	    } else {
nkeynes@550: 		// direct read
nkeynes@550: 	    }
nkeynes@550: 	}
nkeynes@550:     } else {
nkeynes@550: 	if( addr & 0x80000000 ) {
nkeynes@550: 	    if( ((addr&0xFC000000) == 0xE0000000 ) &&
nkeynes@550: 		((mmucr&MMUCR_SQMD) == 0) ) { 
nkeynes@550: 		// Store queue
nkeynes@550: 		return 0;
nkeynes@550: 	    }
nkeynes@550: //	    MMU_READ_ADDR_ERROR();
nkeynes@550: 	}
nkeynes@550: 	if( mmucr&MMUCR_AT ) {
nkeynes@550: 	    uint32_t vpn = addr & 0xFFFFFC00;
nkeynes@550: 	    uint32_t asid = MMIO_READ(MMU,PTEH)&0xFF;
nkeynes@550: 	} else {
nkeynes@550: 	    // direct read
nkeynes@550: 	}
nkeynes@550:     }
nkeynes@550: }
nkeynes@550: 
nkeynes@550: static void mmu_invalidate_tlb()
nkeynes@550: {
nkeynes@550:     int i;
nkeynes@550:     for( i=0; i<ITLB_ENTRY_COUNT; i++ ) {
nkeynes@550: 	mmu_itlb[i].flags &= (~TLB_VALID);
nkeynes@550:     }
nkeynes@550:     for( i=0; i<UTLB_ENTRY_COUNT; i++ ) {
nkeynes@550: 	mmu_utlb[i].flags &= (~TLB_VALID);
nkeynes@550:     }
nkeynes@550: }
nkeynes@550: 
nkeynes@550: #define ITLB_ENTRY(addr) ((addr>>7)&0x03)
nkeynes@550: 
nkeynes@550: int32_t mmu_itlb_addr_read( sh4addr_t addr )
nkeynes@550: {
nkeynes@550:     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550:     return ent->vpn | ent->asid | (ent->flags & TLB_VALID);
nkeynes@550: }
nkeynes@550: int32_t mmu_itlb_data_read( sh4addr_t addr )
nkeynes@550: {
nkeynes@550:     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550:     return ent->ppn | ent->flags;
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550: {
nkeynes@550:     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550:     ent->vpn = val & 0xFFFFFC00;
nkeynes@550:     ent->asid = val & 0x000000FF;
nkeynes@550:     ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID);
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void mmu_itlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550: {
nkeynes@550:     struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)];
nkeynes@550:     ent->ppn = val & 0x1FFFFC00;
nkeynes@550:     ent->flags = val & 0x00001DA;
nkeynes@550: }
nkeynes@550: 
nkeynes@550: #define UTLB_ENTRY(addr) ((addr>>8)&0x3F)
nkeynes@550: #define UTLB_ASSOC(addr) (addr&0x80)
nkeynes@550: #define UTLB_DATA2(addr) (addr&0x00800000)
nkeynes@550: 
nkeynes@550: int32_t mmu_utlb_addr_read( sh4addr_t addr )
nkeynes@550: {
nkeynes@550:     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550:     return ent->vpn | ent->asid | (ent->flags & TLB_VALID) |
nkeynes@550: 	((ent->flags & TLB_DIRTY)<<7);
nkeynes@550: }
nkeynes@550: int32_t mmu_utlb_data_read( sh4addr_t addr )
nkeynes@550: {
nkeynes@550:     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550:     if( UTLB_DATA2(addr) ) {
nkeynes@550: 	return ent->pcmcia;
nkeynes@550:     } else {
nkeynes@550: 	return ent->ppn | ent->flags;
nkeynes@550:     }
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550: {
nkeynes@550:     if( UTLB_ASSOC(addr) ) {
nkeynes@550:     } else {
nkeynes@550: 	struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550: 	ent->vpn = (val & 0xFFFFFC00);
nkeynes@550: 	ent->asid = (val & 0xFF);
nkeynes@550: 	ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID));
nkeynes@550: 	ent->flags |= (val & TLB_VALID);
nkeynes@550: 	ent->flags |= ((val & 0x200)>>7);
nkeynes@550:     }
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void mmu_utlb_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550: {
nkeynes@550:     struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)];
nkeynes@550:     if( UTLB_DATA2(addr) ) {
nkeynes@550: 	ent->pcmcia = val & 0x0000000F;
nkeynes@550:     } else {
nkeynes@550: 	ent->ppn = (val & 0x1FFFFC00);
nkeynes@550: 	ent->flags = (val & 0x000001FF);
nkeynes@550:     }
nkeynes@550: }
nkeynes@550: 
nkeynes@550: /* Cache access - not implemented */
nkeynes@550: 
nkeynes@550: int32_t mmu_icache_addr_read( sh4addr_t addr )
nkeynes@550: {
nkeynes@550:     return 0; // not implemented
nkeynes@550: }
nkeynes@550: int32_t mmu_icache_data_read( sh4addr_t addr )
nkeynes@550: {
nkeynes@550:     return 0; // not implemented
nkeynes@550: }
nkeynes@550: int32_t mmu_ocache_addr_read( sh4addr_t addr )
nkeynes@550: {
nkeynes@550:     return 0; // not implemented
nkeynes@550: }
nkeynes@550: int32_t mmu_ocache_data_read( sh4addr_t addr )
nkeynes@550: {
nkeynes@550:     return 0; // not implemented
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void mmu_icache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550: {
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void mmu_icache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550: {
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val )
nkeynes@550: {
nkeynes@550: }
nkeynes@550: 
nkeynes@550: void mmu_ocache_data_write( sh4addr_t addr, uint32_t val )
nkeynes@550: {
nkeynes@550: }