nkeynes@231: .section .text
nkeynes@231: .include "sh4/inc.s"
nkeynes@231: !
nkeynes@231: ! Test for all cases that raise a slot-illegal exception (according to the SH4
nkeynes@231: ! manual). See Page 103 of the Hitachi manual
nkeynes@231: 
nkeynes@231: .global _test_slot_illegal
nkeynes@231: _test_slot_illegal:	
nkeynes@231: 	start_test
nkeynes@231: 
nkeynes@231: ! First the easy ones - instructions not permitted in delay slots at any
nkeynes@231: ! time:
nkeynes@231: ! JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA,
nkeynes@231: ! LDC (to SR), MOV pcrel, MOVA
nkeynes@231: !
nkeynes@231: ! Note that the tests use BSR as the branch instruction, and assume it
nkeynes@231: ! functions correctly.
nkeynes@231: 	
nkeynes@231: test_slot_1:	!JMP
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_1_pc:	
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	jmp @r3
nkeynes@231: 	assert_exc_caught test_slot_str_k1 test_slot_1_pc
nkeynes@231: 
nkeynes@231: test_slot_2:	! JSR
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_2_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	jsr @r3
nkeynes@231: 	assert_exc_caught test_slot_str_k1 test_slot_2_pc
nkeynes@231: 	
nkeynes@231: test_slot_3:	! BRA
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_3_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	bra test_slot_fail
nkeynes@233: 	assert_exc_caught test_slot_str_k1 test_slot_3_pc
nkeynes@231: 
nkeynes@231: test_slot_4:	! BRAF
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_4_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	braf r3
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_4_pc
nkeynes@231: 
nkeynes@231: test_slot_5:	! BSR
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_5_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_5_pc
nkeynes@231: 
nkeynes@231: test_slot_6:	! BSRF
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_6_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	bsrf r3
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_6_pc
nkeynes@231: 
nkeynes@231: test_slot_7:	! BF
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_7_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	bf test_slot_7_fail
nkeynes@231: test_slot_7_fail:	
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_7_pc
nkeynes@231: 
nkeynes@231: test_slot_8:	! BT
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_8_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	bt test_slot_8_fail
nkeynes@231: test_slot_8_fail:	
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_8_pc
nkeynes@231: 
nkeynes@231: test_slot_9:	! BF/S
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_9_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	bf/s test_slot_9_fail
nkeynes@231: test_slot_9_fail:	
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_9_pc
nkeynes@231: 
nkeynes@231: test_slot_10:	! BT/S
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_10_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	bt/s test_slot_10_fail
nkeynes@231: test_slot_10_fail:	
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_10_pc
nkeynes@233: 	bra test_slot_11
nkeynes@233: 	nop
nkeynes@233: test_slot_str_k1:
nkeynes@233: 	.long test_slot_str
nkeynes@231: 
nkeynes@233: 	
nkeynes@231: test_slot_11:	! TRAPA
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_11_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	trapa #12
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_11_pc
nkeynes@231: 
nkeynes@231: test_slot_12:	! LDC r0, sr
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: 	stc sr, r0
nkeynes@231: test_slot_12_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	ldc r0, sr
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_12_pc
nkeynes@231: 
nkeynes@231: test_slot_13:	! LDC @r0, sr
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: 	stc sr, r1
nkeynes@231: 	mova test_slot_13_temp, r0
nkeynes@231: 	mov.l r1, @r0
nkeynes@231: test_slot_13_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	ldc.l @r0+, sr
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_13_pc
nkeynes@231: 	bra test_slot_14
nkeynes@231: 	nop
nkeynes@231: test_slot_13_temp:
nkeynes@231: 	.long 0
nkeynes@231: 	
nkeynes@231: test_slot_14:	! MOVA
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_14_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	mova test_slot_15, r0
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_14_pc
nkeynes@231: 
nkeynes@231: test_slot_15:	! MOV.W pcrel, Rn
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_15_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	mov.w test_slot_16, r0
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_15_pc
nkeynes@231: 
nkeynes@231: test_slot_16:	! MOV.L pcrel, Rn
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_16_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	mov.l test_slot_str_k, r0
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_16_pc
nkeynes@231: 
nkeynes@231: test_slot_17:	! "Undefined" 0xFFFD
nkeynes@231: 	add #1, r12
nkeynes@231: 	expect_exc 0x000001A0
nkeynes@231: test_slot_17_pc:
nkeynes@231: 	bsr test_slot_fail
nkeynes@231: 	.word 0xFFFD
nkeynes@231: 	assert_exc_caught test_slot_str_k test_slot_17_pc
nkeynes@231: 
nkeynes@231: !
nkeynes@231: ! Ok now the privilege tests. These should raise SLOT_ILLEGAL when executed
nkeynes@231: ! in a delay slot (otherwise it's GENERAL_ILLEGAL)
nkeynes@233: 
nkeynes@233: test_slot_18:   ! LDC Rn, SPC in user mode
nkeynes@233: 	add #1, r12
nkeynes@233: 	expect_exc 0x000001A0
nkeynes@233: 	stc spc, r4
nkeynes@233: 	usermode
nkeynes@233: test_slot_18_pc:
nkeynes@233: 	bsr test_slot_fail
nkeynes@233: 	ldc r4, spc
nkeynes@233: 	systemmode
nkeynes@233: 	assert_exc_caught test_slot_str_k test_slot_18_pc
nkeynes@231: 	
nkeynes@233: 		
nkeynes@231: test_slot_end:
nkeynes@231: 	end_test test_slot_str_k
nkeynes@231: 
nkeynes@231: ! Returns after the delay slot, which should hit the "no exception" test
nkeynes@231: test_slot_fail:
nkeynes@231: 	rts
nkeynes@231: 	nop
nkeynes@231: 
nkeynes@231: test_slot_str_k:
nkeynes@231: 	.long test_slot_str
nkeynes@231: test_slot_str:
nkeynes@231: 	.string "SLOT-ILLEGAL"
nkeynes@231: 
nkeynes@231: